CN104993837A - Convolutional interleaving method and convolutional interleaver - Google Patents
Convolutional interleaving method and convolutional interleaver Download PDFInfo
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Abstract
The invention discloses a convolutional interleaving method and device. The method comprises the following steps of: initializing an address offset of each branch of convolutional interleaving in a SDRAM(Synchronous Dynamic Random Access Memory) to be B-1; while performing the convolutional interleaving, adding an initial address of each branch of the convolutional interleaving and a current address offset of the branch together to obtain an actual access address of data of the branch in the SDRAM; when the address offset of the ith branch of convolutional interleaving in the SDRAM is equal to (i-1)*M, resetting the address offset of the ith branch to be B-1, wherein B is the total number of the branches of the convolutional interleaving, i is a positive integer not less than 2 and not more than B, and M is interleaving depth of the convolutional interleaving. The method realizes shorter address hop among the branches in the convolutional interleaving process, greatly reduces trans-regional hop of addresses while accessing data in the SDRAM, and then realizes high-efficiency time domain convolutional interleaving, so that a clock period for processing one superframe is reduced obviously; and in comparison with the existing design, the method may improve a throughput rate by 64%.
Description
Technical field
The present invention relates to digital television techniques, particularly a kind of method that interweaves of convolution of carrying out in SDRAM and convolutional deinterleaver.
Background technology
Interleaving technology is an indispensable part in mobile communication system.The effect of interleaver is upset by the sending order of data or data block, and object is the burst error that minimizing data or data block occur in transport process.
Convolutional interleave is the one of interleaving technology.The memory capacity of typical convolutional deinterleaver needs is B × (B-1) × M/2 symbolic unit, and wherein B is intertexture number of branches, is also referred to as weaving width, and M is the interleaver delay cycle, is also referred to as interleave depth, and its principle as shown in Figure 1.
As shown in Figure 1, in convolutional deinterleaver, total B is capable, represents B branch road.Wherein the 1st branch road directly exports, without the need to buffer memory.As can be seen from Figure 1, the memory capacity needed for convolutional deinterleaver is B × (B-1) × M/2 symbolic unit.Interleaving process is: original data stream inputs from left side, the input of each bit (bit) data flow in left side in bit stream enters the 1st branch road in order successively in B branch road, the symbol period that each finger delays is different, 1st branch road is without delay (namely directly exporting), export after a 2nd finger delays M symbol period, export after a 3rd finger delays 2M symbol period ... export after B finger delays (B-1) M symbol period, the interleaving data of each branch road exports from right side.
China digital television standard DTMB (Digital Television Terrestrial Multimedia Broadcasting, digital TV ground multimedia broadcasting) apply convolutional interleave in standard and interweave as time domain, wherein adopt 52 branch roads, i.e. B=52, interleave depth is 240 or 720 symbols, i.e. M=240 or M=720.
When B and M value is larger, uses on-chip memory resource consumption excessive, employing cost is low, capacity is large, fast SDRAM is a kind of solution preferably.
SDRAM (Synchronous Dynamic Random Access Memory, synchronous DRAM) be developed so far and experienced by several generations, comprise the SDR SDRAM of the first generation, the DDR SDRAM of the second generation, the DDR2SDRAM of the third generation, the DDR3SDRAM of forth generation and higher to devices such as DDR5.The technology access chip internal unit that SDRAM utilizes rank addresses multiplexing, have employed many bodies (Bank) memory construction and burst mode, a monoblock instead of one piece of data can be transmitted continuously, there is very large using value in high-speed data acquistion system.
SDRAM's is each for memory, all there are two features:
1, address strobe needs first gating row address, then other addresses of gating, if there is address saltus step frequently, then can cause very large expense;
2, the read-write of SDRAM memory all adopts burst mode, and namely burst is read, and burst is write, and burst length differs, and is generally 4 or 8.
The 1st feature for above-mentioned SDRAM memory:
In order to improve the performance of SDRAM memory, internal memory operating efficiency must be improved, the time proportion shared by operation such as namely reduction addressing.To be read as example to internal memory, when non-data is transmitted, having three important parameters, is tRCD, CL and tRP respectively; Wherein, tRCD determines the interval between row addressing (effectively) to row addressing (read/write command), CL determines row and is addressed to data and is really read the spent time, and tRP then determines the speed of the capable conversion of different operating in identical L-Bank (logic Bank).Here is for once reading the 3 kinds of situations run at random:
1) want the row of addressing and L-Bank to be idle.Namely all row of this L-Bank are closed, and now can directly send row effective order, and always consuming time before digital independent be tRCD+CL, and this situation is referred to as page and hits (PH, Page Hit).
2) want the row of addressing to be just in time the working line of previous operation, namely the row of addressing is wanted to be in gating effective status, now can directly send row addressed command, always consuming time before digital independent is only CL, addressing that Here it is so-called (Back to Back) back-to-back, be referred to as page and hit (PFH, Page Fast Hit) or page direct hit (PDH, Page Direct Hit) fast.
3) want in the L-Bank at the row place of addressing, had a row to be in active state (closedown), this phenomenon is referred to as addressing conflicts, now must carry out precharge to close working line, then sends row effective order to newline.The always consuming time of this situation is tRP+tRCD+CL, and this situation is referred to as page and misses (PM, Page Miss).
Obviously, above-mentioned 2nd kind of situation and PFH are optimal addressing situations, and the 3rd kind of situation and PM are then the addressing situations of worst.The probability that above-mentioned 3 kinds of situations occur can separately referred to as PHR---PH Rate, PFHR---PFH Rate and PMR---PM Rate.Therefore, in order to improve internal memory operating efficiency, needing to improve PHR and PFHR as much as possible, reducing PMR simultaneously.
The 2nd feature for above-mentioned SDRAM memory:
After an effective address A enters SDRAM memory inside, it exports as continuous print burst length BL (being generally 4 or 8) individual data, and when to get BL be 4, namely OPADD is A, A+1, A+2, the data of A+3.
Convolutional interleave scheme in China's Digital Television comes from " People's Republic of China's radio, film and television industry standard " " ground digital television broadcast exciter technical requirement and method of measurement ", hereinafter GB.Schematic diagram is realized as shown in Figure 2 in GB.
In Fig. 2, the data stored in actual register are carried out piecemeal according to different fill pattern, different fill patterns represents the deposit position of the data of different branch in intertexture register, and identical style represents the data deposited continuously in intertexture register.In convolutional interleave process, as shown in Figure 2, the memory address of the intertexture register of each branch road is all one section of continuous print address; And between adjacent legs, the memory address of intertexture register each other and discontinuous.According to interleaving principle, export the data for each branch road enters at first, namely the rightmost position of each fill pattern memory block.
Interleave parameter is
M＝240×(2
M_PAR-1)
Wherein, M_PAR is mode selection parameter, M_PAR desirable 1 or 2.
The input of interleaver adopts one-to-many switch, and the data of serial input are sent into interleaver according to clockwise direction.Wherein the Article 1 branch road of interleaver connects for straight-through, namely exports without time delay.Have the intertexture Parasites Fauna of 51 row downwards, wherein, the data depth of i-th group is i × M, i is the integer of 1 to 51, namely when M_PAR is 1: the degree of depth of the intertexture Parasites Fauna of the 2nd branch road is 1 × 240=240, the degree of depth of the intertexture Parasites Fauna of the 3rd branch road is 2 × 240=480, and the degree of depth of the intertexture Parasites Fauna of the 4th branch road is 3 × 240=720, the rest may be inferred, and the degree of depth of the intertexture Parasites Fauna of the 52nd branch road is 51 × 240=12240.Thus the register number required for intertexture Parasites Fauna of an interleaver is:
Visible, for the output (farthest right position of the intertexture register of each fill pattern is each output) of convolutional deinterleaver, its address change is very violent, an integral multiple address change of difference M.
Can find out in conjunction with the convolutional interleave scheme in the access feature of above-mentioned SDRAM and existing Digital Television, if according to the interleaving scheme in existing GB when SDRAM device carries out convolutional interleave, need the change of the interleaving address writing RAM very violent, thus cause the wrong rate PMR of very high page, and can not utilize the characteristic of its burst read-write completely, overall performance will be greatly affected.
In a word, in prior art, in Digital Television leading portion system, it is larger that convolutional interleave module needs to store data volume, if adopt the SDRAM of low cost, due to convolutional interleave, can affect its efficiency read and write data greatly.
Summary of the invention
In view of this, the invention provides a kind of method of convolutional interleave, to realize high-efficiency time domain convolutional interleave in SDRAM.
The technical scheme of the application is achieved in that
A kind of convolutional interleave method, for SDRAM memory, the method comprises:
The address offset of each branch road in SDRAM of convolutional interleave is initialized as B-1;
When carrying out convolutional interleave:
The initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road;
When the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × M, the address offset of this i-th branch road is reset to B-1;
Wherein, B is total circuitry number of described convolutional interleave, and i is the positive integer being more than or equal to 2 and being less than or equal to B, and M is the interleave depth of described convolutional interleave.
Further, B is 52, M is 240 or 720.
Further, in described convolutional interleave process, the 1st branch road of described convolutional interleave directly exports, without the access of described SDRAM.
Further, the initialization address of each branch road of described convolutional interleave in SDRAM and address offset are obtained by triangle Parasites Fauna, an offset address registers group and a column address register group on one; Wherein,
Described upper triangle Parasites Fauna comprises the capable and B-1 column register of B-1, i-th column register of described upper triangle register corresponds to the i-th branch road in described convolutional interleave, 1st row register of described upper triangle register is output register, initialization of register on the first row register of described upper triangle register and leading diagonal is " 1 ", and all the other registers are all initialized as " 0 ";
In described convolutional interleave process, when the actual access address of the i-th branch road in described convolutional interleave in SDRAM reaches (i-1) × M, the data upward displacement of the i-th column register of described upper triangle register once, and in the data shifts of the top register in the i-th column register to register bottom;
Described offset address registers group is made up of B-1 offset address registers, the i-th branch road wherein in the corresponding convolutional interleave of the i-th offset address registers, and the value of all B-1 offset address registers is all initialized as B-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the i-th offset address registers subtracts 1, when the value of the i-th column address register of column address register group corresponding to the i-th branch road in convolutional interleave is (i-1) × M, and the value of output register in i-th of described upper triangle Parasites Fauna the row is when being 1, the value of the i-th offset address registers is reset to B-1;
Described column address register group is made up of B-1 column address register, the i-th branch road wherein in the corresponding convolutional interleave of the i-th column address register, and in described column address register group, the value of the i-th column address register is initialized as i-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the value of the i-th column address register and the i-th offset address registers is added, and the numerical value after being added is updated in the i-th column address register, and then using the data actual access address among SDRAMs of the value of the i-th column address register after renewal as the i-th branch road.
A kind of convolutional deinterleaver, comprising:
Selector, with input-buffer with export buffer memory and be connected, the data for the 1st branch road by convolutional interleave send to output buffer memory, and the 2nd branch road of convolutional interleave is sent to input-buffer to the data of B branch road;
Input-buffer, is connected to sdram controller, for the 2nd branch road of convolutional interleave is sent to sdram controller to the data of B branch road;
Access address maker, for being initialized as B-1 by the address offset of each branch road in SDRAM of convolutional interleave; When carrying out convolutional interleave, the initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road, and then the actual access address of the data of each branch road in SDRAM is sent to sdram controller, receive Data Concurrent from sdram controller and give output buffer memory, wherein, when the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × M, the address offset of this i-th branch road is reset to B-1;
Sdram controller, for receiving each branch data from input-buffer, the actual access address of each branch road convolutional interleave is received from access address maker, and then produce the operation address of SDRAM, according to described operation address, the data in SDRAM are read from SDRAM, then the data received from input-buffer are stored in SDRAM;
SDRAM, is connected with described sdram controller, for storing each branch data of convolution interleaving data;
Export buffer memory, for receiving the data of the 1st branch road of convolutional interleave from described selector, and obtain the data of the 2nd branch road to B branch road of convolutional interleave from access address maker, and obtained data are exported;
Wherein, B is total circuitry number of described convolutional interleave, and i is the positive integer being more than or equal to 2 and being less than or equal to B, and M is the interleave depth of described convolutional interleave.
Further, B is 52, M is 240 or 720.
Further, comprise triangle Parasites Fauna on, an offset address registers group and a column address register group in the maker of described access address, initialization address in SDRAM of each branch road of described convolutional interleave and address offset are determined by triangle Parasites Fauna, offset address registers group and column address register group on described; Wherein,
Described upper triangle Parasites Fauna comprises the capable and B-1 column register of B-1, i-th column register of described upper triangle register corresponds to the i-th branch road in described convolutional interleave, 1st row register of described upper triangle register is output register, initialization of register on the first row register of described upper triangle register and leading diagonal is " 1 ", and all the other registers are all initialized as " 0 ";
In described convolutional interleave process, when the actual access address of the i-th branch road in described convolutional interleave in SDRAM reaches the integral multiple of M or M, the data upward displacement of the i-th column register of described upper triangle register once, and in the data shifts of the top register in the i-th column register to register bottom;
Described offset address registers group is made up of B-1 offset address registers, the i-th branch road wherein in the corresponding convolutional interleave of the i-th offset address registers, and the value of all B-1 offset address registers is all initialized as B-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the i-th offset address registers subtracts 1, when the value of the i-th column address register of column address register group corresponding to the i-th branch road in convolutional interleave is (i-1) × M, and the value of output register in i-th of described upper triangle Parasites Fauna the row is when being 1, the value of the i-th offset address registers is reset to B-1;
Described column address register group is made up of B-1 column address register, the i-th branch road wherein in the corresponding convolutional interleave of the i-th column address register, and in described column address register group, the value of the i-th column address register is initialized as i-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the value of the i-th column address register and the i-th offset address registers is added, and the numerical value after being added is updated in the i-th column address register, and then using the data actual access address among SDRAMs of the value of the i-th column address register after renewal as the i-th branch road.
As can be seen from such scheme, convolutional interleave method and apparatus of the present invention achieves lower ground location saltus step between each branch road in convolutional interleave process, greatly reduce transregional saltus step of address during visit data in SDRAM, and then realize efficient convolution intertexture, the clock cycle processing superframe used obviously reduces, contrast existing design, promoting throughput can reach 64%.
Accompanying drawing explanation
Fig. 1 is existing convolutional deinterleaver schematic diagram;
Fig. 2 is the convolutional deinterleaver implementation principle schematic in GB;
Fig. 3 is the principle schematic of convolutional deinterleaver of the present invention;
Fig. 4 is convolutional interleave method flow block diagram of the present invention;
Fig. 5 for adopt in the embodiment of the present invention upper triangle Parasites Fauna initialization time schematic diagram.
Fig. 6 for adopt in the embodiment of the present invention the initialization of offset address registers group time schematic diagram;
Fig. 7 for adopt in the embodiment of the present invention the initialization of column address register group time schematic diagram;
The convolutional deinterleaver schematic diagram that Fig. 8 provides for the embodiment of the present invention;
The convolutional deinterleaver electrical block diagram that Fig. 9 provides for the embodiment of the present invention;
Figure 10 is the address analogous diagram of existing convolutional interleave method;
Figure 11 is the partial enlarged drawing of Figure 10;
Figure 12 is the address analogous diagram of convolutional interleave method of the present invention;
Figure 13 is the partial enlarged drawing of the beginning of Figure 12;
Figure 14 is partial enlarged drawing when certain resets in Figure 12.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
Be illustrated in figure 3 convolutional deinterleaver principle schematic of the present invention.In Fig. 3, the intertexture register of same fill pattern represents continuous print address space in SDRAM, such as, in Fig. 3 input first row intertexture register in, the data flow of input enters the intertexture register of the 2nd branch road to each branch road in B branch road in order successively, and to enter the 2nd branch road to the actual deposit position of data flow in SDRAM of the intertexture register of each branch road in B branch road be one section of continuous print memory space.Unlike the prior art, in convolutional interleave Method And Principle of the present invention, the data being input to each branch road are stored in continuously one section of memory space of SDRAM from the 2nd branch road to B branch road, and in same branch road the memory address of adjacent intertexture register is each other and discontinuous; And in prior art, as shown in Figure 2, in same branch road, the memory address of adjacent intertexture register is one section of continuous print address, the memory address of the intertexture register of the adjacent legs in the same row in Fig. 2 each other and discontinuous.
Based on the convolutional deinterleaver principle shown in Fig. 3, convolutional interleave method of the present invention, for SDRAM memory, as shown in Figure 4, the method comprises:
The address offset of each branch road in SDRAM of convolutional interleave is initialized as B-1;
When carrying out convolutional interleave:
The initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road;
When the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × M, the address offset of this i-th branch road is reset to B-1;
Wherein, B is total circuitry number of described convolutional interleave, and i is the positive integer being more than or equal to 2 and being less than or equal to B, and M is the interleave depth of described convolutional interleave, and the i-th branch road represents from the 2nd branch road to any one article of branch road B branch road.
In order to adapt to and compatible China digital television standard, i.e. DTMB standard, B is wherein taken as 52, M and is taken as 240 or 720.
When B get 52, M get 240 time, namely total circuitry number of described convolutional interleave is 52, the interleave depth of described convolutional interleave is when being 240, and the inventive method comprises:
The address offset of each branch road in SDRAM of convolutional interleave is initialized as 51;
When carrying out convolutional interleave:
The initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road;
When the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × 240, the address offset of this i-th branch road is reset to 51;
Wherein, i be more than or equal to 2 and be less than or equal to 52 positive integer, the i-th branch road represents from the 2nd branch road to any one article of branch road the 52nd branch road.
Shown in Figure 3, in method of the present invention, the address offset of each branch road in SDRAM of convolutional interleave is initialized as B-1, address offset by the 2nd branch road institute's memory address in SDRAM is set to B-1=52-1=51, the address offset of the 3rd branch road institute's memory address in SDRAM is set to B-1=52-1=51, the rest may be inferred, and the address offset of the 52nd branch road institute's memory address in SDRAM is set to B-1=52-1=51.
The inventive method is in convolutional interleave process, and the 1st branch road of convolutional interleave directly exports, and without the access of SDRAM, in SDRAM, does not also have its initialization address and address offset.
In the inventive method embodiment, the initialization address of each branch road in SDRAM and address offset, obtained by triangle Parasites Fauna, an offset address registers group and a column address register group on one.
Wherein, as shown in Figure 5, described upper triangle Parasites Fauna comprises B-1 (such as 51) row and B-1 (such as 51) column register.Wherein, i-th column register of upper triangle register corresponds to the i-th branch road in described convolutional interleave, 1st row register of upper triangle register is output register, initialization of register on the first row register of upper triangle register and leading diagonal is " 1 ", and all the other registers are all initialized as " 0 ".In convolutional interleave process, when the actual access address of the i-th branch road in convolutional interleave in SDRAM reaches the integral multiple of M or M, on this, the data upward displacement of the i-th column register of triangle register once, and in the data shifts of the top register in the i-th column register to register bottom, as shown in the direction of arrow in Fig. 5.
As shown in Figure 6, offset address registers group is made up of B-1 (such as 51) individual offset address registers, the i-th branch road wherein in the corresponding convolutional interleave of the i-th offset address registers, namely the i-th offset address registers corresponds to the i-th column register of upper triangle register, and the value of all B-1 offset address registers is all initialized as B-1 (such as 51).After the operation completing the i-th branch data in a convolutional interleave, the value of the i-th offset address registers subtracts 1, when the value of the i-th column address register of column address register group corresponding to the i-th branch road in convolutional interleave is (i-1) × M (M such as 240), and the value of output register (these the i-th row register topmost) in i-th of upper triangle Parasites Fauna the row is when being 1, the value of the i-th offset address registers is reset to B-1 (such as 51).
As shown in Figure 7, column address register group is made up of B-1 (such as 51) individual column address register, the i-th branch road wherein in the corresponding convolutional interleave of the i-th column address register, i.e. the i-th column register of corresponding i-th offset address registers of the i-th column address register and upper triangle register, in described column address register group, the value of the i-th column address register is initialized as i-1, such as, the value of the 2nd column address register is initialized as 1, the value of the 3rd column address register is initialized as 2, the rest may be inferred, the value of B (such as 51) column address register is initialized as B-1 (such as 51).After the operation completing the i-th branch data in a convolutional interleave, the value of the value of the i-th column address register and the i-th offset address registers is added, and the numerical value after being added is updated in the i-th column address register, and then using the data actual access address among SDRAMs of the value of the i-th column address register after renewal as the i-th branch road.Such as, after the operation completing order 2 branch data, the value of the value of the 2nd column address register and the 2nd offset address registers is added, and the numerical value after being added is updated in the 2nd column address register, and then using the data actual access address among SDRAMs of the value of the 2nd column address register after renewal as the 2nd branch road, after the operation completing order 3 branch data, the value of the value of the 3rd column address register and the 3rd offset address registers is added, and the numerical value after being added is updated in the 3rd column address register, and then using the data actual access address among SDRAMs of the value of the 3rd column address register after renewal as the 3rd branch road, the rest may be inferred, after the operation completing an order B branch data, the value of the value of B column address register and B offset address registers is added, and the numerical value after being added is updated in B column address register, and then using the data actual access address among SDRAMs of the value of the B column address register after renewal as B branch road.
Embodiments provide a kind of convolutional deinterleaver, as shown in Figure 8, it comprises, selector S, input-buffer cache1, access address maker addr, output buffer memory cache2, sdram controller driver and SDRAM.
Wherein, selector S and input-buffer cache1 and exports buffer memory cache2 and be connected, the data for the 1st branch road by convolutional interleave send to output buffer memory cache2, and the 2nd branch road of convolutional interleave is sent to input-buffer cache1 to the data of B branch road.
Input-buffer cache1 is also connected with sdram controller driver, for the 2nd branch road of convolutional interleave is sent to sdram controller driver to the data of B branch road.
Access address maker addr also with output buffer memory cache2, for the address offset of each branch road in SDRAM of convolutional interleave is initialized as B-1; When carrying out convolutional interleave, the initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road, and then the actual access address of the data of each branch road in SDRAM is sent to sdram controller driver, receive Data Concurrent from sdram controller driver and give output buffer memory cache2, wherein, when the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × M, the address offset of this i-th branch road is reset to B-1.
Sdram controller driver, for receiving each branch data from input-buffer cache1, the actual access address of each branch road convolutional interleave is received from access address maker addr, and then produce the operation address of SDRAM, according to described operation address, the data in SDRAM are read from SDRAM, then the data received from input-buffer cache1 are stored in SDRAM.
SDRAM, is connected with sdram controller driver, for storing each branch data of convolution interleaving data.
Export buffer memory cache2, for receiving the data of the 1st branch road of convolutional interleave from selector S, and obtain the data of the 2nd branch road to B branch road of convolutional interleave from access address maker addr, and obtained data are exported.Wherein, B is total circuitry number of described convolutional interleave, and i is the positive integer being more than or equal to 2 and being less than or equal to B, and M is the interleave depth of described convolutional interleave.
Wherein, comprise triangle Parasites Fauna on, an offset address registers group and a column address register group in the maker addr of access address, initialization address in SDRAM of each branch road of convolutional interleave and address offset are determined by triangle Parasites Fauna, offset address registers group and column address register group on described.
As shown in Figure 5, upper triangle Parasites Fauna comprises the capable and B-1 column register of B-1, wherein the i-th column register corresponds to the i-th branch road in described convolutional interleave, 1st row register is output register, register wherein on the first row register and leading diagonal is all initialized as " 1 ", and all the other registers are all initialized as " 0 ".In convolutional interleave process, when the actual access address of the i-th branch road in convolutional interleave in SDRAM reaches (i-1) × M, the data upward displacement of the i-th column register of described upper triangle register once, and in the data shifts of the top register in the i-th column register to register bottom.
As shown in Figure 6, offset address registers group is made up of B-1 offset address registers, and the i-th branch road wherein in the corresponding convolutional interleave of the i-th offset address registers, the value of all B-1 offset address registers is all initialized as B-1.After the operation completing the i-th branch data in a convolutional interleave, the value of the i-th offset address registers subtracts 1, when the value of the i-th column address register of column address register group corresponding to the i-th branch road in convolutional interleave is (i-1) × M, and the value of output register in i-th of described upper triangle Parasites Fauna the row is when being 1, the value of the i-th offset address registers is reset to B-1;
As shown in Figure 7, column address register group is made up of B-1 column address register, and the i-th branch road wherein in the corresponding convolutional interleave of the i-th column address register, in described column address register group, the value of the i-th column address register is initialized as i-1.After the operation completing the i-th branch data in a convolutional interleave, the value of the value of the i-th column address register and the i-th offset address registers is added, and the numerical value after being added is updated in the i-th column address register, and then using the data actual access address among SDRAMs of the value of the i-th column address register after renewal as the i-th branch road.
For coordinating the work of modules in convolutional deinterleaver of the present invention, also have other interlock circuit structure in convolutional deinterleaver, Fig. 9 is appliance electrical block diagram provided by the present invention.Convolutional deinterleaver, except having selector S as above, input-buffer cache1, access address maker addr, exporting except buffer memory cache2 and SDRAM, also has the first counter cnt 51, second counter cnt 52, first address generator Gen1, the second address generator Gen2 and controller ctrl.
Wherein, the first counter cnt 51 connects the first address generator Gen1, and the count range of the first counter cnt 51 is 0 ~ 50 (totally 51), for counting the data being sent to input-buffer cache1.
First address generator Gen1 also connects addra end and the controller ctrl and selector S of input-buffer cache1 respectively, for sending the 2nd branch road of write input-buffer cache1 to input-buffer cache1 to the write address of B branch data, send control signal thro to controller ctrl and selector S.
The data of the 1st branch road of convolutional interleave directly send to and export buffer memory cache2 by selector S under the triggering of control signal thro, and the 2nd branch road of convolutional interleave is sent to input-buffer cache1 to the data of B branch road.
Be sent to the data of input-buffer cache1 from selector S, write in the input-buffer write address that the first address generator Gen1 produces.
Second counter cnt 52 connects the second address generator Gen2, and the count range of the second counter cnt 52 is 1 ~ 51 (totally 51), for counting being sent to the data exporting buffer memory cache2.
Second address generator Gen2 also connects output buffer memory cache2 and controller ctrl respectively, with first via through connect signal in Dominating paths input signal in the storage exported in buffer memory cache2 and the output exporting buffer memory cache2, and send the write enable signal of the storage of first via through connect signal in output buffer memory cache2 in input signal to controller ctrl.
Controller ctrl also connects the wea end exporting buffer memory cache2, for the control signal thro that sends at the first address generator Gen1 and the second address generator Gen2 send read to send to output buffer memory cache2 under the control of address signal read command signal.
Access address maker addr connects the web terminal, addrb end and the dinb end that export buffer memory cache2, and the data only exported for control SDRAM are stored into and export buffer memory cache2.
With B=52, M=240 for example, the course of work embodiment illustrated in fig. 9 is as follows.
Data input: carry out the input data of convolutional interleave by the frame structure selector S being input to the convolutional deinterleaver shown in Fig. 9 one by one, by selector S, frame data are optionally sent to input-buffer cache1 and output buffer memory cache2, particularly, it is cycle count 0 ~ 51 from the 1st branch data of each Frame, wherein, 1st branch data (being counted as 0) is directly sent into by selector S and is exported buffer memory cache2, 2nd ~ 52 branch roads (being counted as 1 ~ 51) send into input-buffer cache1 by selector S, so just complete a frame 3744 data and (amount to 52 branch roads, each branch road is 72 data) input the operation of convolutional deinterleaver.
The write of SDRAM data and reading: access address maker addr produces the actual access address of each branch road in convolutional interleave, each branch data of input-buffer cache1 is read in sdram controller driver, the control signal that the address translation that access address maker addr produces becomes SDRAM to identify according to the physical characteristic of SDRAM by sdram controller driver, and then produce the operation address of SDRAM, and according to this operation address, the data that convolutional interleave current in SDRAM will read are read from SDRAM, and send to access address maker addr, and then be stored in output buffer memory cache2 by access address maker addr, then each branch data in sdram controller driver is stored in SDRAM, wherein, include from SDRAM reading data and data be stored into SDRAM two processes:
Read data from SDRAM: will the data reading SDRAM be stored according to the order of correspondence, and be stored in output buffer memory cache2 by access address maker addr;
Data are stored into SDRAM: by the data of each branch road in input-buffer cache1 according to specifically to sequentially read and stored in SDRAM;
Data export: the second address generator Gen2 produces the reading address exporting buffer memory cache2, order according to 0 ~ 3743 reads the data in output buffer memory cache2 successively and exports, and then will be positioned at the data of reading address from douta end output convolutional deinterleaver in output buffer memory cache2.
Owing to having certain uncertainty when SDRAM works, the first counter cnt _ 51 counting operation needs the enable signal (such as local_ready, out_valid etc.) coordinating SDRAM to return to count or latch.First counter cnt _ 51 another input access local_ready and out_valid signal phase and result.Such as, work as local_ready=1, during out_valid=1, the first counter cnt _ 51 work, and work as local_ready, when in out_valid, any one is zero, the first counter cnt _ 51 do not work, and namely suspend counting.
Figure 10 is the address analogous diagram of existing convolutional interleave method, Figure 11 is the partial enlarged drawing of Figure 10, Figure 12 is the address analogous diagram of convolutional interleave method of the present invention, Figure 13 is the partial enlarged drawing of the beginning of Figure 12, Figure 14 is partial enlarged drawing when certain resets in Figure 12, can find out in contrast from Figure 10 to Figure 14 that convolutional interleave method and apparatus of the present invention achieves lower ground location saltus step between each branch road in convolutional interleave process, greatly reduce transregional saltus step of address during visit data in SDRAM, and then realize efficient convolution intertexture, the clock cycle processing superframe used obviously reduces, contrast existing design, promote throughput and can reach 64%.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (7)
1. a convolutional interleave method, for SDRAM memory, the method comprises:
The address offset of each branch road in SDRAM of convolutional interleave is initialized as B-1;
When carrying out convolutional interleave:
The initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road;
When the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × M, the address offset of this i-th branch road is reset to B-1;
Wherein, B is total circuitry number of described convolutional interleave, and i is the positive integer being more than or equal to 2 and being less than or equal to B, and M is the interleave depth of described convolutional interleave.
2. convolutional interleave method according to claim 1, is characterized in that: B is 52, M is 240 or 720.
3. convolutional interleave method according to claim 1, is characterized in that: in described convolutional interleave process, and the 1st branch road of described convolutional interleave directly exports, without the access of described SDRAM.
4. convolutional interleave method according to claim 1, is characterized in that:
Initialization address in SDRAM of each branch road of described convolutional interleave and address offset are obtained by triangle Parasites Fauna, an offset address registers group and a column address register group on one; Wherein,
Described upper triangle Parasites Fauna comprises the capable and B-1 column register of B-1, i-th column register of described upper triangle register corresponds to the i-th branch road in described convolutional interleave, 1st row register of described upper triangle register is output register, initialization of register on the first row register of described upper triangle register and leading diagonal is " 1 ", and all the other registers are all initialized as " 0 ";
In described convolutional interleave process, when the actual access address of the i-th branch road in described convolutional interleave in SDRAM reaches (i-1) × M, the data upward displacement of the i-th column register of described upper triangle register once, and in the data shifts of the top register in the i-th column register to register bottom;
Described offset address registers group is made up of B-1 offset address registers, the i-th branch road wherein in the corresponding convolutional interleave of the i-th offset address registers, and the value of all B-1 offset address registers is all initialized as B-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the i-th offset address registers subtracts 1, when the value of the i-th column address register of column address register group corresponding to the i-th branch road in convolutional interleave is (i-1) × M, and the value of output register in i-th of described upper triangle Parasites Fauna the row is when being 1, the value of the i-th offset address registers is reset to B-1;
Described column address register group is made up of B-1 column address register, the i-th branch road wherein in the corresponding convolutional interleave of the i-th column address register, and in described column address register group, the value of the i-th column address register is initialized as i-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the value of the i-th column address register and the i-th offset address registers is added, and the numerical value after being added is updated in the i-th column address register, and then using the data actual access address among SDRAMs of the value of the i-th column address register after renewal as the i-th branch road.
5. a convolutional deinterleaver, is characterized in that, comprising:
Selector, with input-buffer with export buffer memory and be connected, the data for the 1st branch road by convolutional interleave send to output buffer memory, and the 2nd branch road of convolutional interleave is sent to input-buffer to the data of B branch road;
Input-buffer, is connected to sdram controller, for the 2nd branch road of convolutional interleave is sent to sdram controller to the data of B branch road;
Access address maker, for being initialized as B-1 by the address offset of each branch road in SDRAM of convolutional interleave; When carrying out convolutional interleave, the initialization address of each branch road of described convolutional interleave is added the current address skew of this branch road, as the actual access address of data in SDRAM of this branch road, and then the actual access address of the data of each branch road in SDRAM is sent to sdram controller, receive Data Concurrent from sdram controller and give output buffer memory, wherein, when the address offset of the i-th branch road in SDRAM in described convolutional interleave equals (i-1) × M, the address offset of this i-th branch road is reset to B-1;
Sdram controller, for receiving each branch data from input-buffer, the actual access address of each branch road convolutional interleave is received from access address maker, and then produce the operation address of SDRAM, according to described operation address, the data in SDRAM are read from SDRAM, then the data received from input-buffer are stored in SDRAM;
SDRAM, is connected with described sdram controller, for storing each branch data of convolution interleaving data;
Export buffer memory, for receiving the data of the 1st branch road of convolutional interleave from described selector, and obtain the data of the 2nd branch road to B branch road of convolutional interleave from access address maker, and obtained data are exported;
Wherein, B is total circuitry number of described convolutional interleave, and i is the positive integer being more than or equal to 2 and being less than or equal to B, and M is the interleave depth of described convolutional interleave.
6. convolutional deinterleaver according to claim 5, is characterized in that: B is 52, M is 240 or 720.
7. convolutional deinterleaver according to claim 5, is characterized in that:
Comprise triangle Parasites Fauna on, an offset address registers group and a column address register group in the maker of described access address, initialization address in SDRAM of each branch road of described convolutional interleave and address offset are determined by triangle Parasites Fauna, offset address registers group and column address register group on described; Wherein,
Described upper triangle Parasites Fauna comprises the capable and B-1 column register of B-1, i-th column register of described upper triangle register corresponds to the i-th branch road in described convolutional interleave, 1st row register of described upper triangle register is output register, initialization of register on the first row register of described upper triangle register and leading diagonal is " 1 ", and all the other registers are all initialized as " 0 ";
In described convolutional interleave process, when the actual access address of the i-th branch road in described convolutional interleave in SDRAM reaches (i-1) × M, the data upward displacement of the i-th column register of described upper triangle register once, and in the data shifts of the top register in the i-th column register to register bottom;
Described offset address registers group is made up of B-1 offset address registers, the i-th branch road wherein in the corresponding convolutional interleave of the i-th offset address registers, and the value of all B-1 offset address registers is all initialized as B-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the i-th offset address registers subtracts 1, when the value of the i-th column address register of column address register group corresponding to the i-th branch road in convolutional interleave is (i-1) × M, and the value of output register in i-th of described upper triangle Parasites Fauna the row is when being 1, the value of the i-th offset address registers is reset to B-1;
Described column address register group is made up of B-1 column address register, the i-th branch road wherein in the corresponding convolutional interleave of the i-th column address register, and in described column address register group, the value of the i-th column address register is initialized as i-1;
After the operation completing the i-th branch data in a convolutional interleave, the value of the value of the i-th column address register and the i-th offset address registers is added, and the numerical value after being added is updated in the i-th column address register, and then using the data actual access address among SDRAMs of the value of the i-th column address register after renewal as the i-th branch road.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108073548A (en) * | 2016-11-14 | 2018-05-25 | 耐能股份有限公司 | Convolution algorithm device and convolution algorithm method |
| CN108228492A (en) * | 2016-12-21 | 2018-06-29 | 深圳市中兴微电子技术有限公司 | A kind of multichannel DDR intertexture control method and device |
| CN109525255A (en) * | 2017-09-18 | 2019-03-26 | 华为技术有限公司 | Deinterleaving method and interlaced device |
| CN109816093A (en) * | 2018-12-17 | 2019-05-28 | 北京理工大学 | A kind of one-way convolution implementation method |
| CN111831328A (en) * | 2019-04-18 | 2020-10-27 | 华为技术有限公司 | Data processing method and device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030097621A1 (en) * | 2001-11-12 | 2003-05-22 | Weizhuang Xin | Efficient address generation for interleaver and de-interleaver |
| CN1638287A (en) * | 2004-02-03 | 2005-07-13 | 上海奇普科技有限公司 | Convolution interleaving and de-interleaving method in digital transmission |
| US20070061667A1 (en) * | 2005-09-13 | 2007-03-15 | Chia-Chun Lin | Convolutional interleaving and de-interleaving circuit and method thereof |
| CN101204014A (en) * | 2005-06-22 | 2008-06-18 | 适应性频谱和信号校正股份有限公司 | Dynamic minimum-memory interleaving |
| CN101488763A (en) * | 2008-01-18 | 2009-07-22 | 卓胜微电子（上海）有限公司 | Deinterleaving method for DTMB symbols |
| CN101674093A (en) * | 2009-09-28 | 2010-03-17 | 北京海尔集成电路设计有限公司 | Two-stage realization method of convolutional interleave and device thereof |
| CN101697491A (en) * | 2009-10-15 | 2010-04-21 | 浙江大学 | Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM |
| CN102006087A (en) * | 2010-11-11 | 2011-04-06 | 福州大学 | Convolutional interleaving method and device based on static random access memory (SRAM) |
-
2015
- 2015-07-24 CN CN201510442028.5A patent/CN104993837B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030097621A1 (en) * | 2001-11-12 | 2003-05-22 | Weizhuang Xin | Efficient address generation for interleaver and de-interleaver |
| CN1638287A (en) * | 2004-02-03 | 2005-07-13 | 上海奇普科技有限公司 | Convolution interleaving and de-interleaving method in digital transmission |
| CN101204014A (en) * | 2005-06-22 | 2008-06-18 | 适应性频谱和信号校正股份有限公司 | Dynamic minimum-memory interleaving |
| US20070061667A1 (en) * | 2005-09-13 | 2007-03-15 | Chia-Chun Lin | Convolutional interleaving and de-interleaving circuit and method thereof |
| CN101488763A (en) * | 2008-01-18 | 2009-07-22 | 卓胜微电子（上海）有限公司 | Deinterleaving method for DTMB symbols |
| CN101674093A (en) * | 2009-09-28 | 2010-03-17 | 北京海尔集成电路设计有限公司 | Two-stage realization method of convolutional interleave and device thereof |
| CN101697491A (en) * | 2009-10-15 | 2010-04-21 | 浙江大学 | Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM |
| CN102006087A (en) * | 2010-11-11 | 2011-04-06 | 福州大学 | Convolutional interleaving method and device based on static random access memory (SRAM) |
Non-Patent Citations (1)
| Title |
|---|
| 洪波 等: "DVB 系统中卷积交织器的设计与实现", 《通信技术》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108073548A (en) * | 2016-11-14 | 2018-05-25 | 耐能股份有限公司 | Convolution algorithm device and convolution algorithm method |
| CN108073548B (en) * | 2016-11-14 | 2021-09-10 | 耐能股份有限公司 | Convolution operation device and convolution operation method |
| CN108228492A (en) * | 2016-12-21 | 2018-06-29 | 深圳市中兴微电子技术有限公司 | A kind of multichannel DDR intertexture control method and device |
| CN109525255A (en) * | 2017-09-18 | 2019-03-26 | 华为技术有限公司 | Deinterleaving method and interlaced device |
| CN109525255B (en) * | 2017-09-18 | 2022-04-05 | 华为技术有限公司 | Interleaving method and interleaving apparatus |
| CN109816093A (en) * | 2018-12-17 | 2019-05-28 | 北京理工大学 | A kind of one-way convolution implementation method |
| CN109816093B (en) * | 2018-12-17 | 2020-12-04 | 北京理工大学 | Single-path convolution implementation method |
| CN111831328A (en) * | 2019-04-18 | 2020-10-27 | 华为技术有限公司 | Data processing method and device |
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|---|---|
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Denomination of invention: A Convolutional Interleaving Method and Convolutional Interleaver Effective date of registration: 20230417 Granted publication date: 20180803 Pledgee: Lishui branch of Bank of Hangzhou Co.,Ltd. Pledgor: LISHUI BOYUAN TECHNOLOGY Co.,Ltd. Registration number: Y2023980038020 |