CN102437896B - Bit interleaving and constellation mapping method and apparatus thereof - Google Patents
Bit interleaving and constellation mapping method and apparatus thereof Download PDFInfo
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Abstract
The invention provides a bit interleaving and constellation mapping method and an apparatus thereof. The method comprises the following steps: (1) storing configuration information corresponding to a selected modulation mode in bit interleaving and constellation mapping; (2) selecting a corresponding storage array according to the configuration information; (3) sending received data to be interleaved to the storage array, carrying out interleaving on data through the storage array, directly and parallelly outputting the interleaved data, and carrying out constellation mapping on the interleaved data, wherein, bit width of the interleaved data which is outputted directly and parallelly is same with a bit number of each symbol in the constellation mapping. Accordingly, in the invention, after carrying out bit interleaving, the interleaved data can be outputted directly and parallelly, the bit width of the interleaved data which is outputted directly and parallelly is same with the bit number of each symbol in the constellation mapping, thus subsequent constellation mapping can be carried out directly, and complexity of a device is substantially reduced.
Description
Technical field
The invention belongs to communication technical field, be specifically related to method and the device of a kind of Bit Interleave and constellation mapping.
Background technology
Along with the development of the communication technology, terminal use improves constantly for the requirement of system reliability, and especially at moving communicating field, the transmitting procedure of digital signal often can be attended by all kinds of interference sources, thereby makes signal produce distortion, affects communication quality.
Error correction coding can be corrected the random error of the digital information sequence of the random disturbances generation in channel.But, only utilize error correction coding, for the bursty interference in transmitting procedure, need to can increase like this complexity of coder by means of very long code word, also can produce larger time delay simultaneously.
Bit Interleave technology is as a mode of improving communication system performance, its groundwork principle is: Bit data is upset according to certain rule, the error code that original gathering is in blocks disperses, thereby make unexpected error be converted into randomness mistake, like this, error code number after error correction is within the scope of the error correction of error correcting code, and receiving terminal just can carry out error correction by shorter code word.
In prior art, the structure of common bit interleaver comprises: control unit, RAM (RAM-Random Access Memory, random asccess memory).The satellite transmission standard DVB-S2 (ETSI En 302307) of take is example, the course of work of bit interleaver is wherein: RAM is with hocket write and read operation of ping-pong, (m is line number as m*n to take RAM, n is columns) storage matrix is that example describes, specifically comprise the following steps: (1) need to carry out after the bit data flow of Bit Interleave when control unit receives first, first this bit data flow is write to RAM in row mode, that is: to the 1st, be listed as the 1st row and write the 1st Bit data, to the 1st, be listed as the 2nd row and write the 2nd Bit data, the rest may be inferred, until be listed as to the 1st, m is capable writes m Bit data, then, be listed as the 1st row write m+1 bit to the 2nd, until be listed as to n, m is capable writes m*n Bit data.During this period, RAM is for writing state; (2) when RAM write full after, control module changes RAM into read states, with line mode from RAM sense data, from the 1st row the 1st row, read the 1st Bit data, the 1st row the 2nd row are read the 2nd Bit data, and the rest may be inferred, until read n Bit data from the 1st row n row; Then, from the 2nd row the 1st row, read n+1 bit, until read m*n bit from the capable n row of m.Thereby realize the object that Bit data is interweaved.
In realizing process of the present invention, inventor finds, at least has following problem in prior art:
(1) because the RAM in bit interleaver is with hocket write and read operation of ping-pong, write in one way after completely whole memory capacity again sense data in another way, the valid data throughput of whole module only has half of operating frequency, that is to say that operating frequency must be 2 times of data throughput.Take 8PSK modulation mode as example, 3 times of data throughput is-symbol rate, 6 of operating frequency is-symbol rate times, symbol rate for 45M, requiring the operating frequency of module is 45*6=270MHz, and these all devices for this module have proposed very high requirement, thereby have increased device cost.
(2) due to the stage hocketing write and read operation, must use line address counter and column address counter respectively row and column address to be increased progressively to computing, thereby increase equipment complexity.
(3) data due to bit interleaver output are that bit wide is the serial bit stream of 1, must go here and there and change, thereby increased equipment complexity and cost when carrying out subsequent bits constellation mapping.
Summary of the invention
The defect existing for prior art, the invention provides method and the device of a kind of Bit Interleave and constellation mapping, after carrying out Bit Interleave, the direct data of parallel output after interweaving, and, the bit wide of the data after the interweaving of parallel output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping, and do not need extra use string conversion operations, thereby significantly reduced the complexity of device.
The technical solution adopted in the present invention is as follows:
A kind of method that the invention provides Bit Interleave and constellation mapping, comprises the following steps:
(1) stored bits interweaves and the configuration information corresponding with selected modulating mode during constellation mapping;
(2) according to described configuration information, select corresponding storage array;
(3) interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after direct parallel output interweaves, then carry out constellation mapping to the data after interweaving; When wherein, the bit wide of the data after the interweaving of parallel output is with constellation mapping, the bit number of each symbol is identical.
Preferably, in step (1), selected modulating mode comprises: 8PSK, 16APSK, 32APSK.
Preferably, described configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
Preferably, when interleave depth is the capable * n of m row, wherein, m represents the bit number information of each symbol when corresponding frame length information, the n of the modulating mode with selecting in described configuration information represents the constellation mapping in described configuration information; In step (2), according to described configuration information, select corresponding storage array to be specially: determined storage array is comprised of n-1 memory module, the degree of depth of each memory module is m; Wherein, the numbering of a described n-1 memory module be respectively A1, A2 ... An-1.
Preferably, described memory module is that bit wide is the asynchronous FIFO of 1.
Preferably, in step (3), the interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after direct parallel output interweaves, then carry out constellation mapping to the data after interweaving, and are specially:
(1) in memory module A1, memory module A2... memory module An-1, by row, write full Bit data successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, is m capable;
(2) the capable Bit data of m and outside directly 1 Bit data of input in while parallel read-out memory module A1, memory module A2... memory module An-1, form the parallel bit being comprised of n Bit data and flow;
(3) parallel bit stream step (2) being obtained carries out follow-up constellation mapping, simultaneously, continue to receive 1 new Bit data of outside input, then parallel read-out memory module A1, the capable data of m-1 in memory module A2... memory module An-1, repeat above-mentioned steps m time, until parallel read-out memory module A1, in memory module A2... memory module An-1, the 1st line number is according to this and during the outside m sending 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
The present invention also provides the device of a kind of Bit Interleave and constellation mapping, it is characterized in that, comprising: control module, dynamic-configuration module, storage array and constellation mapping module;
Wherein, described dynamic-configuration module interweaves for stored bits and the configuration information corresponding with selected modulating mode during constellation mapping, and this configuration information is sent to described control module;
Storage array is the corresponding storage array of selecting according to described configuration information;
Described control module is used for: the interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after directly interweaving to described constellation mapping module parallel output; Wherein, then the data after interweaving are carried out to constellation mapping; When wherein, the bit wide of the data after the interweaving of parallel output is with constellation mapping, the bit number of each symbol is identical.
Described constellation mapping module for to receive interweave after data carry out constellation mapping.
Preferably, selected modulating mode comprises: 8PSK, 16APSK, 32APSK.
Preferably, described configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
Preferably, when interleave depth is the capable * n of m row, wherein, m represents the bit number information of each symbol when corresponding frame length information, the n of the modulating mode with selecting in described configuration information represents the constellation mapping in described configuration information; In step (2), according to described configuration information, select corresponding storage array to be specially: determined storage array is comprised of n-1 memory module, the degree of depth of each memory module is m; Wherein, the numbering of a described n-1 memory module be respectively A1, A2 ... An-1.
Preferably, described memory cell is that bit wide is the asynchronous FIFO of 1.
Preferably, described control module also for:
(1) in memory module A1, memory module A2... memory module An-1, by row, write full Bit data successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, is m capable;
(2) the capable Bit data of m and outside directly 1 Bit data of input in while parallel read-out memory module A1, memory module A2... memory module An-1, form the parallel bit being comprised of n Bit data and flow;
(3) parallel bit stream step (2) being obtained carries out follow-up constellation mapping, simultaneously, continue to receive 1 new Bit data of outside input, then parallel read-out memory module A1, the capable data of m-1 in memory module A2... memory module An-1, repeat above-mentioned steps m time, until parallel read-out memory module A1, in memory module A2... memory module An-1, the 1st line number is according to this and during the outside m sending 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
Beneficial effect of the present invention is as follows:
(1) method of Bit Interleave provided by the invention and constellation mapping and device, after carrying out Bit Interleave, the direct data of parallel output after interweaving, and, the bit wide of the data after the interweaving of parallel output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping, and not need extra use string conversion operations, thereby significantly reduce the complexity of device.
(2) because the present invention is when carrying out Bit Interleave, the storage array that the storage array adopting is comprised of 1 asynchronous FIFO, and do not need to use line address counter and column address counter respectively row and column address to be increased progressively to computing, thereby further reduced equipment complexity.
(3) due in interleaving mode provided by the invention, when interleave depth is the capable * n of m row, only need to wait for that the individual bit write operation of m* (n-1) completes, just can carry out follow-up parallel work-flow, and do not need to wait for after all m*n bits are all write full data and just carry out output function, thereby the operating efficiency that has improved Bit Interleave and constellation mapping, has reduced operating frequency.
(4) in the present invention, when needs interweave to m*n Bit data, only need to use the individual memory cell of m* (n-1), compare with m*n memory cell of satellite transmission standard DVB-S2 regulation, reduce the number of m memory cell, thereby reduced device cost.
(5), in the present invention, by changing the degree of depth and the quantity of each memory cell in configuration information and storage array, go for different modulating pattern, thereby improved the versatility of equipment.
Accompanying drawing explanation
The schematic flow sheet of a kind of Bit Interleave that Fig. 1 provides for the embodiment of the present invention and the method for constellation mapping;
The structural representation of a kind of Bit Interleave that Fig. 2 provides for the embodiment of the present invention and the device of constellation mapping.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described.
Embodiment mono-
The embodiment of the present invention provides a kind of method of Bit Interleave and constellation mapping, as shown in Figure 1, comprises the following steps:
Step 101, stored bits interweaves and the configuration information corresponding with selected modulating mode during constellation mapping.
Concrete, the configuration information corresponding with selected modulating mode comprises but is not limited to: the bit number information of each symbol during with frame length information corresponding to the modulating mode of selecting, constellation mapping.And, the method of Bit Interleave provided by the invention and constellation mapping can be applied in different modulating modes, for example: 8PSK (8 Phase Shift Keying, 8 phase-shift keyings)), 16APSK (16 Amplitude Phase Shift Keying, 16 amplitude-phase shift keyings), 32APSK (32 Amplitude Phase Shift Keying, 32 amplitude-phase shift keyings) etc.As shown in table 1, in existing standard, the bit number information of each symbol when the frame length information that various modulating modes are corresponding, constellation mapping.
Table 1
Step 102, selects corresponding storage array according to described configuration information.
In order to match with the regulation of existing standard, in the present invention, the various parameters of storage array are determined by configuration information corresponding to selected modulating mode.Further, storage array is comprised of a plurality of memory modules, and the frame length information in configuration information has determined the degree of depth of memory module, and during constellation mapping in configuration information, the bit number information of each symbol has determined the quantity of memory module in storage array.
Concrete, when interleave depth is the capable * n of m row, wherein, m represents the bit number information of each symbol when corresponding frame length information, the n of the modulating mode with selecting in described configuration information represents the constellation mapping in described configuration information; In step (2), according to described configuration information, select corresponding storage array to be specially: determined storage array is comprised of n-1 memory module, the degree of depth of each memory module is m; Wherein, the numbering of a described n-1 memory module be respectively A1, A2 ... An-1.
For example: when the modulating mode of selecting is 16APSK, under 16APSK modulating mode, the frame length of long frame is 16200, during constellation mapping, the bit number of each symbol is 4, therefore, selected storage array is comprised of 3 memory modules, that is: memory module A1, memory module A2, memory module A3, and the degree of depth of each memory module A3 is 21600.
The complexity of device during for further reduction Bit Interleave and constellation mapping, it is asynchronous FIFO (the First Input First Output of 1 that the type of memory module can be selected bit wide, First Input First Output), because adding 1 automatically by inside read-write pointer, the data address of asynchronous FIFO completes, and do not need to use outside to read to determine address wire as normal memory, do not count, thus the complexity of device in the time of can reducing Bit Interleave.
For example: when the modulating mode of selecting is 8PSK, under 8PSK modulating mode, the frame length of long frame is 21600, during constellation mapping, the bit number of each symbol is 3, therefore, selected storage array is comprised of 2 asynchronous FIFOs, that is: asynchronous FIFO 1, asynchronous FIFO 2, wherein, the degree of depth of asynchronous FIFO 1 and asynchronous FIFO 2 is 21600.
In this step, with standard gauge phasing ratio, reduced the number of memory cell, thereby reduced device cost.Take 8PSK as example, with respect to standard regulation, reduced by 21600 memory cell, and standard compares, reduced by 1/3 device cost.As shown in table 2, under various modulating modes, the method and apparatus of Bit Interleave provided by the invention and constellation mapping is with respect to the improvement of standard regulation.
Table 2
And, by changing the degree of depth and the quantity of each memory cell in configuration information and storage array, go for different modulating pattern, thereby improved the versatility of equipment.
Step 103, sends to described storage array by the interleaving data for the treatment of receiving, and by described storage array, data is interweaved, and the data after direct parallel output interweaves, then carry out constellation mapping to the data after interweaving; When wherein, the bit wide of the data after the interweaving of parallel output is with constellation mapping, the bit number of each symbol is identical.
Concrete interleaving mode comprises the following steps:
(1) successively to memory module A1, memory module A2 ... in memory module An-1, by row, write full Bit data, wherein, memory module A1, memory module A2 ... it is capable that the line number in memory module An-1 is m;
(2) simultaneously parallel read-out memory module A1, memory module A2 ... in memory module An-1, according to this and outside directly 1 Bit data of input, the parallel bit that formation is comprised of n Bit data flows m line number;
(3) parallel bit stream step (2) being obtained carries out follow-up constellation mapping, simultaneously, continue to receive outside 1 the new Bit data sending, then parallel read-out memory module A1, memory module A2, ... the capable data of m-1 in memory module An-1, repeat above-mentioned steps m time, until parallel read-out memory module A1, memory module A2, ... in memory module An-1, the 1st line number is according to this and during the outside m sending 1 Bit data, that is: memory module A1, memory module A2, ... when memory module An-1 is sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
For example: when the modulating mode of selecting is 8PSK, the storage array of selection is comprised of 2 asynchronous FIFOs, that is: asynchronous FIFO 1, asynchronous FIFO 2, wherein, the degree of depth of asynchronous FIFO 1 and asynchronous FIFO 2 is 21600.Interleaving mode comprises the following steps:
(1) to asynchronous FIFO 1, asynchronous FIFO 2, by row, write full Bit data successively, wherein, the line number of asynchronous FIFO 1, asynchronous FIFO 2 is the degree of depth, is 21600 row.
Concrete, in asynchronous FIFO 1, write after full 21600 Bit datas, then write full 21600 Bit datas in asynchronous FIFO 2.
(2) simultaneously the 21600th line number according to this and 1 Bit data of outside input, forms the parallel bit being comprised of 3 Bit datas and flows in parallel read-out asynchronous FIFO 1, asynchronous FIFO 2;
(3) the 3 parallel-by-bit bit streams that step (2) obtained carry out follow-up constellation mapping, simultaneously, continuation writes 1 new Bit data the 2nd time from outside, then with parallel read-out asynchronous FIFO 1, the 21599th row data in asynchronous FIFO 2, obtain 3 new parallel-by-bit bit streams and carry out follow-up constellation mapping, repeat above-mentioned steps 21600 times, until parallel read-out asynchronous FIFO 1, when in asynchronous FIFO 2, the 1st line number is according to this and from outside 1 Bit data writing for the 21600th time, that is: asynchronous FIFO 1, when asynchronous FIFO 2 is sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
In sum, the method for Bit Interleave provided by the invention and constellation mapping, has the following advantages:
(1) after carrying out Bit Interleave, the direct data of parallel output after interweaving, and, the bit wide of the data after the interweaving of parallel output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping, and do not need extra use string conversion operations, thereby significantly reduced the complexity of device.
(2) because the present invention is when carrying out Bit Interleave, the storage array that the storage array adopting is comprised of 1 asynchronous FIFO, and do not need to use line address counter and column address counter respectively row and column address to be increased progressively to computing, thereby further reduced equipment complexity.
(3) due in interleaving mode provided by the invention, when interleave depth is the capable * n of m row, only need to wait for that the individual bit write operation of m* (n-1) completes, just can carry out follow-up parallel work-flow, and do not need to wait for after all m*n bits are all write full data and just carry out output function, thereby the operating efficiency that has improved Bit Interleave and constellation mapping, has reduced operating frequency.
(4) in the present invention, when needs interweave to m*n Bit data, only need to use the individual memory cell of m* (n-1), compare with m*n memory cell of satellite transmission standard DVB-S2 regulation, reduce the number of m memory cell, thereby reduced device cost.
(5), in the present invention, by changing the degree of depth and the quantity of each memory cell in configuration information and storage array, go for different modulating pattern, thereby improved the versatility of equipment.
Embodiment bis-
A kind of Bit Interleave that the embodiment of the present invention provides and the device of constellation mapping, comprising: control module, dynamic-configuration module, storage array and constellation mapping module; Introduce respectively operation principle and the course of work of each module below.
(1) dynamic-configuration module
Dynamic-configuration module interweaves for stored bits and the configuration information corresponding with selected modulating mode during constellation mapping, and this configuration information is sent to described control module.Wherein, selected modulating mode comprises: 8PSK, 16APSK, 32APSK.Described configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
(2) storage array
Storage array is the corresponding storage array of selecting according to described configuration information.
Concrete, when interleave depth is the capable * n of m row, wherein, m represents the bit number information of each symbol when corresponding frame length information, the n of the modulating mode with selecting in described configuration information represents the constellation mapping in described configuration information; In step (2), according to described configuration information, select corresponding storage array to be specially: determined storage array is comprised of n-1 memory module, the degree of depth of each memory module is m; Wherein, the numbering of a described n-1 memory module be respectively A1, A2 ... An-1.Wherein, memory cell can be the asynchronous FIFO of 1 for bit wide.
(3) control module
Control module is used for: the interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after directly interweaving to described constellation mapping module parallel output; Wherein, then the data after interweaving are carried out to constellation mapping; When wherein, the bit wide of the data after the interweaving of parallel output is with constellation mapping, the bit number of each symbol is identical.
The specific works flow process of described control module comprises the following steps:
(1) successively to memory module A1, memory module A2 ... in memory module An-1, by row, write full Bit data, wherein, memory module A1, memory module A2 ... it is capable that the line number in memory module An-1 is m;
(2) simultaneously parallel read-out storage unit A 1, storage unit A 2 ... in storage unit A n-1, m line number according to this and 1 Bit data of outside input, forms the parallel bit being comprised of n Bit data and flows;
(3) parallel bit stream step (2) being obtained sends to described constellation mapping module, thereby carry out follow-up constellation mapping, simultaneously, continuation writes 1 new Bit data the 2nd time in storage unit A n, then parallel read-out storage unit A 1, storage unit A 2, ... 1 the new Bit data of m-1 line number according to this and in storage unit A n in storage unit A n-1, repeat above-mentioned steps m time, until parallel read-out storage unit A 1, storage unit A 2, ... in storage unit A n-1, the 1st line number is according to this and during 1 Bit data writing for the m time in storage unit A n, that is: storage unit A 1, storage unit A 2, ... when storage unit A n-1 and storage unit A n are sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
(4) constellation mapping module
Constellation mapping module for to receive interweave after data carry out constellation mapping.
As shown in Figure 2, a kind of Bit Interleave providing for the embodiment of the present invention and the device of constellation mapping, wherein, the modulating mode of selecting is 8PSK, the storage array of selecting is comprised of 2 asynchronous FIFOs, that is: asynchronous FIFO 1, asynchronous FIFO 2, wherein, the degree of depth of asynchronous FIFO 1 and asynchronous FIFO 2 is 21600.
In sum, the device of Bit Interleave provided by the invention and constellation mapping, after carrying out Bit Interleave, the direct data of parallel output after interweaving, and, the bit wide of the data after the interweaving of parallel output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping, and do not need extra use string conversion operations, thereby significantly reduced the complexity of device.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be looked protection scope of the present invention.
Claims (6)
1. a method for Bit Interleave and constellation mapping, is characterized in that, comprises the following steps:
(1) stored bits interweaves and the configuration information corresponding with selected modulating mode during constellation mapping;
(2) according to described configuration information, select corresponding storage array;
(3) interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after direct parallel output interweaves, then carry out constellation mapping to the data after interweaving; When wherein, the bit wide of the data after the interweaving of parallel output is with constellation mapping, the bit number of each symbol is identical;
Described configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping;
When interleave depth is the capable * n of m row, wherein, m represents the bit number information of each symbol when corresponding frame length information, the n of the modulating mode with selecting in described configuration information represents the constellation mapping in described configuration information; In step (2), according to described configuration information, select corresponding storage array to be specially: selected storage array is comprised of n-1 memory module, the degree of depth of each memory module is m; Wherein, the numbering of a described n-1 memory module be respectively A1, A2 ... An-1;
In step (3), the interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after direct parallel output interweaves, then carry out constellation mapping to the data after interweaving, and are specially:
S31 writes full Bit data by row successively in memory module A1, memory module A2... memory module An-1, and wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, is m capable;
S32, the capable Bit data of m and outside directly 1 Bit data of input in parallel read-out memory module A1, memory module A2... memory module An-1, form the parallel bit being comprised of n Bit data and flow simultaneously;
S33, the parallel bit stream that S32 is obtained carries out follow-up constellation mapping, simultaneously, continue to receive 1 new Bit data of outside input, then parallel read-out memory module A1, the capable data of m-1 in memory module A2... memory module An-1, repeat above-mentioned S31-S33 step m time, until parallel read-out memory module A1, in memory module A2... memory module An-1, the 1st line number is according to this and during the outside m sending 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
2. the method for Bit Interleave according to claim 1 and constellation mapping, is characterized in that, in step (1), selected modulating mode comprises: 8PSK, 16APSK or 32APSK.
3. the method for Bit Interleave according to claim 1 and constellation mapping, is characterized in that, described memory module is that bit wide is the asynchronous FIFO of 1.
4. a device for Bit Interleave and constellation mapping, is characterized in that, comprising: control module, dynamic-configuration module, storage array and constellation mapping module;
Wherein, described dynamic-configuration module interweaves for stored bits and the configuration information corresponding with selected modulating mode during constellation mapping, and this configuration information is sent to described control module;
Storage array is the corresponding storage array of selecting according to described configuration information;
Described control module is used for: the interleaving data for the treatment of receiving is sent to described storage array, by described storage array, data are interweaved, the data after directly interweaving to described constellation mapping module parallel output; Then the data after interweaving are carried out to constellation mapping; When wherein, the bit wide of the data after the interweaving of parallel output is with constellation mapping, the bit number of each symbol is identical;
Described constellation mapping module for to receive interweave after data carry out constellation mapping;
Described configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping;
When interleave depth is the capable * n of m row, wherein, m represents the bit number information of each symbol when corresponding frame length information, the n of the modulating mode with selecting in described configuration information represents the constellation mapping in described configuration information; According to described configuration information, select corresponding storage array to be specially: determined storage array is comprised of n-1 memory module, the degree of depth of each memory module is m; Wherein, the numbering of a described n-1 memory module be respectively A1, A2 ... An-1;
Described control module also for:
(1) in memory module A1, memory module A2... memory module An-1, by row, write full Bit data successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, is m capable;
(2) the capable Bit data of m and outside directly 1 Bit data of input in while parallel read-out memory module A1, memory module A2... memory module An-1, form the parallel bit being comprised of n Bit data and flow;
(3) parallel bit stream is carried out to follow-up constellation mapping, simultaneously, continue to receive 1 new Bit data of outside input, then parallel read-out memory module A1, the capable data of m-1 in memory module A2... memory module An-1, repeat above-mentioned steps (1)-(3) m time, until parallel read-out memory module A1, in memory module A2... memory module An-1, the 1st line number is according to this and during the outside m sending 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, complete the cycle of a data interlacing and constellation mapping, repeat this cycle, constantly the Bit data receiving is carried out to data interlacing and constellation mapping.
5. the device of Bit Interleave according to claim 4 and constellation mapping, is characterized in that, selected modulating mode comprises: 8PSK, 16APSK or 32APSK.
6. the device of Bit Interleave according to claim 4 and constellation mapping, is characterized in that, described memory module is that bit wide is the asynchronous FIFO of 1.
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| CN201110354289.3A CN102437896B (en) | 2011-11-10 | 2011-11-10 | Bit interleaving and constellation mapping method and apparatus thereof |
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| CN111030780B (en) * | 2019-12-16 | 2022-07-12 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
| CN112737732B (en) * | 2020-12-25 | 2022-10-04 | 中国科学院国家空间科学中心 | In-channel interleaving system for DVB-T transmitter |
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| CN101188429A (en) * | 2007-12-24 | 2008-05-28 | 北京创毅视讯科技有限公司 | A bit interleaver and method for bit interleaving |
| CN101345738A (en) * | 2008-08-29 | 2009-01-14 | 成都德芯数字科技有限公司 | Mapping and interweaving method and system for digital television ground broadcast signal |
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| CN101345738A (en) * | 2008-08-29 | 2009-01-14 | 成都德芯数字科技有限公司 | Mapping and interweaving method and system for digital television ground broadcast signal |
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