CN102437896A - Bit interleaving and constellation mapping method and apparatus thereof - Google Patents
Bit interleaving and constellation mapping method and apparatus thereof Download PDFInfo
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Abstract
The invention provides a bit interleaving and constellation mapping method and an apparatus thereof. The method comprises the following steps: (1) storing configuration information corresponding to a selected modulation mode in bit interleaving and constellation mapping; (2) selecting a corresponding storage array according to the configuration information; (3) sending received data to be interleaved to the storage array, carrying out interleaving on data through the storage array, directly and parallelly outputting the interleaved data, and carrying out constellation mapping on the interleaved data, wherein, bit width of the interleaved data which is outputted directly and parallelly is same with a bit number of each symbol in the constellation mapping. Accordingly, in the invention, after carrying out bit interleaving, the interleaved data can be outputted directly and parallelly, the bit width of the interleaved data which is outputted directly and parallelly is same with the bit number of each symbol in the constellation mapping, thus subsequent constellation mapping can be carried out directly, and complexity of a device is substantially reduced.
Description
Technical field
The invention belongs to communication technical field, be specifically related to the method and the device of a kind of Bit Interleave and constellation mapping.
Background technology
Along with development of Communication Technique, the terminal use improves constantly for the requirement of system reliability, and especially at moving communicating field, the transmission course regular meeting of digital signal is attended by all kinds of interference sources, thereby makes signal produce distortion, influences communication quality.
Error correction coding can be corrected the random error of the digital information sequence of the random disturbances generation in the channel.But, only utilize error correction coding, for the bursty interference in the transmission course, need can increase the complexity of coder like this by means of very long code word, also can produce bigger time delay simultaneously.
The Bit Interleave technology is as a mode of improving communication system performance; Its groundwork principle is: Bit data is upset according to certain rule; Assemble error code dispersion in blocks original, thereby make unexpected error be converted into the randomness mistake, like this; Then in the error correction scope of error correcting code, receiving terminal just can carry out error correction with short code word to error code number after the error correction.
In the prior art, the structure of common bit interleaver comprises: control unit, RAM (RAM-Random Access Memory, random asccess memory).With satellite transmits standard DVB-S2 (ETSI En 302307) is example; The course of work of bit interleaver wherein is: RAM is that m*n (m is a line number, and n is a columns) storage matrix is that example describes with hocket write and read operation of ping-pong with RAM; Specifically may further comprise the steps: (1) when control unit receives first need carry out the bit data flow of Bit Interleave after; At first this bit data flow is write RAM with the row mode, that is: be listed as the 1st row to the 1st and write the 1st Bit data, be listed as the 2nd row to the 1st and write the 2nd Bit data; The rest may be inferred, and m is capable to write m Bit data up to being listed as to the 1st; Then, be listed as the 1st row to the 2nd and write m+1 bit, m is capable to write m*n Bit data up to being listed as to n.During this period, RAM is for writing state; (2) when RAM write full after, control module changes RAM into read states, with line mode from the RAM sense data; Promptly read the 1st Bit data from the 1st row the 1st row; The 1st row the 2nd row are read the 2nd Bit data, and the rest may be inferred, up to reading n Bit data from the 1st row n row; Then, read n+1 bit, up to reading m*n bit from the capable n row of m from the 2nd row the 1st row.Thereby realize the purpose that the bit data interweave.
In realizing process of the present invention, the inventor finds, has following problem in the prior art at least:
(1) since the RAM in the bit interleaver with hocket write and read operation of ping-pong; Promptly write after the completely whole memory capacity again sense data in another way in one way; The valid data throughput of whole module has only the half the of operating frequency, that is to say that operating frequency must be 2 times of data throughput.With the 8PSK modulation mode is example, 3 times of data throughput is-symbol rate, then 6 of operating frequency is-symbol rate times; Symbol rate for 45M; Requiring the operating frequency of module is 45*6=270MHz, and these all devices for this module have proposed very high requirement, thereby have increased device cost.
(2) owing to, must use line address counter and column address counter respectively the row and column address to be increased progressively computing, thereby increase the complex equipments degree in the stage of hocketing the write and read operation.
(3) because the data of bit interleaver output are that bit wide is 1 a serial bit stream, when carrying out the subsequent bits constellation mapping, must go here and there and change, thereby increased complex equipments degree and cost.
Summary of the invention
To the defective that prior art exists, the present invention provides the method and the device of a kind of Bit Interleave and constellation mapping, after carrying out Bit Interleave; Can be directly and the data of line output after interweaving; And, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping; And do not need extra use string and conversion operations, thereby significantly reduced the complexity of device.
The technical scheme that the present invention adopted is following:
The present invention provides the method for a kind of Bit Interleave and constellation mapping, may further comprise the steps:
(1) the stored bits configuration information corresponding when the constellation mapping that interweave with selected modulating mode;
(2) select corresponding storage array according to said configuration information;
The interleaving data of treating that (3) will receive sends to said storage array, through said storage array data is interweaved, and the data after directly also line output interweaves are carried out constellation mapping to the data after interweaving then; Wherein, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical.
Preferably, in the step (1), selected modulating mode comprises: 8PSK, 16APSK, 32APSK.
Preferably, said configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
Preferably, when interleave depth is the capable * n of m row, wherein, the bit number information of each symbol when on behalf of corresponding frame length information, the n of modulating mode with selecting in the said configuration information, m represent the constellation mapping in the said configuration information; In the step (2), select corresponding storage array to be specially according to said configuration information: determined storage array is made up of n-1 memory module, and the degree of depth of each memory module is m; Wherein, the numbering of a said n-1 memory module be respectively A1, A2 ... An-1.
Preferably, said memory module is that bit wide is 1 a asynchronous FIFO.
Preferably, in the step (3), the interleaving data of treating that receives is sent to said storage array, through said storage array data are interweaved, the data after directly also line output interweaves are carried out constellation mapping to the data after interweaving then, are specially:
(1) in memory module A1, memory module A2... memory module An-1, write full Bit data by row successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, and it is capable to be m;
(2) the capable Bit data of m and outside directly 1 Bit data of input among while parallel read-out memory module A1, the memory module A2... memory module An-1 form the parallel bit stream of being made up of n Bit data;
(3) the parallel bit stream that step (2) is obtained carries out follow-up constellation mapping; Simultaneously, continue to receive 1 new Bit data of outside input, then m-1 line data among parallel read-out memory module A1, the memory module A2... memory module An-1; Repeat above-mentioned steps m time; In parallel read-out memory module A1, memory module A2... memory module An-1 during the 1st line data and the outside m that sends 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, accomplishes that data interweave and the cycle of constellation mapping; Repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
The present invention also provides the device of a kind of Bit Interleave and constellation mapping, it is characterized in that, comprising: control module, dynamic-configuration module, storage array and constellation mapping module;
Wherein, said dynamic-configuration module is used for the stored bits configuration information corresponding with selected modulating mode when the constellation mapping that interweave, and this configuration information is sent to said control module;
Storage array is the storage array according to the correspondence of said configuration information selection;
Said control module is used for: the interleaving data of treating that will receive sends to said storage array, through said storage array data is interweaved, directly the data after said constellation mapping module and line output interweave; Wherein, then the data after interweaving are carried out constellation mapping; Wherein, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical.
Said constellation mapping module be used for to receive interweave after data carry out constellation mapping.
Preferably, selected modulating mode comprises: 8PSK, 16APSK, 32APSK.
Preferably, said configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
Preferably, when interleave depth is the capable * n of m row, wherein, the bit number information of each symbol when on behalf of corresponding frame length information, the n of modulating mode with selecting in the said configuration information, m represent the constellation mapping in the said configuration information; In the step (2), select corresponding storage array to be specially according to said configuration information: determined storage array is made up of n-1 memory module, and the degree of depth of each memory module is m; Wherein, the numbering of a said n-1 memory module be respectively A1, A2 ... An-1.
Preferably, said memory cell is that bit wide is 1 a asynchronous FIFO.
Preferably, said control module also is used for:
(1) in memory module A1, memory module A2... memory module An-1, write full Bit data by row successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, and it is capable to be m;
(2) the capable Bit data of m and outside directly 1 Bit data of input among while parallel read-out memory module A1, the memory module A2... memory module An-1 form the parallel bit stream of being made up of n Bit data;
(3) the parallel bit stream that step (2) is obtained carries out follow-up constellation mapping; Simultaneously, continue to receive 1 new Bit data of outside input, then m-1 line data among parallel read-out memory module A1, the memory module A2... memory module An-1; Repeat above-mentioned steps m time; In parallel read-out memory module A1, memory module A2... memory module An-1 during the 1st line data and the outside m that sends 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, accomplishes that data interweave and the cycle of constellation mapping; Repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
Beneficial effect of the present invention is following:
(1) method of Bit Interleave provided by the invention and constellation mapping and device; After carrying out Bit Interleave, can be directly and the data of line output after interweaving, and; And the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical; Thereby can directly carry out follow-up constellation mapping, and not need extra use string and conversion operations, thereby significantly reduce the complexity of device.
(2) since the present invention when carrying out Bit Interleave; The storage array that the storage array that adopts is made up of 1 asynchronous FIFO; And need not use line address counter and column address counter respectively the row and column address to be increased progressively computing, thereby further reduced the complex equipments degree.
(3) because in the interleaving mode provided by the invention; When interleave depth is the capable * n of m row; Only need to wait for the individual bit write operation completion of m* (n-1), just can carry out follow-up parallel work-flow, and need not wait for and just carry out output function after all m*n bits are all write full data; Thereby improved the operating efficiency of Bit Interleave and constellation mapping, reduced operating frequency.
(4) among the present invention; When needs interweave to m*n Bit data, only need to use the individual memory cell of m* (n-1), compare with m*n memory cell of satellite transmits standard DVB-S2 regulation; Reduce the number of m memory cell, thereby reduced device cost.
(5) among the present invention,, go for the different modulating pattern, thereby improved the versatility of equipment through changing the degree of depth and the quantity of each memory cell in configuration information and the storage array.
Description of drawings
The schematic flow sheet of a kind of Bit Interleave that Fig. 1 provides for the embodiment of the invention and the method for constellation mapping;
The structural representation of a kind of Bit Interleave that Fig. 2 provides for the embodiment of the invention and the device of constellation mapping.
Embodiment
Describe below in conjunction with the accompanying drawing specific embodiments of the invention.
Embodiment one
The embodiment of the invention provides the method for a kind of Bit Interleave and constellation mapping, and is as shown in Figure 1, may further comprise the steps:
Step 101, the stored bits configuration information corresponding when the constellation mapping that interweave with selected modulating mode.
Concrete, the configuration information corresponding with selected modulating mode comprises but is not limited to: the bit number information of each symbol during with the corresponding frame length information of the modulating mode of selection, constellation mapping.And; The method of Bit Interleave provided by the invention and constellation mapping can be applied in the different modulating modes; For example: 8PSK (8 Phase Shift Keying; 8 phase-shift keyings)), 16APSK (16 Amplitude Phase Shift Keying, 16 amplitude-phase shift keyings), 32APSK (32 Amplitude Phase Shift Keying, 32 amplitude-phase shift keyings) etc.As shown in table 1, in existing standard, the bit number information of each symbol when the frame length information that various modulating modes are corresponding, constellation mapping.
Table 1
Step 102 is selected corresponding storage array according to said configuration information.
For the regulation with existing standard is complementary, among the present invention, the various parameters of storage array are by the corresponding configuration information decision of selected modulating mode.Further, storage array is made up of a plurality of memory modules, and the frame length information in the configuration information has determined the degree of depth of memory module, and the bit number information of each symbol has determined the quantity of memory module in the storage array during constellation mapping in the configuration information.
Concrete, when interleave depth is the capable * n of m row, wherein, the bit number information of each symbol when on behalf of corresponding frame length information, the n of modulating mode with selecting in the said configuration information, m represent the constellation mapping in the said configuration information; In the step (2), select corresponding storage array to be specially according to said configuration information: determined storage array is made up of n-1 memory module, and the degree of depth of each memory module is m; Wherein, the numbering of a said n-1 memory module be respectively A1, A2 ... An-1.
For example: when the modulating mode of selecting is 16APSK; Because under the 16APSK modulating mode, the frame length of long frame is 16200, the bit number of each symbol is 4 during constellation mapping; Therefore; Selected storage array is made up of 3 memory modules, that is: memory module A1, memory module A2, memory module A3, and the degree of depth of each memory module A3 is 21600.
The complexity of device during for further reduction Bit Interleave and constellation mapping; It is 1 asynchronous FIFO (First Input First Output that the type of memory module can be selected bit wide; First Input First Output); Accomplish because the data address of asynchronous FIFO adds 1 automatically by the internal read write pointer, do not count and need not use external read to decide address wire as normal memory, thus the complexity of device can reduce Bit Interleave the time.
For example: when the modulating mode of selecting is 8PSK, because under the 8PSK modulating mode, the frame length of long frame is 21600; The bit number of each symbol is 3 during constellation mapping; Therefore, selected storage array is made up of 2 asynchronous FIFOs, that is: asynchronous FIFO 1, asynchronous FIFO 2; Wherein, the degree of depth of asynchronous FIFO 1 and asynchronous FIFO 2 is 21600.
In this step, compare, reduced the number of memory cell, thereby reduced device cost with standard code.With 8PSK is example, with respect to standard code, has reduced 21600 memory cell and standard and has compared, and has reduced by 1/3 device cost.As shown in table 2, under various modulating modes, the method and apparatus of Bit Interleave provided by the invention and constellation mapping is with respect to the improvement of standard code.
Table 2
And, through changing the degree of depth and the quantity of each memory cell in configuration information and the storage array, go for the different modulating pattern, thereby improved the versatility of equipment.
Step 103 sends to said storage array with the interleaving data of treating that receives, and through said storage array data is interweaved, and the data after directly also line output interweaves are carried out constellation mapping to the data after interweaving then; Wherein, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical.
Concrete interleaving mode may further comprise the steps:
(1) successively to memory module A1, memory module A2 ... write full Bit data by row among the memory module An-1, wherein, memory module A1, memory module A2 ... it is capable that the line number among the memory module An-1 is m;
(2) simultaneously parallel read-out memory module A1, memory module A2 ... m line data and outside directly 1 Bit data of input among the memory module An-1 form the parallel bit of being made up of n Bit data and flow;
(3) the parallel bit stream that step (2) is obtained carries out follow-up constellation mapping; Simultaneously; Continue to receive outside 1 the new Bit data that sends; Then parallel read-out memory module A1, memory module A2 ... m-1 line data among the memory module An-1, repeat above-mentioned steps m time, up to parallel read-out memory module A1, memory module A2 ... among the memory module An-1 during individual 1 Bit data of the 1st line data and the outside m that sends; That is: memory module A1, memory module A2 ... when memory module An-1 is sky; Accomplish data and interweave the cycle with constellation mapping, repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
For example: when the modulating mode of selecting was 8PSK, the storage array of selection was made up of 2 asynchronous FIFOs, that is: asynchronous FIFO 1, asynchronous FIFO 2, and wherein, the degree of depth of asynchronous FIFO 1 and asynchronous FIFO 2 is 21600.Then interleaving mode may further comprise the steps:
(1) write full Bit data to asynchronous FIFO 1, asynchronous FIFO 2 by row successively, wherein, the line number of asynchronous FIFO 1, asynchronous FIFO 2 is the degree of depth, is 21600 row.
Concrete, in asynchronous FIFO 1, write full 21600 Bit datas after, in asynchronous FIFO 2, write full 21600 Bit datas again.
(2) 1 Bit data of the 21600th line data and outside input in while parallel read-out asynchronous FIFO 1, the asynchronous FIFO 2 forms the parallel bit stream of being made up of 3 Bit datas;
(3) the 3 parallel-by-bit bit streams that step (2) obtained carry out follow-up constellation mapping; Simultaneously; Continuation writes 1 new Bit data from outside the 2nd time, then with parallel read-out asynchronous FIFO 1, asynchronous FIFO 2 in the 21599th line data, obtain 3 new parallel-by-bit bit streams and carry out follow-up constellation mapping; Repeat above-mentioned steps 21600 times; The 1st line data and during in parallel read-out asynchronous FIFO 1, asynchronous FIFO 2 from 1 Bit data writing for outside the 21600th time, that is: asynchronous FIFO 1, when asynchronous FIFO 2 is sky, accomplishes that data interweave and the cycle of constellation mapping; Repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
In sum, the method for Bit Interleave provided by the invention and constellation mapping has the following advantages:
(1) after carrying out Bit Interleave; Can be directly and the data of line output after interweaving; And, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping; And do not need extra use string and conversion operations, thereby significantly reduced the complexity of device.
(2) since the present invention when carrying out Bit Interleave; The storage array that the storage array that adopts is made up of 1 asynchronous FIFO; And need not use line address counter and column address counter respectively the row and column address to be increased progressively computing, thereby further reduced the complex equipments degree.
(3) because in the interleaving mode provided by the invention; When interleave depth is the capable * n of m row; Only need to wait for the individual bit write operation completion of m* (n-1), just can carry out follow-up parallel work-flow, and need not wait for and just carry out output function after all m*n bits are all write full data; Thereby improved the operating efficiency of Bit Interleave and constellation mapping, reduced operating frequency.
(4) among the present invention; When needs interweave to m*n Bit data, only need to use the individual memory cell of m* (n-1), compare with m*n memory cell of satellite transmits standard DVB-S2 regulation; Reduce the number of m memory cell, thereby reduced device cost.
(5) among the present invention,, go for the different modulating pattern, thereby improved the versatility of equipment through changing the degree of depth and the quantity of each memory cell in configuration information and the storage array.
Embodiment two
A kind of Bit Interleave that the embodiment of the invention provides and the device of constellation mapping comprise: control module, dynamic-configuration module, storage array and constellation mapping module; Introduce the operation principle and the course of work of each module below respectively.
(1) dynamic-configuration module
The dynamic-configuration module is used for the stored bits configuration information corresponding with selected modulating mode when the constellation mapping that interweave, and this configuration information is sent to said control module.Wherein, selected modulating mode comprises: 8PSK, 16APSK, 32APSK.Said configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
(2) storage array
Storage array is the storage array according to the correspondence of said configuration information selection.
Concrete, when interleave depth is the capable * n of m row, wherein, the bit number information of each symbol when on behalf of corresponding frame length information, the n of modulating mode with selecting in the said configuration information, m represent the constellation mapping in the said configuration information; In the step (2), select corresponding storage array to be specially according to said configuration information: determined storage array is made up of n-1 memory module, and the degree of depth of each memory module is m; Wherein, the numbering of a said n-1 memory module be respectively A1, A2 ... An-1.Wherein, memory cell can be 1 asynchronous FIFO for bit wide.
(3) control module
Control module is used for: the interleaving data of treating that will receive sends to said storage array, through said storage array data is interweaved, directly the data after said constellation mapping module and line output interweave; Wherein, then the data after interweaving are carried out constellation mapping; Wherein, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical.
The concrete workflow of said control module may further comprise the steps:
(1) successively to memory module A1, memory module A2 ... write full Bit data by row among the memory module An-1, wherein, memory module A1, memory module A2 ... it is capable that the line number among the memory module An-1 is m;
(2) simultaneously parallel read-out storage unit A 1, storage unit A 2 ... 1 Bit data of m line data and outside input among the storage unit A n-1 forms the parallel bit of being made up of n Bit data and flows;
(3) the parallel bit stream that step (2) is obtained sends to said constellation mapping module; Thereby carry out follow-up constellation mapping; Simultaneously, continue in storage unit A n the 2nd time and write 1 new Bit data, then parallel read-out storage unit A 1, storage unit A 2 ... 1 new Bit data among the storage unit A n-1 among m-1 line data and the storage unit A n; Repeat above-mentioned steps m time; Up to parallel read-out storage unit A 1, storage unit A 2 ... during the m time writes among the 1st line data and the storage unit A n among the storage unit A n-1 1 Bit data, that is: storage unit A 1, storage unit A 2 ... when storage unit A n-1 and storage unit A n are sky, accomplish data and interweave the cycle with constellation mapping; Repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
(4) constellation mapping module
The constellation mapping module be used for to receive interweave after data carry out constellation mapping.
As shown in Figure 2; A kind of Bit Interleave that provides for the embodiment of the invention and the device of constellation mapping, wherein, the modulating mode of selection is 8PSK; The storage array of selecting is made up of 2 asynchronous FIFOs; That is: asynchronous FIFO 1, asynchronous FIFO 2, wherein, the degree of depth of asynchronous FIFO 1 and asynchronous FIFO 2 is 21600.
In sum, the device of Bit Interleave provided by the invention and constellation mapping is after carrying out Bit Interleave; Can be directly and the data of line output after interweaving; And, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical, thereby can directly carry out follow-up constellation mapping; And do not need extra use string and conversion operations, thereby significantly reduced the complexity of device.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be looked protection scope of the present invention.
Claims (12)
1. the method for Bit Interleave and constellation mapping is characterized in that, may further comprise the steps:
(1) the stored bits configuration information corresponding when the constellation mapping that interweave with selected modulating mode;
(2) select corresponding storage array according to said configuration information;
The interleaving data of treating that (3) will receive sends to said storage array, through said storage array data is interweaved, and the data after directly also line output interweaves are carried out constellation mapping to the data after interweaving then; Wherein, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical.
2. the method for Bit Interleave according to claim 1 and constellation mapping is characterized in that, in the step (1), selected modulating mode comprises: 8PSK, 16APSK, 32APSK.
3. the method for Bit Interleave according to claim 1 and constellation mapping is characterized in that, said configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
4. the method for Bit Interleave according to claim 3 and constellation mapping; It is characterized in that; When interleave depth is the capable * n of m row; Wherein, m represents the bit number information of each symbol when representing the constellation mapping in the said configuration information with corresponding frame length information, the n of modulating mode that select in the said configuration information; In the step (2), select corresponding storage array to be specially according to said configuration information: determined storage array is made up of n-1 memory module, and the degree of depth of each memory module is m; Wherein, the numbering of a said n-1 memory module be respectively A1, A2 ... An-1.
5. the method for Bit Interleave according to claim 4 and constellation mapping is characterized in that, said memory module is that bit wide is 1 a asynchronous FIFO.
6. according to the method for claim 4 or 5 described Bit Interleaves and constellation mapping; It is characterized in that, in the step (3), the interleaving data of treating that receives is sent to said storage array; Through said storage array data are interweaved; Data after directly also line output interweaves are carried out constellation mapping to the data after interweaving then, are specially:
(1) in memory module A1, memory module A2... memory module An-1, write full Bit data by row successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, and it is capable to be m;
(2) the capable Bit data of m and outside directly 1 Bit data of input among while parallel read-out memory module A1, the memory module A2... memory module An-1 form the parallel bit stream of being made up of n Bit data;
(3) the parallel bit stream that step (2) is obtained carries out follow-up constellation mapping; Simultaneously, continue to receive 1 new Bit data of outside input, then m-1 line data among parallel read-out memory module A1, the memory module A2... memory module An-1; Repeat above-mentioned steps m time; In parallel read-out memory module A1, memory module A2... memory module An-1 during the 1st line data and the outside m that sends 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, accomplishes that data interweave and the cycle of constellation mapping; Repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
7. the device of Bit Interleave and constellation mapping is characterized in that, comprising: control module, dynamic-configuration module, storage array and constellation mapping module;
Wherein, said dynamic-configuration module is used for the stored bits configuration information corresponding with selected modulating mode when the constellation mapping that interweave, and this configuration information is sent to said control module;
Storage array is the storage array according to the correspondence of said configuration information selection;
Said control module is used for: the interleaving data of treating that will receive sends to said storage array, through said storage array data is interweaved, directly the data after said constellation mapping module and line output interweave; Wherein, then the data after interweaving are carried out constellation mapping; Wherein, and the bit wide of the data after the interweaving of line output during with constellation mapping the bit number of each symbol identical.
Said constellation mapping module be used for to receive interweave after data carry out constellation mapping.
8. the device of Bit Interleave according to claim 7 and constellation mapping is characterized in that, selected modulating mode comprises: 8PSK, 16APSK, 32APSK.
9. the device of Bit Interleave according to claim 7 and constellation mapping is characterized in that, said configuration information comprises: the bit number information of each symbol when the frame length information corresponding with the modulating mode of selecting, constellation mapping.
10. the device of Bit Interleave according to claim 9 and constellation mapping; It is characterized in that; When interleave depth is the capable * n of m row; Wherein, m represents the bit number information of each symbol when representing the constellation mapping in the said configuration information with corresponding frame length information, the n of modulating mode that select in the said configuration information; In the step (2), select corresponding storage array to be specially according to said configuration information: determined storage array is made up of n-1 memory module, and the degree of depth of each memory module is m; Wherein, the numbering of a said n-1 memory module be respectively A1, A2 ... An-1.
11. the device of Bit Interleave according to claim 10 and constellation mapping is characterized in that, said memory cell is that bit wide is 1 a asynchronous FIFO.
12. the device according to claim 10 or 11 described Bit Interleaves and constellation mapping is characterized in that said control module also is used for:
(1) in memory module A1, memory module A2... memory module An-1, write full Bit data by row successively, wherein, the line number of memory module A1, memory module A2... memory module An-1 is the degree of depth of memory module, and it is capable to be m;
(2) the capable Bit data of m and outside directly 1 Bit data of input among while parallel read-out memory module A1, the memory module A2... memory module An-1 form the parallel bit stream of being made up of n Bit data;
(3) the parallel bit stream that step (2) is obtained carries out follow-up constellation mapping; Simultaneously, continue to receive 1 new Bit data of outside input, then m-1 line data among parallel read-out memory module A1, the memory module A2... memory module An-1; Repeat above-mentioned steps m time; In parallel read-out memory module A1, memory module A2... memory module An-1 during the 1st line data and the outside m that sends 1 Bit data, that is: memory module A1, when memory module A2... memory module An-1 is sky, accomplishes that data interweave and the cycle of constellation mapping; Repeat this cycle, constantly the Bit data that receives is carried out data interlacing and constellation mapping.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106134086A (en) * | 2014-03-14 | 2016-11-16 | 三星电子株式会社 | For the method and apparatus controlling interleave depth |
| CN111030780A (en) * | 2019-12-16 | 2020-04-17 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
| US10693501B2 (en) | 2014-03-14 | 2020-06-23 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
| CN112737732A (en) * | 2020-12-25 | 2021-04-30 | 中国科学院国家空间科学中心 | In-channel interleaving system for DVB-T transmitter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188429A (en) * | 2007-12-24 | 2008-05-28 | 北京创毅视讯科技有限公司 | A bit interleaver and method for bit interleaving |
| CN101345738A (en) * | 2008-08-29 | 2009-01-14 | 成都德芯数字科技有限公司 | Mapping and interweaving method and system for digital television ground broadcast signal |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188429A (en) * | 2007-12-24 | 2008-05-28 | 北京创毅视讯科技有限公司 | A bit interleaver and method for bit interleaving |
| CN101345738A (en) * | 2008-08-29 | 2009-01-14 | 成都德芯数字科技有限公司 | Mapping and interweaving method and system for digital television ground broadcast signal |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106134086A (en) * | 2014-03-14 | 2016-11-16 | 三星电子株式会社 | For the method and apparatus controlling interleave depth |
| CN106134086B (en) * | 2014-03-14 | 2020-02-28 | 三星电子株式会社 | Method and apparatus for controlling interleaving depth |
| US10693501B2 (en) | 2014-03-14 | 2020-06-23 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
| US11018699B2 (en) | 2014-03-14 | 2021-05-25 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
| CN111030780A (en) * | 2019-12-16 | 2020-04-17 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
| CN111030780B (en) * | 2019-12-16 | 2022-07-12 | 中国科学院国家空间科学中心 | Configurable parallel bit grouping interleaver and interleaving method |
| CN112737732A (en) * | 2020-12-25 | 2021-04-30 | 中国科学院国家空间科学中心 | In-channel interleaving system for DVB-T transmitter |
| CN112737732B (en) * | 2020-12-25 | 2022-10-04 | 中国科学院国家空间科学中心 | In-channel interleaving system for DVB-T transmitter |
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