CN101667596A - 半导体元件及其制造方法 - Google Patents
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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Abstract
本发明提供一种半导体元件及其制造方法,该半导体元件包括一半导体基底与形成于半导体基底上的一晶体管。此晶体管具有一栅极结构,包括:一界面层,位于半导体基底上;一高介电常数介电层,位于界面层上;一盖层,位于高介电常数介电层上;以及一多晶硅层,位于盖层上。上述盖层包括氧化硅、氮氧化硅、氮化硅、或前述的组合。本发明可改善临界电压与载流子移动率,可形成高介电常数栅极介电层,使用的材料更适合整合在现有的CMOS工艺,并可以避免高介电常数金属栅极技术的各种问题。
Description
技术领域
本发明涉及半导体技术,尤其涉及一种具有高介电常数介电质与多晶硅栅极的半导体元件及其制造方法。
背景技术
半导体集成电路(IC)产业已历经快速的成长,每一新世代的IC均比前一世代更小且包含更复杂的电路。然而,这也代表IC制造工艺的复杂度越来越高,因此IC制造工艺也需要取得同样的进展才能实现新世代的集成电路。
集成电路不断朝着微缩化发展(在更小的几何尺寸上制作出更高密度的功能性电路)以增加生产效率并降低制作成本。此微缩化造成了相对高的功耗值(power dissipation value),为了解决此问题,可采用低功耗的元件例如互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor;CMOS)元件。
为了配合元件的微缩化趋势,许多材料已被应用作为CMOS元件的栅极与栅介电层,例如可使用金属材料作为栅极,并以高介电常数介电质(high-kdielectric)作为栅介电层。然而,NMOS与PMOS元件各自的栅极需要不同功函数。虽然目前已经有许多方法可同时形成金属栅极的N功函数与P功函数,例如双金属栅极结构及/或盖层,然而这些方法并非在所有方面均令人满意。例如,有效功函数不足与金属的热稳定性太差可能导致在制造工艺中临界电压上升与载流子移动率下降。
发明内容
本发明为了解决现有技术的问题而提供一种半导体元件,包括:一半导体基底;一晶体管,形成于半导体基底上,晶体管具有一栅极结构,包括:一界面层,位于半导体基底上;一高介电常数介电层,位于界面层上;一盖层,位于高介电常数介电层上,其中盖层包括氧化硅、氮氧化硅、氮化硅、或前述的组合;以及一多晶硅层,位于盖层上。
本发明还提供一种半导体元件的制造方法,包括:形成一界面层于一半导体基底上;形成一高介电常数介电层于界面层上;形成一盖层于高介电常数介电层上,其中盖层包括氧化硅、氮氧化硅、氮化硅、或前述的组合;形成一多晶硅层于盖层上;以及,图案化界面层、高介电常数介电层、盖层、及多晶硅层以形成一栅极结构。
本发明还提供一种半导体元件,包括:一半导体基底;一晶体管,形成于半导体基底上,晶体管具有一栅极结构,包括:一界面层,位于半导体基底上,界面层包括氧化硅、氮氧化硅、氮化硅、或前述的组合;一高介电常数介电层,位于界面层上;一盖层,位于高介电常数介电层上,其中盖层包括氧化硅、氮氧化硅、氮化硅、或前述的组合;以及一多晶硅层,位于盖层上。
本发明可改善临界电压与载流子移动率,可形成高介电常数栅极介电层,使用的材料更适合整合在现有的CMOS工艺,并可以避免高介电常数金属栅极技术的各种问题。
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出优选实施例,并配合所附附图,作详细说明如下:
附图说明
图1为一流程图,其显示本发明实施例中具有高介电常数介电质与多晶硅栅极的半导体元件的制作流程。
图2A~图2F为一系列剖面图,用以配合图1说明本发明实施例制作半导体元件的流程。
其中,附图标记说明如下:
110、120、130、140、150、160、170~流程步骤
200~半导体元件
202~半导体基底
203~隔离结构
204~PMOS元件
206~NMOS元件
210~界面层
212~高介电常数介电层
214~盖层
220~多晶硅层
231、232~光致抗蚀剂图案
241、242~栅极堆叠
具体实施方式
以下将说明本发明的各种实施例,在本说明书的各种例子中可能会出现重复的元件符号以便简化描述,但这不代表在各个实施例及/或图示之间有何特定的关联。另外,当提到某一元件位于另一元件“之上”或“上方”,可代表两元件之间直接接触或中间还插有其他元件或膜层。为了简化图示与突显本发明的特征,各元件之间可能未照实际比例描绘。
请参见图1,其显示本发明实施例中具有高介电常数介电质与多晶硅栅极的半导体元件的制作流程100。图2A~图2F为一系列剖面图,用以配合图1说明本发明实施例制作半导体元件200的流程。应注意的是,图2A~图2F的半导体元件200可还包含其他元件,但为了突显本发明的特征,仅示出PMOS元件与NMOS元件的栅极结构。另外,图1的方法100可以实施于CMOS制造工艺中,因此在方法100之前,之中,或之后均可以加入额外的制造工艺。
请参见图2A,首先提供一半导体基底,如步骤110。半导体元件200包含一半导体基底202,例如硅基底。基底202也可以是碳化硅(SiC)、砷化镓(GaAs)、或其他适合的半导体基底。基底202可还包含其他元件例如掺杂区(p-阱或n-阱)、埋藏层(buried layer)、及/或外延层。基底202也可以是绝缘层上覆硅(Silicon on Insulator;SOI)基底。在其他实施例中,基底202可包含掺杂外延层、梯度(gradient)半导体层、及/或还包括位于另一不同的半导体层之上的一半导体层,例如位于一硅锗层上的一硅层。在其他例子中,化合物半导体基底可包含多层硅结构或硅基底可包含多层化合物半导体结构。
半导体元件200可还包含一隔离结构203例如浅沟槽隔离(STI)或局部硅氧化(LOCOS)结构,以电性隔离基底上的有源区204、206。举例而言,浅沟槽隔离的形成可包含干蚀刻基底以形成一沟槽,然后以氧化硅、氮化硅、或氮氧化硅等绝缘材料填入上述沟槽。浅沟槽隔离可包含多层结构,例如一热氧化物衬层加上氧化硅或氮化硅的填充材料。在一实施例中,浅沟槽隔离的形成的工艺可包含:成长一垫氧化层、以低压化学气相沉积法(Low-pressurechemical vapor deposition;LPCVD)形成一氮化层、以光刻与蚀刻技术形成STI开口、蚀刻基底形成沟槽、视需要(optionally)成长一热氧化衬层以改善沟槽界面、以CVD氧化物填入沟槽、以化学机械研磨(Chemical MechanicalPolishing;CMP)进行平坦化、去除氮化层。有源区204可用来形成PMOS元件,有源区206可用来形成NMOS元件。
接着,形成一界面层210于半导体基底202上,如步骤120。此界面层210可包含厚度约2-的二氧化硅。界面层210可采用热氧化工艺形成,或者使用原子层沉积(ALD)、化学气相沉积(CVD)、化学处理(例如化学氧化)、前述的组合、或其他适合的热工艺形成。在其他实施例中,界面层210可包含氮氧化硅或氮化硅。
请参见图2B,形成一高介电常数介电层212于界面层210上,如步骤130。高介电常数介电层212可使用ALD、CVD、有机金属化学气相沉积法(Metal Organic Chemical Vapor Deposition,MOCVD)、物理气相沉积法(PVD)、前述的组合、或其他适合的沉积工艺形成。高介电常数介电层212的厚度约5-高介电常数介电层212可包含二元或三元高介电常数材料,例如HfO,LaO,AlO,ZrO,TiO,Ta2O5,Y2O3,STO,BTO,BaZrO,HfZrO,HfLaO,HfSiO,LaSiO,AlSiO,HfTaO,HfTiO,BST,Al2O3,Si3N4、前述的组合、或其他适合的材料。此外,高介电常数介电层212可包含硅化物(silicate)例如HfSiO、LaSiO、AlSiO、前述的组合、或其他适合的材料。
请参见图2C,形成一盖层214于高介电常数介电层212上,如步骤140。盖层214可用来降低及/或避免高介电常数介电层212与其上方多晶硅层220之间的费米能阶钉扎效应(Femi level pinning)。盖层214例如可包含氧化硅、氮氧化硅、或氮化硅。盖层214可使用ALD、CVD、PVD、或其他适合的沉积工艺形成在高介电常数介电层212上。另外,可在高介电常数介电层212上先形成氧化层,然后对此氧化层进行氮化工艺以形成盖层214。例如,先以CVD、ALD、及/或PVD沉积氧化层,再对氧化层进行热氮化工艺。上述热氮化工艺可包括在含氮气体下进行约500-1200℃的热回火,其中含氮气体例如NH3、N2O、NO、或N2。在其他实施例中,可先以CVD、ALD、及/或PVD沉积氧化层,再对氧化层进行自由基氮化(radical nitridation)工艺。自由基氮化工艺使用氮自由基作为氮的来源。盖层214的厚度例如约2-应注意的是,高介电常数介电层212与盖层214的形成可以在原位(in-situ)进行。
请参见图2E,将上述各层图案化以形成一栅极结构,如步骤160。在一实施例中,可先以适当沉积方式(如旋转涂布法)形成一光致抗蚀剂层,然后进行光刻工艺以形成光致抗蚀剂图案231、232。然后借由数个适当的工艺步骤将光致抗蚀剂图案231、232转移至底下的多晶硅层220、盖层214、高介电常数介电层212、以及界面层210。光致抗蚀剂图案231、232可以公知的适当工艺剥除。在另一实施例中,可将一硬掩模层形成于多晶硅层220上,并将上述光致抗蚀剂层形成于硬掩模层上。之后,光致抗蚀剂图案先转移到硬掩模层上,再转移至底下的材料层以形成栅极结构。上述硬掩模层可包含氮化硅、氮氧化硅、碳化硅、氧化硅、及/或其他适合的介电材料,且可以CVD或PVD形成。
请参见图2F,借由干蚀刻、湿蚀刻、或干蚀刻与湿蚀刻的组合形成PMOS元件204的栅极堆叠241与NMOS元件206的栅极堆叠242。栅极堆叠241可包含:界面层210p、高介电常数介电层212p、盖层214p、多晶硅层220p。栅极堆叠242可包含:界面层210n、高介电常数介电层212n、盖层214n、多晶硅层220n。栅极堆叠241与栅极堆叠242分别作为PMOS元件204与NMOS元件206的栅极。多晶硅层220p与多晶硅层220n可分别掺杂p型与n型掺质。多晶硅层的掺杂可与后续形成源极/漏极区的离子注入一并进行,或在沉积多晶硅层的同时进行掺杂。或者,利用其他公知的工艺进行掺杂。
接着,进行CMOS制造工艺步骤以完成半导体元件的制作,如步骤170。其余的CMOS制造工艺步骤例如包括:形成轻掺杂源极/漏极区(LDD)、栅极间隔物、源极/漏极区、金属硅化物、接触插塞、内连线层、金属层、内层介电层、保护层等。
例如,可借由离子注入在基底202中形成与栅极堆叠241、242对齐的轻掺杂源极/漏极区(LDD)。在PMOS元件204中,栅极堆叠241两侧的LDD可包含P型掺质例如硼。在NMOS元件206中,栅极堆叠242两侧的LDD可包含N型掺质例如磷或砷。在栅极堆叠241、242两侧的侧壁上可形成栅极间隔物,其可包含介电材质例如氧化硅、氮化硅、碳化硅、氮氧化硅、或前述的组合。此外,栅极间隔物可包含多层结构。栅极间隔物可用公知的沉积与回蚀刻(各向异性蚀刻)技术形成。
本发明的实施例具有许多优点,例如本发明提供一种简单且低成本的方法以降低或避免高介电常数介电层与多晶栅极之间的费米能阶钉扎效应(Femi level pinning),因此可改善临界电压与载流子移动率。此外,本发明的方法与结构可以轻易整合在现有的CMOS制造工艺与半导体设备,因此可形成高介电常数栅极介电层。另外,此处所使用的材料例如氧化硅、氮氧化硅、氮化硅、多晶硅等都比金属栅极更适合整合在现有的CMOS制造工艺。因此本发明的方法与结构可以避免高介电常数金属栅极技术的各种问题,例如N/P金属图案化(如光致抗蚀剂剥落)、金属栅极复杂的功函数最佳化工艺、载流子移动率下降、可靠性度与电容-电压阻滞(C-V hysteresis)等问题。
虽然本发明已以数个优选实施例揭示如上,然其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,例如本发明的半导体装置不限于特定的晶体管,而可包括其他装置例如鳍式场效应晶体管、高压晶体管、双极性结晶体管(BJT)、电阻、二极管、电容、及电熔丝(eFuse)等,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (14)
1.一种半导体元件,包括:
一半导体基底;
一晶体管,形成于该半导体基底上,该晶体管具有一栅极结构,包括:
一界面层,位于该半导体基底上;
一高介电常数介电层,位于该界面层上;
一盖层,位于该高介电常数介电层上,其中该盖层包括氧化硅、氮氧化硅、氮化硅、或前述的组合;以及
一多晶硅层,位于该盖层上。
2.如权利要求1所述的半导体元件,其中该晶体管包括一PMOS晶体管或一NMOS晶体管。
3.如权利要求1所述的半导体元件,其中该多晶硅层的厚度约200-2000
5.如权利要求1所述的半导体元件,其中该高介电常数介电层包括:HfO,LaO,AlO,ZrO,TiO,Ta2O5,Y2O3,STO,BTO,BaZrO,HfZrO,HfLaO,HfSiO,LaSiO,AlSiO,HfTaO,HfTiO,BST,Al2O3,Si3N4、或前述的组合。
6.如权利要求5所述的半导体元件,其中该高介电常数介电层的厚度约5-50
7.如权利要求1所述的半导体元件,其中该界面层包括氧化硅、氮氧化硅、氮化硅、或前述的组合。
8.如权利要求7所述的半导体元件,其中该界面层的厚度约2-20
9.一种半导体元件的制造方法,包括如下步骤:
形成一界面层于一半导体基底上;
形成一高介电常数介电层于该界面层上;
形成一盖层于该高介电常数介电层上,其中该盖层包括氧化硅、氮氧化硅、氮化硅、或前述的组合;
形成一多晶硅层于该盖层上;以及
图案化该界面层、该高介电常数介电层、该盖层、及该多晶硅层以形成一栅极结构。
10.如权利要求9所述的半导体元件的制造方法,其中该盖层的形成方法包括化学气相沉积法、原子层沉积法、物理气相沉积法、在含氮气体下回火进行氮化、氮自由基氮化、或前述的组合。
11.如权利要求10所述的半导体元件的制造方法,其中该盖层的形成包括如下步骤:
以化学气相沉积法、原子层沉积法、或物理气相沉积法形成一氧化层;及
对该氧化层进行一热氮化处理,该热氮化处理的温度约500-1200℃。
12.如权利要求10所述的半导体元件的制造方法,其中该盖层的形成包括如下步骤:
以化学气相沉积法、原子层沉积法、或物理气相沉积法形成一氧化层;及
对该氧化层进行一自由基氮化处理。
13.如权利要求9所述的半导体元件的制造方法,其中该界面层的形成方法包括:热成长工艺、原子层沉积法、化学气相沉积法、或前述的组合。
14.如权利要求9所述的半导体元件的制造方法,其中该高介电常数介电层与该盖层的形成是在原位进行。
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CN102760656A (zh) * | 2011-04-27 | 2012-10-31 | 南亚科技股份有限公司 | 栅极介电层制备方法及栅极结构制备方法 |
CN103299430A (zh) * | 2010-12-30 | 2013-09-11 | 周星工程股份有限公司 | 薄膜晶体管及其制造方法 |
CN109037332A (zh) * | 2017-06-12 | 2018-12-18 | 中兴通讯股份有限公司 | 碳化硅金属氧化物半导体场效应晶体管及其制造方法 |
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US20100052076A1 (en) * | 2008-09-04 | 2010-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating high-k poly gate device |
US20120299157A1 (en) * | 2011-05-25 | 2012-11-29 | Teng-Chun Hsuan | Semiconductor process and fabricated structure thereof |
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US6803611B2 (en) * | 2003-01-03 | 2004-10-12 | Texas Instruments Incorporated | Use of indium to define work function of p-type doped polysilicon |
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JP4919586B2 (ja) * | 2004-06-14 | 2012-04-18 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
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EP1880409B1 (en) * | 2005-04-21 | 2014-03-26 | Freescale Semiconductor, Inc. | Method of fabricating a mos device with a high-k or sion gate dielectric |
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US20100052076A1 (en) * | 2008-09-04 | 2010-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating high-k poly gate device |
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CN103299430A (zh) * | 2010-12-30 | 2013-09-11 | 周星工程股份有限公司 | 薄膜晶体管及其制造方法 |
CN102760656A (zh) * | 2011-04-27 | 2012-10-31 | 南亚科技股份有限公司 | 栅极介电层制备方法及栅极结构制备方法 |
CN109037332A (zh) * | 2017-06-12 | 2018-12-18 | 中兴通讯股份有限公司 | 碳化硅金属氧化物半导体场效应晶体管及其制造方法 |
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