CN101661887A - Method for preparing source-drain injection structures - Google Patents
Method for preparing source-drain injection structures Download PDFInfo
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- CN101661887A CN101661887A CN200810043731A CN200810043731A CN101661887A CN 101661887 A CN101661887 A CN 101661887A CN 200810043731 A CN200810043731 A CN 200810043731A CN 200810043731 A CN200810043731 A CN 200810043731A CN 101661887 A CN101661887 A CN 101661887A
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Abstract
The invention discloses a method for preparing source-drain injection structures in semiconductor devices. The method comprises: performing lightly doped drain injection for masks through photoresistgraphs after previous lithography development; narrowing openings of mask graphs; and performing source-drain injection through the narrowed mask graphs to form source-drain injection regions. The preparation method, having the advantages of needing lithography development only once and omitting a sidewall process, can be widely used in the preparation of semiconductor devices.
Description
Technical field
The present invention relates to a kind of preparation method of semiconductor device source-drain injection structures, comprise the formation of source-drain area and lightly doped drain.
Background technology
In semiconductor chip was made, the number of times of general photoetching had determined the cost of product.In traditional chip preparing process flow process, injection region (SD Implanting) is leaked in the source and lightly doped drain (LDDLight Dose Doping) injection is used as injecting the barrier layer by Twi-lithography respectively.The method flow that common semiconductor device injecting structure forms after polysilicon gate forms, comprises the steps:
1, deposit one deck silicon oxide liner bed course on silicon chip is used for the structure that has formed on ion implantation process protection silicon substrate;
2, low dosage doping injection region photoetching, after carry out low dose ion and inject;
3, form the polysilicon gate side wall;
4, photoetching leak is injected in the source, after carry out the source-drain area ion and inject.
The follow-up conventional steps such as photoresist and cleaning that for example go in addition.In above-mentioned flow process, as can be seen, need, carry out Twi-lithography technology as injecting the barrier layer with two lithography mask versions.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of preparation method of source-drain injection structures, and it can reduce the chip production cost by reducing lithography mask version and photoetching number of times.
For solving the problems of the technologies described above, the preparation method of source-drain injection structures of the present invention, described source-drain injection structures comprises that the source leaks injection region and lightly doped drain, it is characterized in that, forms after the grid of described semiconductor device on silicon substrate, comprises the steps:
1) deposit one deck silica on described surface of silicon, the protective layer when injecting as ion;
2) resist coating on described silica with the lithography mask version exposure imaging of low dose ion injection region, exposes and need carry out the zone that low dose ion injects, and is mask with the photoresist figure after developing, and carries out ion and injects the formation lightly doped drain;
3) silicon chip is toasted, make photoresist figure opening be contracted to predetermined number range;
4) the photoresist figure after utilizing opening size to dwindle is mask, carries out the source and leaks ion and inject, and the injection region is leaked in the formation source;
5) remove photoresist and cleaning.
The preparation method of source-drain injection structures of the present invention, only need a lithography mask version to carry out a photoetching, and between twice injection by dwindling the opening size of mask pattern, omit the flow process (deposit and the etching that comprise silica) of side wall preparation in the common process, significantly reduced the cost of preparation.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the structural representation behind the polysilicon gate photoetching development among the preparation method of the present invention;
Fig. 2 is the structural representation behind the polysilicon gate etching among the preparation method of the present invention;
Fig. 3 is the structural representation after the preparation of silicon oxide liner bed course among the preparation method of the present invention;
Fig. 4 is the structural representation after LDD forms among the preparation method of the present invention;
Fig. 5 is the structural representation after the baking among the preparation method of the present invention;
Fig. 6 is the structural representation after the source leakage is injected among the preparation method of the present invention;
Fig. 7 is a preparation flow schematic diagram of the present invention.
Embodiment
The preparation method who injects is leaked in semiconductor device of the present invention source, and wherein the source is leaked to inject and comprised that conventional source-drain area injects (heavy doping) and lightly doped drain injects (being that LDD injects).Preparation method of the present invention mainly based on after the photoetching, carries out the injection of low dosage doped region earlier, forms the LDD district; Then dwindle the photoresist opening, make the photoresist opening be reduced into the size that the doped region figure is leaked in predefined source; Carry out the injection of source-drain area again, form source-drain area; Remove photoresist at last to clean and get final product.
Specifically describe the flow process of enforcement below in conjunction with Fig. 7:
1, after the polysilicon gate deposit, carries out the photoetching (see figure 1) of polysilicon gate;
2, etching is removed the polysilicon that exposes, and forms the grid (see figure 2) of semiconductor device;
3, follow deposit one deck silicon oxide liner bed course (liner oxide), the protective layer (see figure 3) when injecting as ion;
4, resist coating, lithography mask version exposure imaging with low dosage doping injection region, expose and need carry out the zone that low dosage mixes and injects, low energy ion injects and forms the lightly doped drain (see figure 4), and the injection ion energy in this step is identical with conventional technology with dosage;
5, dwindle the opening of photoresist, make the photoresist opening be reduced into the size that the doped region figure is leaked in predefined source.Concrete implementation method is: will form the silicon chip baking behind the photoresist figure, and utilize photoresist to be subjected to thermal softening, the hot reflux effect makes the openings get smaller of photoresist figure to predetermined numerical value (see figure 5).In this process, the kind and the thickness of the variation of photoresist opening and the photoresist that is coated with, technological parameters such as the temperature that baking sets and stoving time are relevant, and the temperature and the stoving time that toast in concrete the use can obtain by test.Used photoresist can be that I-Line (I line photoresist) also can be the KrF photoresist, and it is by ketone, ethers, alkanes organic solvent and photosensitive cross-linking resin constitute, and molecular weight is between 85000～150000, and each full-filling dosage is 1.5ml～5ml, can be coated with 1～3 time, the photoresist bed thickness is
Baking temperature is 60 ℃～250 ℃, and stoving time is 10s～120s.Live width (being the photoresist opening) is 0.2～1.0um before the baking, and baking back live width is 0.1～0.8um.
6, the figure that dwindles with the step 5 split shed is a mask, carries out the source and leaks the ion injection, and the injection region (see figure 6) is leaked in the formation source.The type of the injection ion in the injection technology, dosage, injection energy etc. are identical with common process.
7, last, remove photoresist and cleaning.
Claims (2)
1, a kind of preparation method of source-drain injection structures, described source-drain injection structures comprises leakage injection region, source and lightly doped drain, it is characterized in that, forms after the grid of described semiconductor device on silicon substrate, comprises the steps:
1) deposit one deck silica on described surface of silicon, the protective layer when injecting as ion;
2) resist coating on described silica with the lithography mask version exposure imaging of low dose ion injection region, exposes and need carry out the zone that low dose ion injects, and is mask with the photoresist figure after developing, and carries out ion and injects the formation lightly doped drain;
3) silicon chip is toasted, make photoresist figure opening be contracted to predetermined number range;
4) the photoresist figure after utilizing opening size to dwindle is mask, carries out the source and leaks ion and inject, and the injection region is leaked in the formation source;
5) remove photoresist and cleaning.
According to the described preparation method of claim 1, it is characterized in that 2, the temperature range of toasting in the described step 3 is 60 ℃～250 ℃, stoving time is 10s～120s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100437319A CN101661887B (en) | 2008-08-25 | 2008-08-25 | Method for preparing source-drain injection structures |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100437319A CN101661887B (en) | 2008-08-25 | 2008-08-25 | Method for preparing source-drain injection structures |
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| CN101661887A true CN101661887A (en) | 2010-03-03 |
| CN101661887B CN101661887B (en) | 2012-04-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386096A (en) * | 2010-08-31 | 2012-03-21 | 上海华虹Nec电子有限公司 | Method of improving consistence and stability of LDMOS (Laterally Diffused Metal Oxide Semiconductor) performance |
| CN109698262A (en) * | 2017-10-24 | 2019-04-30 | 山东浪潮华光光电子股份有限公司 | A kind of electrode preparation method of LED chip |
| WO2024146133A1 (en) * | 2023-01-04 | 2024-07-11 | 长鑫存储技术有限公司 | Preparation method for semiconductor structure, and semiconductor structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003124309A (en) * | 2001-10-09 | 2003-04-25 | Macronix Internatl Co Ltd | Method of forming via and trench in copper dual damascene process |
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2008
- 2008-08-25 CN CN2008100437319A patent/CN101661887B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386096A (en) * | 2010-08-31 | 2012-03-21 | 上海华虹Nec电子有限公司 | Method of improving consistence and stability of LDMOS (Laterally Diffused Metal Oxide Semiconductor) performance |
| CN109698262A (en) * | 2017-10-24 | 2019-04-30 | 山东浪潮华光光电子股份有限公司 | A kind of electrode preparation method of LED chip |
| WO2024146133A1 (en) * | 2023-01-04 | 2024-07-11 | 长鑫存储技术有限公司 | Preparation method for semiconductor structure, and semiconductor structure |
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| CN101661887B (en) | 2012-04-18 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |