CN102445839B - Method for self-aligned photo-etching - Google Patents
Method for self-aligned photo-etching Download PDFInfo
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- CN102445839B CN102445839B CN 201010509857 CN201010509857A CN102445839B CN 102445839 B CN102445839 B CN 102445839B CN 201010509857 CN201010509857 CN 201010509857 CN 201010509857 A CN201010509857 A CN 201010509857A CN 102445839 B CN102445839 B CN 102445839B
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Abstract
The invention discloses a method for self-aligned photo-etching, comprising the following steps of: 1) depositing an anti-reflecting material on a self-aligned graph layer; and then utilizing photo-etching and etching processes to form a self-aligned graph in the anti-reflecting material; 2) then coating negative photo-resist; and 3), finally, exposing and developing to remove the negative photo-resist on the anti-reflecting material. With the adoption of the method provided by the invention, the self-aligned photo-etching without a photo-etching mask is realized.
Description
Technical field
The present invention relates to a kind of photoetching process, particularly a kind of self aligned photoresist process.
Background technology
Photoetching process is a kind of manufacturing process of in semiconductor devices production, design configuration being transferred on silicon chip.It decomposes by the device that will design, and repeatedly photoetching forms respectively the different piece of different components.Repeatedly photoetching just runs into the problem of a mutual overlay alignment between different lithography layers.Usually due to the restriction of equipment and process, will inevitably there be a departure in this alignment deviation, has restricted the characteristic of device.Therefore must consider when designing this deviate to a certain amount of Redundancy Design space, but device area is increased.Therefore photoetching alignment precision becomes the index of a critical restriction technological ability.In order to overcome device property that the photoetching alignment brings or the loss of area, self aligned method has been subject to device designer and technique fabricator's very big welcome, and it can realize the alignment between perfectly two-layer.
Self-registered technology method commonly used has two kinds: a kind of is in injection technology, utilize the level that has formed as the restraining barrier, the zone that does not need to inject is stopped by other materials, the source-drain area later such as grid injects (seeing Fig. 1), utilizes the grid that has formed that channel region is stopped.The shortcoming of this method is to need the autoregistration layer thickness very thick; can exist as the restraining barrier in subsequent technique; and this layer material can after need directly to be injected into or etching in technique, therefore can not have the situation of damage inapplicable for the autoregistration layer that needs protection.It can only operate in lower not protected zone simultaneously, can not operate the autoregistration layer conversely.Therefore this method relatively is fit to substrate is injected or wet etching usually.
Another kind is to be used in etching technics, if when materials at two layers needs autoregistration to form, just do not adopt respectively monolayer deposition, and the method for individual layer etching, but adopt deposition together, the method for etching forms (seeing Fig. 2) together.Formation such as double-deck autoregistration stacking gate.But the shortcoming of this method also clearly, can't form separately the figure of each layer, needs extra light shield to carry out the generation of autoregistration layer, and process complexity and cost are higher.Materials at two layers or remove together simultaneously, or produce together, and this materials at two layers is all often the parts that form device, therefore be difficult to produce simultaneously the autoregistration structure adjacent with monolayer material, if produce, not just autoregistration, change back to again and will consider alignment precision.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method of self-aligned photo-etching, and it can form the autoregistration figure at arbitrary region.
For solving the problems of the technologies described above, the method for self-aligned photo-etching of the present invention comprises the steps:
1) deposit antireflection material on self aligned graph layer adopts photoetching and etching technics to form the autoregistration figure in described antireflection material;
2) then be coated with negative photoresist;
3) directly expose at last and develop, removing the negative photoresist on described antireflection material layer.
The method of self-aligned photo-etching of the present invention, having used negative photoresist has lower than threshold value E0 exposure and can be developed, can not be developed this characteristic higher than E0, utilize antireflection material to disappear substrate reflectivity to very low, even exposure energy is higher than E0, but therefore the actual effectively exposure energy of the part on antireflection material still can be developed far below E0.And in the zone that there is no anti-reflecting layer, exposure energy is still higher than E0, and photoresist can be retained, and does not use up mask plate but therefore do not need to make, as long as carry out blanket exposure, just can form figure according to the figure autoregistration of anterior layer anti-reflecting layer.Adopt the method for self-aligned photo-etching of the present invention, have a cost low, the simple advantage of technique, illumination even can not adopted litho machine comprehensively, and can adopt the direct irradiation of ultraviolet light.Simultaneously, use therein anti-reflecting layer is not the material that forms device, and the intermediate materials in just making, therefore can carry out arbitrarily subsequent technique and do not worry its be injected into or etching after device property is impacted.When anti-reflecting layer is selected SiON, during the covering layer material commonly used such as TiN, can deposit together formation with other retes, its figure also can produce when other retes of etching together, does not therefore need extra photolithography plate and lithography step.Adopt simultaneously the anti-reflecting layers such as SiON or TiN, it is membranous has retinue, can ignore the step difference of height, produces in high or low zone arbitrarily according to the selection of integrated technique, therefore self-registered technology is not subjected to the restriction of step difference, can form the autoregistration figure at arbitrary region.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the exemplary construction schematic diagram of autoregistration Implantation;
Fig. 2 is the structural representation of Self-aligned etching;
Fig. 3 is the schematic flow sheet of self-aligned photo-etching of the present invention;
Fig. 4 is the structural representation after the coating negative photoresist in the present invention;
Fig. 5 is the structural representation after exposure imaging in the present invention;
Fig. 6 is the developing rate schematic diagram of negative photoresist.
Embodiment
Self-aligned photo-etching method of the present invention comprises the steps:
1) deposit antireflection material on self aligned graph layer then adopts photoetching and etching technics to form the autoregistration figure on the antireflection material layer;
2) then be coated with negative photoresist;
3) directly expose at last and develop, removing the negative photoresist on the antireflection material layer.Exposure energy E can be: E0<E<E0*A, wherein E0 is the threshold energy that is not dissolved in developer solution after the negative photoresist exposure, A=r/R, R is that antireflection material is under exposure wavelength, the substrate reflectivity of the multilayer film that forms with substrate, r is the substrate reflectivity under exposure wavelength when there is no antireflection material.Do not need to use lithography mask version in exposure process.Antireflection material preferentially adopts the inorganic anti-reflective material, SiON or TiN.Also can use organic antireflection material, as BARC.
In concrete enforcement, the E0 value of first demarcating the negative photoresist that uses by light exposure test.With the photoresist that contains dyestuff of a kind of KrF wave band of using in 0.13 μ m technique, its typical E0 value is 4mj/cm2 on the Si substrate.Antireflection material take SiON as example, forms the autoregistration layer on Si, its typical reflectivity is between 0.1%~20%, with the different and to some extent changes different with thickness of SiON technique.
The deposition of SiON can adopt chemical vapor deposition (CVD) method, and its typical one-tenth-value thickness 1/10 is 300~600 dusts, and this moment, reflectivity was 2% left and right.And the typical reflectivity of Si is 40% left and right, and therefore obtaining the difference ratio A is A=40%/2%=20.In order to increase process window, can reduce as far as possible its reflectivity.
The spin coating negative photoresist carries out blanket exposure, and its exposure energy E can be set to greater than 4mj/cm2 then to develop less than 4*A=80mj/cm2.Referring to the negative photoresist developing rate schematic diagram of Fig. 6, wherein do not have the photoresist exposure energy in anti-reflecting layer district to be retained greater than E0, and be developed less than E0 at the actual effectively exposure energy in anti-reflecting layer district, final autoregistration forms figure.
Claims (3)
1. the method for a self-aligned photo-etching, is characterized in that, comprises the steps:
1) deposit antireflection material on self aligned graph layer then adopts photoetching and etching technics to form the autoregistration figure in described antireflection material;
2) then be coated with negative photoresist;
3) directly expose at last and develop, removing the negative photoresist on described antireflection material; In described step 3) exposure, the exposure energy E that adopts is: E0<E<E0*A, wherein E0 is the threshold energy that is not dissolved in developer solution after described negative photoresist exposure, A=r/R, R is that described antireflection material is under exposure wavelength, the substrate reflectivity of the multilayer film that forms with substrate, r is the substrate reflectivity under exposure wavelength when there is no antireflection material.
2. it is characterized in that in accordance with the method for claim 1: the R in described step 3) is less than 20%.
3. according to the described method of any one in claim 1 to 2, it is characterized in that: described antireflection material is SiON or TiN.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080203490A1 (en) * | 2007-02-28 | 2008-08-28 | Feilchenfeld Natalie B | Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for bicmos integration |
CN101447456A (en) * | 2007-11-30 | 2009-06-03 | 东部高科股份有限公司 | Method for fabricating semiconductor device |
JP2009532883A (en) * | 2006-03-31 | 2009-09-10 | アプライド マテリアルズ インコーポレイテッド | Method for forming thin film photovoltaic interconnects using a self-aligned process |
CN101752247A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method for automatically collimating and forming Zener diode |
CN101847596A (en) * | 2009-03-25 | 2010-09-29 | 旺宏电子股份有限公司 | Patterning method |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009532883A (en) * | 2006-03-31 | 2009-09-10 | アプライド マテリアルズ インコーポレイテッド | Method for forming thin film photovoltaic interconnects using a self-aligned process |
US20080203490A1 (en) * | 2007-02-28 | 2008-08-28 | Feilchenfeld Natalie B | Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for bicmos integration |
CN101447456A (en) * | 2007-11-30 | 2009-06-03 | 东部高科股份有限公司 | Method for fabricating semiconductor device |
CN101752247A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method for automatically collimating and forming Zener diode |
CN101847596A (en) * | 2009-03-25 | 2010-09-29 | 旺宏电子股份有限公司 | Patterning method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |