CN101383280B - Preparation of grid injection masking layer based on negative photoresist - Google Patents
Preparation of grid injection masking layer based on negative photoresist Download PDFInfo
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- CN101383280B CN101383280B CN200710094077XA CN200710094077A CN101383280B CN 101383280 B CN101383280 B CN 101383280B CN 200710094077X A CN200710094077X A CN 200710094077XA CN 200710094077 A CN200710094077 A CN 200710094077A CN 101383280 B CN101383280 B CN 101383280B
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- negative photoresist
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- photoetching
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Abstract
The invention discloses a method for preparing a grid injection mask layer based on negative photoresist, which comprises the following steps: firstly, the negative photoresist is coated; then, the photoetching development is carried out by using a grid photoetching mask plate; finally, the negative photoresist which is remained after development in the second step is used for forming the injection mask layer, and a grid is injected. The method can be used after the grid is etched and can also be used after the side wall of the grid is completed. The grid injection mask layer which is prepared by the method can greatly increase the injected voltage and energy, the partial pressure of the grid is smaller, meanwhile, the influence for two source-drain electrodes is avoided in the prior art, moreover, compared with the prior art, the method only increases one photoetching time, but has no need to increase the number of the photoetching mask plate, is beneficial for cost control, and can be widely used for a manufacture process of a semiconductor device.
Description
Technical field
The present invention relates to the preparation method that a kind of grid injects mask, particularly a kind of preparation method of the grid injection masking layer based on negative photoresist.
Background technology
Two kinds of photoresists are arranged in the semiconductor manufacturing, are respectively positive photoresist and negative photoresist.The exposure area of positive photoresist is removed when developing, and the pattern that carries out behind the photoetching development with positive photoresist is the same with pattern on the lithography mask version.And negative photoresist is just in time opposite, and it will not be removed when developing the exposure area, and the pattern that carries out behind the photoetching development with negative photoresist is opposite with pattern on the lithography mask version.In the traditional semiconductor fabrication technology, the problem that the grid that the dividing potential drop of solution grid itself causes exhaust, the one, the method for employing attenuate gate; The 2nd, adopt grid to inject the method for mixing.In the second approach, the conventional at present mask for use positive photoresist and source/leakage (Source/Drain) prepares the mask layer (as Fig. 1) that the grid injection is mixed.In this method, be subjected to the restriction of source/drain region, the injecting voltage of grid and implantation dosage all can not be too big, otherwise can destroy the electrical property of source/drain region.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of preparation method of the grid injection masking layer based on negative photoresist, and the grid injection masking layer of this method preparation can make the grid injection condition not be subjected to the restriction in source/drain region.
For solving the problems of the technologies described above, the preparation method of the grid injection masking layer based on negative photoresist of the present invention may further comprise the steps:
(1) on silicon chip, applies negative photoresist;
(2) carry out photoetching development with the grid lithography mask version;
(3) utilize the negative photoresist pattern that stays after the development in the step (2) to make injection masking layer, carry out grid and inject.
The mask layer that the prepared grid of the method according to this invention injects, grid lithography mask version when having utilized negative photoresist and being used for grid etch before is prepared, only increase a photoetching but do not increase the quantity of lithography mask version, help controlling manufacturing cost.And the mask layer that prepared grid injects can improve the voltage and the energy of injection greatly, makes that the dividing potential drop of grid is littler, has avoided leaking for the source in the traditional handicraft influence at the two poles of the earth simultaneously.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is that existing grid inject the doping process schematic diagram;
Fig. 2 is preparation method's flow chart of the present invention;
Fig. 3 is a specific embodiment of the present invention;
Fig. 4 is another specific embodiment of the present invention.
Embodiment
In the present invention, select negative photoresist and the grid lithography mask version (lithography mask version of using when being grid etch for use, define the position of grid during grid etch with positive photoresist and grid lithography mask version), before needs inject doping to grid, on silicon chip, apply negative photoresist, and carry out photoetching development with the grid lithography mask version, form the mask layer that the negative photoresist pattern injects as grid.Its concrete preparation flow is: apply earlier negative photoresist on silicon chip; Then carry out photoetching development with the grid lithography mask version; Utilize the negative photoresist pattern that stays after developing in the step (2) to make injection masking layer at last, carry out grid and inject.
Above-mentioned grid injects and can carry out after grid etch is finished, be that the preparation of grid injection masking layer of the present invention can be placed on after grid etch finishes, also can be placed on grid curb wall (spacer) complete after (as Fig. 3), i.e. after the etching that the preparation of grid injection masking layer is placed on grid curb wall is finished.
Utilize the prepared grid injection masking layer of method of the present invention can improve the voltage and the energy of injection greatly, make that the dividing potential drop of grid is littler, avoided leaking for the source in the traditional handicraft influence at the two poles of the earth simultaneously.Be placed on grid etch and carry out the technology and traditional handicraft comparison that grid injects after finishing, be equivalent to add a photoetching, for the requirement of photoetching alignment precision than higher; After grid curb wall is finished, carry out technology that grid injects with on a kind of situation compare, changed the order of injecting, owing to the protection of grid curb wall has been arranged during the grid injection, so can relax the required precision of photoetching alignment.
The preparation method of the grid injection masking layer based on negative photoresist of the present invention, the lithography mask version of using when adopting grid etch does not increase extra lithography mask version, has promptly improved the utilization rate of this lithography mask version, so help controlling manufacturing cost.
Claims (3)
1. the preparation method based on the grid injection masking layer of negative photoresist is characterized in that, this preparation method comprises:
(1) on silicon chip, applies negative photoresist;
(2) carry out photoetching development with the grid lithography mask version;
(3) utilize the negative photoresist pattern that stays after the development in the step (2) to make injection masking layer, carry out grid and inject.
2. according to the described preparation method of claim 1, it is characterized in that: the preparation of described grid injection masking layer is carried out after grid etch is finished.
3. according to the described preparation method of claim 1, it is characterized in that: the preparation of described grid injection masking layer is to carry out after the side wall etching of grid is finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710094077XA CN101383280B (en) | 2007-09-07 | 2007-09-07 | Preparation of grid injection masking layer based on negative photoresist |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710094077XA CN101383280B (en) | 2007-09-07 | 2007-09-07 | Preparation of grid injection masking layer based on negative photoresist |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101383280A CN101383280A (en) | 2009-03-11 |
| CN101383280B true CN101383280B (en) | 2010-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200710094077XA Active CN101383280B (en) | 2007-09-07 | 2007-09-07 | Preparation of grid injection masking layer based on negative photoresist |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107393814A (en) * | 2017-08-10 | 2017-11-24 | 中国科学院上海微系统与信息技术研究所 | A kind of MOS power devices and preparation method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468147B (en) * | 2010-11-01 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of forming gate of semiconductor devices |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5976902A (en) * | 1998-08-03 | 1999-11-02 | Industrial Technology Research Institute | Method of fabricating a fully self-aligned TFT-LCD |
| US6444404B1 (en) * | 2000-08-09 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions |
| US6689541B1 (en) * | 2001-06-19 | 2004-02-10 | Advanced Micro Devices, Inc. | Process for forming a photoresist mask |
| CN1691297A (en) * | 2004-04-28 | 2005-11-02 | 尔必达存储器股份有限公司 | Method for manufacturing a semiconductor device having a dual-gate structure |
| KR20070087360A (en) * | 2006-02-23 | 2007-08-28 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device |
-
2007
- 2007-09-07 CN CN200710094077XA patent/CN101383280B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5976902A (en) * | 1998-08-03 | 1999-11-02 | Industrial Technology Research Institute | Method of fabricating a fully self-aligned TFT-LCD |
| US6444404B1 (en) * | 2000-08-09 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions |
| US6689541B1 (en) * | 2001-06-19 | 2004-02-10 | Advanced Micro Devices, Inc. | Process for forming a photoresist mask |
| CN1691297A (en) * | 2004-04-28 | 2005-11-02 | 尔必达存储器股份有限公司 | Method for manufacturing a semiconductor device having a dual-gate structure |
| KR20070087360A (en) * | 2006-02-23 | 2007-08-28 | 주식회사 하이닉스반도체 | Method for fabricating the same of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107393814A (en) * | 2017-08-10 | 2017-11-24 | 中国科学院上海微系统与信息技术研究所 | A kind of MOS power devices and preparation method thereof |
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| CN101383280A (en) | 2009-03-11 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206 Jinqiao Road, Pudong New Area Jinqiao Export Processing Zone, Shanghai, 1188 Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |