CN101901786B

CN101901786B - Preparation method for integrated circuit containing DMOS transistor

Info

Publication number: CN101901786B
Application number: CN2009100573144A
Authority: CN
Inventors: 陈华伦; 陈瑜; 熊涛; 罗啸; 陈雄斌
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-05-26
Filing date: 2009-05-26
Publication date: 2012-04-18
Anticipated expiration: 2029-05-26
Also published as: CN101901786A

Abstract

The invention discloses a preparation method for an integrated circuit containing a DMOS transistor. After a polycrystalline silicon grid is formed, the method comprises the following steps of: 1) depositing a film used as a side wall; 2) covering a photoresist on the film which is positioned on a high-pressure drifting and injecting region in the DMOS transistor, provided with a preformed rigid mask and is used as the side wall by using a photoetching process; 3) etching the film used as the side wall to form the side wall on one side of the polycrystalline silicon grid and form the rigid mask on the other side of the polycrystalline silicon grid; 4) extracting the formed body out of the injecting region; 5) forming a source/drain region; and 6) preparing self-aligned metal silicide. The preparation method can reduce the size of devices so as to ensure the efficiency of the devices.

Description

The preparation method who comprises the transistorized integrated circuit of DMOS

Technical field

The present invention relates to the preparation method of the transistorized integrated circuit of a kind of DMOS of comprising.

Background technology

In power and high voltage integrated circuit manufacturing, usually can adopt DMOS (lateral metal oxide semiconductor) device that big output current and high output voltage is provided.In the structure of DMOS, polysilicon gate can directly have influence on the puncture voltage and the conducting resistance of device to drain electrode exit (injection region or silicon metallizing zone are leaked in the source) spacing.

At existing processes flow process such as Fig. 1-shown in Figure 6, for:

(1) forms after the polysilicon gate, in the film (see figure 1) of substrate surface deposit one as side wall;

(2) etching side wall film forms the side wall (see figure 2) in the both sides of polysilicon gate;

(3) adopt photoetching process and ion implantation technology, substep organizator injection region, source region and drain region, Fig. 3 is for forming source-drain area structural representation afterwards;

(4) then at the substrate surface deposit hard mask layer that forms said structure, this hard mask layer can be silicon nitride or silica;

(5) adopt photoetching process to make photoresist cover the zone of top except that the drain region, high pressure drift injection region; A part that comprises polysilicon gate; The silicon face of the side wall of this polysilicon gate part side and high pressure drift injection region; Also can cover the upper surface in sub-fraction drain region, the hard mask layer in the etch step four is then removed photoresist afterwards;

(6) be mask with the hard mask layer that forms in the step 5, carry out the preparation (see figure 6) of self-aligned metal silicate.

In the above-mentioned technological process,, the metallization process of silicon and source be divided into Twi-lithography because leaking injection technology, and because there is certain relative displacement in the existence of alignment precision between two layer photoetchings.In order to guarantee that the silicon metallizing zone is positioned within the drain region, the size in drain region can be bigger than metallized area.So just cause the overall dimensions of device to become big, influenced the efficient of device.

Summary of the invention

The technical problem that the present invention will solve provides the preparation method of the transistorized integrated circuit of a kind of DMOS of comprising, and it can reduce prepared DMOS device size.

For solving the problems of the technologies described above, the preparation method who comprises the transistorized integrated circuit of DMOS of the present invention after polysilicon gate forms, comprises the steps:

1) on the substrate of said formation polysilicon gate deposit as the film of side wall;

2) utilize photoetching process that photoresist is covered to be arranged in the predetermined film that forms hard mask in top, high pressure drift injection region of said DMOS transistor as side wall;

3) the said film as side wall that exposes of etching form side wall in a side of said polysilicon gate, and a side that is positioned on the high pressure drift injection region at said polysilicon gate forms hard mask, removes the photoresist in the step 2 afterwards;

4) adopting photoetching process to define the position that body is drawn the injection region, is that mask carries out ion and injects organizator and draw the injection region with the photoresist in the photoetching process afterwards, removes said photoresist then;

5) adopting photoetching process to define the position of source-drain area, is that mask carries out the source and leaks ion and inject and form source region and drain region respectively with the photoresist in the photoetching process afterwards, removes said photoresist then;

6) then utilize the protection of said hard mask, carry out the preparation of self-aligned metal silicate, the polysilicon gate surface of drawing surface, injection region, surface, source region at body, the drain region is surperficial and does not cover said hard mask forms self-aligned metal silicate.

The preparation method who comprises the transistorized integrated circuit of DMOS of the present invention; Utilize to form the hardmask that the dry etch process of side wall forms simultaneously between drain electrode draw-out area and polysilicon gate, make metallization process that injection technology and silicon are leaked in follow-up source to have and utilize this zone simultaneously as masking jig.So just avoid the alignment issues of Twi-lithography alignment, the high tension apparatus drain region of preparation and silicon metallizing district can have been overlapped fully, thereby reduced size of devices, guaranteed the efficient of device.Simultaneously; Preparation method of the present invention directly adopts side wall to form technology and forms hard mask at the drain electrode exit, has omitted the hard mask layer of the independent deposit etching in original technology; Simultaneously; Because the existence of hard mask is arranged, can make the photoetching window that source-drain area injects in the subsequent technique become big, reduce the requirement of photoetching process.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 to Fig. 6 is and the corresponding cross section structure sketch map of the transistorized preparation flow of existing DMOS;

Fig. 7 is the preparation flow sketch map that comprises the transistorized integrated circuit of DMOS of the present invention;

Fig. 8 to Figure 11 is and the corresponding cross section structure sketch map of preparation flow of the present invention.

Embodiment

The preparation method who comprises the transistorized integrated circuit of DMOS of the present invention, after polysilicon gate formed, idiographic flow can comprise the steps: referring to Fig. 7

1) deposit is as the film (see figure 8) of side wall on the substrate that forms polysilicon gate, and this film is the material that is conventionally used as side wall, can be silicon nitride film, also can be silicon oxide film;

2) utilize photoetching process that photoresist is covered to be arranged in the predetermined film that forms hard mask in top, high pressure drift injection region of said DMOS transistor as side wall; Comprise the part on a part and the high pressure drift injection region of polysilicon gate, will be scheduled to form the position in drain region in principle and come out;

3) etching (being generally dry etching) expose as the film of side wall; Side at polysilicon gate after the etching forms side wall; And a side that is positioned on the high pressure drift injection region at polysilicon gate forms the hard mask (see figure 9), removes the photoresist in the step 2 afterwards;

4) adopting photoetching process to define the position that body is drawn the injection region, is that mask carries out ion and injects organizator and draw the injection region with the photoresist in the photoetching process afterwards, removes photoresist then;

5) adopting photoetching process to define the position of source-drain area, is that mask carries out the source and leaks ion and inject and form source region and drain region (see figure 10) respectively with the photoresist in the photoetching process afterwards, removes photoresist then.In this time photoetching, because the protection of hard mask is arranged, the photoetching window in source region and drain region can be bigger slightly than original size setting, reduces the photoetching process requirement;

6) then utilize the protection of hard mask, carry out the preparation of self-aligned metal silicate, the polysilicon gate surface of drawing surface, injection region, surface, source region at body, the drain region is surperficial and does not cover hard mask forms self-aligned metal silicate (seeing Figure 11).

3. comprise the preparation method of the transistorized integrated circuit of DMOS according to claim 1, it is characterized in that: the etching in the said step 3 adopts dry etch process.

Claims

1. a preparation method who comprises the transistorized integrated circuit of DMOS after polysilicon gate forms, comprises the steps:

3) the said film as side wall that exposes of dry etching form side wall in a side of said polysilicon gate, and a side that is positioned on the high pressure drift injection region at said polysilicon gate forms hard mask, removes the photoresist in the step 2 afterwards;

2. comprise the preparation method of the transistorized integrated circuit of DMOS according to claim 1, it is characterized in that: the film that is used as side wall in the said step 1 is silicon nitride film or silicon oxide film.