CN103107084A - Etching process method of polycide insulator polycide (PIP) polycrystalline silicon - Google Patents
Etching process method of polycide insulator polycide (PIP) polycrystalline silicon Download PDFInfo
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- CN103107084A CN103107084A CN2011103600704A CN201110360070A CN103107084A CN 103107084 A CN103107084 A CN 103107084A CN 2011103600704 A CN2011103600704 A CN 2011103600704A CN 201110360070 A CN201110360070 A CN 201110360070A CN 103107084 A CN103107084 A CN 103107084A
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- polysilicon
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- polycrystalline silicon
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- side wall
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Abstract
The invention discloses an etching process method of polycide insulator polycide (PIP) polycrystalline silicon. The etching process method comprises the following steps that (1) gate-oxide is generated on a silicon substrate, a layer of polycrystalline silicon is deposited on the gate-oxide and photoetching and etching are performed on the polycrystalline silicon so that a polycrystalline silicon grid is generated to serve as bottom polycrystalline silicon of the PIP polycrystalline silicon; and a layer of flank oxidation film is deposited on a whole silicon slice to serve as a middle insulating layer of the PIP polycrystalline silicon, then a layer of polycrystalline silicon is further deposited to serve as top polycrystalline silicon of the PIP polycrystalline silicon, a protective film is deposited on the top polycrystalline silicon of the PIP polycrystalline silicon, the photoetching is performed on the PIP polycrystalline silicon, the etching is performed on the protective film and the top polycrystalline silicon of the PIP polycrystalline silicon and photoresist is removed; and (2) the oxide film flank is etched and the flank is formed. According to the method, the protective film is deposited at the top of an existing PIP polycrystalline silicon structure so that loss in the process of flank etching of the PIP polycrystalline silicon is reduced and stability of the value of resistance of the PIP polycrystalline silicon in a crystal plate face is achieved.
Description
Technical field
The invention belongs to the semiconductor integrated circuit manufacturing process, be specifically related to a kind of PIP polycrystalline silicon etching process method.
Background technology
BCD (Bipolar CMOS DMOS, be called for short BCD, BCD technique can be made bipolar tube Bipolar on same chip, complementary metal oxide semiconductors (CMOS) CMOS and diffused metal oxide emiconductor DMOS device) during technique makes, need to obtain side wall by dry etch process, traditional technological process is as follows: 1) growth grid oxygen 2 on silicon base 1, deposition one deck polysilicon on grid oxygen 2, polysilicon photoetching and etching form polysilicon gate 4 (polysilicon gate 4 is as the bottom polysilicon of PIP polysilicon); Deposition one deck side wall oxide-film 3 (side wall oxide-film 3 is as the intermediate insulating layers of PIP polysilicon) on the total silicon sheet, and then deposition one deck polysilicon is as the top polysilicon 6 of PIP polysilicon, the photoetching of PIP polysilicon, top polysilicon 6 etchings of PIP polysilicon, and the removal photoresist, as shown in Figure 1; 2) etching side wall oxide-film 3 (being the intermediate insulating layer of PIP polysilicon), and form grid oxidation film side wall 9, as shown in Figure 2.Because lacking in the intermediate insulating layer etching effectively, the polysilicon (poly) that is positioned at polysilicon-insulating layer-polysilicon (PIP) structure top on existing technique basis protects; and it is very large that PIP itself opens area; in the situation that do not make when the side wall etching PIP top polysilicon loss larger to the selection of polysilicon than high in the etching of intermediate insulating layer, even can reach 25% loss amount.This loss can cause resistance value to increase, and because the inhomogeneity impact in the etched wafer face, it is unstable that the inconsistent meeting that in wafer face, PIP loses causes device performance to distribute in wafer face.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of PIP polycrystalline silicon etching process method, improves the loss of PIP polysilicon in the time of the side wall etching, thereby reaches the resistance of stablizing PIP polysilicon in wafer face.
For solving the problems of the technologies described above, the invention provides a kind of PIP polycrystalline silicon etching process method, comprise the steps:
1) growth grid oxygen on silicon base, deposition one deck polysilicon on grid oxygen, polysilicon photoetching and etching form polysilicon gate as the bottom polysilicon of PIP polysilicon; Deposition one deck side wall oxide-film is as the intermediate insulating layer of PIP polysilicon on the total silicon sheet, and then deposition one deck polysilicon is as the top polysilicon of PIP polysilicon, deposit diaphragm on the polysilicon of the top of PIP polysilicon, then carry out the photoetching of PIP polysilicon, the top etching polysilicon of diaphragm and PIP polysilicon, photoresist is removed;
2) erosion of oxide film sidewall stela and side wall form.
In step 1) in, described diaphragm is nitride film or nitrogen oxidation film.
In step 1) in, the thickness of described diaphragm is 5%～100% of side wall oxide thickness.
In step 1) in, the top etching polysilicon of described diaphragm and PIP polysilicon is completed in etching polysilicon board one.
In step 2) in, in the time of described oxide film sidewall stela erosion, the side wall oxide-film is greater than 4 to the etching selection ratio of diaphragm.
In step 2) in, C is adopted in described oxide film sidewall stela erosion
5F
8And O
2Gas; C
5F
8The flow of gas is 5sccm～100sccm, O
2The flow of gas is 5～100sccm.Perhaps,
In step 2) in, C is adopted in described oxide film sidewall stela erosion
4F
6And O
2Gas; C
4F
6The flow of gas is 5sccm～100sccm, O
2The flow of gas is 5～100sccm.
Compared to the prior art; the present invention has following beneficial effect: the present invention has certain thickness diaphragm at deposited on top one deck of existing PIP polysilicon structure; then by adjusting the side wall etching condition etch rate different with the PIP diaphragm to side wall; diaphragm had the etching of certain selection ratio when the etching side wall; and then make on the basis of the very little thickness diaphragm of loss the polysilicon at the top in the PIP polysilicon structure is carried out complete protection, thereby reach the resistance of stablize the interior PIP polysilicon of wafer face.
Description of drawings
Fig. 1 is the PIP section of structure before the side wall etching in traditional handicraft;
Fig. 2 is the PIP section of structure after the side wall etching in traditional handicraft;
Fig. 3 is the PIP section of structure before the side wall etching in the present invention;
Fig. 4 is the PIP section of structure after the side wall etching in the present invention;
In figure, description of reference numerals is as follows:
1 is silicon base, and 2 is grid oxygen, the 3rd, and side wall oxide-film (before etching), the 4th, polysilicon gate, the 5th, an oxygen, the top polysilicon of the 6th, PIP polysilicon, the 8th, diaphragm, the 9th, oxide-film side wall (after etching).
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
As shown in Figure 3 and Figure 4, a kind of PIP polycrystalline silicon etching process of the present invention method specifically comprises the steps:
1) as shown in Figure 3, growth grid oxygen 2 on silicon base 1, deposition one deck polysilicon on grid oxygen 2, polysilicon photoetching and etching form polysilicon gate 4 (polysilicon gate 4 is as the bottom polysilicon of PIP polysilicon); Deposition one deck side wall oxide-film 3 (side wall oxide-film 3 is as the intermediate insulating layers of PIP polysilicon) on the total silicon sheet, and then deposition one deck polysilicon is as the top polysilicon 6 of PIP polysilicon, carry out diaphragm 8 depositions on the top of PIP polysilicon polysilicon 6, then carry out the photoetching of PIP polysilicon, top polysilicon 6 etchings of diaphragm 8 and PIP polysilicon (the top polysilicon 6 of diaphragm 8 and PIP polysilicon is etched in etching polysilicon board one and completes), and remove photoresist; Wherein, the diaphragm 8 of deposition is nitride film or nitrogen oxidation film; The thickness of diaphragm 8 is 5%～100% of side wall oxide-film 3 thickness (being the intermediate insulation layer thickness of PIP polysilicon);
2) as shown in Figure 4, etching side wall oxide-film 3 forms oxide-film side wall 9.In the time of oxide-film side wall 9 etching, the etching selection ratio of 3 pairs of diaphragms 8 of side wall oxide-film is greater than 4.Use C in the time of etching side wall oxide-film
5F
8And O
2Mist; Perhaps use C when etching side wall oxide-film
4F
6And O
2Mist; C
5F
8And C
4F
6The flow of gas is 5sccm～100sccm, O
2Gas flow is 5～100sccm.
The present invention has certain thickness diaphragm at deposited on top one deck of existing PIP polysilicon structure; then by adjusting the side wall etching condition etch rate different with the PIP diaphragm to side wall; diaphragm had the etching of certain selection ratio when the etching side wall; and then make on the basis of the very little thickness diaphragm of loss the polysilicon at the top in the PIP polysilicon structure is carried out complete protection, thereby reach the resistance of stablize the interior PIP polysilicon of wafer face.
Claims (9)
1. a PIP polycrystalline silicon etching process method, is characterized in that, comprises the steps:
1) growth grid oxygen on silicon base, deposition one deck polysilicon on grid oxygen, polysilicon photoetching and etching form polysilicon gate as the bottom polysilicon of PIP polysilicon; Deposition one deck side wall oxide-film is as the intermediate insulating layer of PIP polysilicon on the total silicon sheet, and then deposition one deck polysilicon is as the top polysilicon of PIP polysilicon, deposit diaphragm on the polysilicon of the top of PIP polysilicon, then carry out the photoetching of PIP polysilicon, the top etching polysilicon of diaphragm and PIP polysilicon, photoresist is removed;
2) erosion of oxide film sidewall stela and side wall form.
2. the method for claim 1, is characterized in that, in step 1) in, described diaphragm is nitride film or nitrogen oxidation film.
3. method as claimed in claim 1 or 2, is characterized in that, in step 1) in, the thickness of described diaphragm is 5%～100% of side wall oxide thickness.
4. the method for claim 1, is characterized in that, in step 1) in, the top etching polysilicon of described diaphragm and PIP polysilicon is completed in etching polysilicon board one.
5. the method for claim 1, is characterized in that, in step 2) in, in the time of described oxide film sidewall stela erosion, the side wall oxide-film is greater than 4 to the etching selection ratio of diaphragm.
6. method as described in claim 1 or 5, is characterized in that, in step 2) in, C is adopted in described oxide film sidewall stela erosion
5F
8And O
2Gas.
7. method as described in claim 1 or 5, is characterized in that, in step 2) in, C is adopted in described oxide film sidewall stela erosion
4F
6And O
2Gas.
8. method as claimed in claim 6, is characterized in that, in step 2) in, C
5F
8The flow of gas is 5sccm～100sccm, O
2The flow of gas is 5～100sccm.
9. method as claimed in claim 7, is characterized in that, in step 2) in, C
4F
6The flow of gas is 5sccm～100sccm, O
2The flow of gas is 5～100sccm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103600704A CN103107084A (en) | 2011-11-14 | 2011-11-14 | Etching process method of polycide insulator polycide (PIP) polycrystalline silicon |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103600704A CN103107084A (en) | 2011-11-14 | 2011-11-14 | Etching process method of polycide insulator polycide (PIP) polycrystalline silicon |
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| CN103107084A true CN103107084A (en) | 2013-05-15 |
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| CN2011103600704A Pending CN103107084A (en) | 2011-11-14 | 2011-11-14 | Etching process method of polycide insulator polycide (PIP) polycrystalline silicon |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436750B1 (en) * | 1999-08-25 | 2002-08-20 | Infineon Technologies Ag | Method of fabricating integrated circuits having transistors and further semiconductor elements |
| US20050142741A1 (en) * | 2003-12-29 | 2005-06-30 | Hynix Semiconductor Inc. | Method for manufacturing flash memory device |
| CN101901786A (en) * | 2009-05-26 | 2010-12-01 | 上海华虹Nec电子有限公司 | Preparation method for integrated circuit containing DMOS transistor |
-
2011
- 2011-11-14 CN CN2011103600704A patent/CN103107084A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436750B1 (en) * | 1999-08-25 | 2002-08-20 | Infineon Technologies Ag | Method of fabricating integrated circuits having transistors and further semiconductor elements |
| US20050142741A1 (en) * | 2003-12-29 | 2005-06-30 | Hynix Semiconductor Inc. | Method for manufacturing flash memory device |
| CN101901786A (en) * | 2009-05-26 | 2010-12-01 | 上海华虹Nec电子有限公司 | Preparation method for integrated circuit containing DMOS transistor |
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Application publication date: 20130515 |