CN102290349A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN102290349A CN102290349A CN2010102080568A CN201010208056A CN102290349A CN 102290349 A CN102290349 A CN 102290349A CN 2010102080568 A CN2010102080568 A CN 2010102080568A CN 201010208056 A CN201010208056 A CN 201010208056A CN 102290349 A CN102290349 A CN 102290349A
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Abstract
The invention provides a semiconductor structure and a forming method thereof. The method comprises the following steps of providing a wafer and forming an oxide layer for covering a polysilicon layer, wherein the reverse side of the wafer is provided with the polysilicon layer, and the front side of the wafer is provided with a semiconductor device. The problem of damage of a cleaning process to the polysilicon layer at the reverse side of the wafer on the rear section of a processing line is solved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor structure and forming method thereof.
Background technology
Along with integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements that is comprised is also more and more, and this development makes crystal column surface can't provide enough areas to make required interconnection line.
For the interconnection line demand after satisfying element and dwindling, the very large scale integration technology institute a kind of method of employing usually that is designed to of two-layer and two-layer above multiple layer metal interconnection line.The process that semiconductor is made is normally at processing line leading portion (front end ofline, FEOL) form MOS transistor, and the dielectric layer between the orlop in MOS transistor and the interconnection layer, (back end of line BEOL) forms the design of described two-layer and two-layer above multiple layer metal interconnection line at the processing line back segment.Be to disclose a kind of method that in semiconductor device, forms metal interconnecting layer in the Chinese patent literature of " 02160425.8 " for example at application number.
In described processing line last part technology, just in the process that forms the multilayer interconnection line, to for example after the etch step that forms interconnected pores or interconnection channel, need to clean through repeatedly cleaning, after the step of filling interconnected pores or interconnection channel, need to clean.Usually, the one side that wafer is formed semiconductor device is called the front, and another side is called the back side.When carrying out the processing line back segment, chip back surface has one deck polysilicon layer (U-POLY), it is at the accessory substance of FEOL technical process, its evenness has certain influence to last part technology stability, if U-POLY has damage, can cause chip back surface evenness variation and visually also not satisfy the requirement of wafer slice, owing to be difficult to control on the etching technics of cleaning soup among the BEOL to U-POLY, therefore U-POLY easily in the process of BEOL by uneven etching (ETCH), cause chip back surface to grow dim, wafer is unusual.
So improved technical scheme in the prior art: be to change to clean soup, increase the composition that suppresses the U-POLY etching.Clean soup but change, the cycle is long, has a big risk, and walking the new material checking needs the above time of half a year at least.
Summary of the invention
The damage that cleaning caused the U-POLY of chip back surface when the technical problem that the present invention solves was the processing line back segment.
In order to address the above problem, the invention provides a kind of formation method of semiconductor structure, comprise step:
Wafer is provided, and described chip back surface has polysilicon layer, and described front wafer surface has semiconductor device;
Form the oxide skin(coating) that covers described polysilicon layer.
Preferably, described oxide skin(coating) is to utilize the method for oxidation to form.
Preferably, the parameter of described oxidation is that the pressure in the chamber is 50 millitorr to 100 millitorrs, and radio-frequency power is 300 watts to 500 watts, and the O2 flow is 50sccm to 250sccm, and temperature is 200 ℃ to 300 ℃.
Preferably, the thickness of described oxide skin(coating) is 100 dust to 200 dusts.
Preferably, the thickness of described polysilicon layer is that 2000 dusts are to 4000 dusts.
Accordingly, the present invention also provides a kind of semiconductor structure, comprising:
Wafer, described chip back surface has polysilicon layer, and described front wafer surface has semiconductor device;
Described polysilicon layer surface coverage has oxide skin(coating).
Preferably, described oxide is a silicon dioxide.
Preferably, the thickness of described oxide skin(coating) is 100 dust to 200 dusts.
Preferably, the thickness of described polysilicon layer is that 2000 dusts are to 4000 dusts.
Compared with prior art, the present invention mainly has the following advantages:
The present invention forms oxide skin(coating) by the method for utilizing the oxidation chip back surface at chip back surface polysilicon layer is protected, and the polysilicon layer damage to chip back surface is little in the process that forms oxide skin(coating), the efficient height, and cost is low.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is the formation method flow diagram of semiconductor structure of the present invention;
Fig. 2 is the schematic diagram of the formation method of semiconductor structure of the present invention.
Embodiment
By background technology as can be known, in described processing line last part technology, just in the process that forms the multilayer interconnection line, be through repeatedly cleaning, for example after the etch step that forms interconnected pores or interconnection channel, need to clean, after the step of filling interconnected pores or interconnection channel, need to clean.Usually, the one side that wafer is formed semiconductor device is called the front, and another side is called the back side.When carrying out the processing line back segment, chip back surface has one deck U-POLY and since BEOL in the etching technics of cleaning soup to U-POLY on be difficult to control, so U-POLY easily in the process of BEOL by uneven etching (ETCH), cause chip back surface to grow dim, wafer is unusual.
The present inventor thinks through a large amount of experiments: utilize cleaning soup in the BEOL process to oxide, for example the slower characteristics of the etch rate of silicon dioxide consider to utilize the protective layer of oxide as chip back surface.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 is the formation method flow diagram of semiconductor structure of the present invention, and Fig. 2 is the schematic diagram of the formation method of semiconductor structure of the present invention.The present invention is described in detail below in conjunction with Fig. 1 and Fig. 2.The formation method of semiconductor structure of the present invention comprises the following steps:
Step S10 provides wafer.
As shown in Figure 2, silicon that described wafer 10 can be monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe), also can be silicon-on-insulator (SOI), can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Can also be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes or the substrate that is not patterned in addition.
In the present embodiment, the one side of described wafer 10 is formed with semiconductor device 20, and the one side that is formed with described semiconductor device 20 is called the front, and another side is called the back side, and for example described semiconductor device can be the MOS device.When carrying out the processing line back segment, chip back surface has one deck polysilicon layer (U-POLY) 30, and the thickness of described polysilicon layer does not generally wait to 4000 dusts at 2000 dusts, and it is slightly variant to look the technology difference.
Step S20 forms the oxide skin(coating) that covers U-POLY.
Concrete, in the present embodiment, as shown in Figure 2, utilize the equipment of cineration technics, for example preferably utilize Ultima-III Furnace, Ultima-III Furnace to have to wafer isotropic reaction properties.
In the present embodiment, wafer 10 is positioned between the last bottom crown in the chamber 15, gives last bottom crown making alive, make and form electric field between the bottom crown.
The concrete parameter of method for oxidation is: described wafer 10 is positioned in the chamber 15, and the pressure in the chamber 15 is 50 millitorr to 100 millitorrs, and radio-frequency power is 300 watts to 500 watts, and the O2 flow is 50sccm to 250sccm, and temperature is 200 ℃ to 300 ℃.In oxidation technology, in described chamber, oxygen is ionized is plasma, the plasma of oxygen is injected into chip back surface under described electric field action then, and the degree of depth that ion injects is less than 300 dusts.The plasma of oxygen and the polysilicon layer of chip back surface 30 react, and generate oxide skin(coating) 40, for example silicon dioxide.In the present embodiment, the thickness of described oxide skin(coating) 40 is 100 dust to 200 dusts.
Utilize described oxide skin(coating) also can utilize other method, for example the method for chemical vapor deposition or thermal oxide growth forms.
In follow-up cleaning process, the cleaning soup that for example uses is EKC270, described oxide skin(coating) is not easy to be cleaned the soup etching mutually, for example described cleaning soup is 0.04 dust/per minute to the etch rate of oxide skin(coating), etch rate to TEOS is 0.27 dust/per minute, etch rate to BPSG is 1.14 dusts/per minute, is 0.39 dust/per minute to the etch rate of silicon nitride.Therefore can effectively protect the polysilicon layer of chip back surface not sustain damage, and the efficient height, cost is low.
Accordingly, the present invention also provides a kind of semiconductor structure, comprising:
Wafer, described chip back surface has polysilicon layer, and described front wafer surface has semiconductor device;
Described polysilicon layer surface coverage has oxide skin(coating).
Preferably, described oxide is a silicon dioxide.
Preferably, the thickness of described oxide skin(coating) is 100 dust to 200 dusts.
Preferably, the thickness of polysilicon layer is that 2000 dusts are to 4000 dusts.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (9)
1. the formation method of a semiconductor structure is characterized in that, comprises step:
Wafer is provided, and described chip back surface has polysilicon layer, and described front wafer surface has semiconductor device;
Form the oxide skin(coating) that covers described polysilicon layer.
2. the formation method of semiconductor structure according to claim 1 is characterized in that, described oxide skin(coating) is to utilize the method for oxidation to form.
3. the formation method of semiconductor structure according to claim 2 is characterized in that, the parameter of described oxidation is that the pressure in the chamber is 50 millitorr to 100 millitorrs, and radio-frequency power is 300 watts to 500 watts, O
2Flow is 50sccm to 250sccm, and temperature is 200 ℃ to 300 ℃.
4. the formation method of semiconductor structure according to claim 3 is characterized in that, the thickness of described oxide skin(coating) is 100 dust to 200 dusts.
5. the formation method of semiconductor structure according to claim 4 is characterized in that, the thickness of described polysilicon layer is that 2000 dusts are to 4000 dusts.
6. a semiconductor structure is characterized in that, comprising:
Wafer, described chip back surface has polysilicon layer, and described front wafer surface has semiconductor device;
Described polysilicon layer surface coverage has oxide skin(coating).
7. semiconductor structure according to claim 6 is characterized in that, described oxide is a silicon dioxide.
8. semiconductor structure according to claim 7 is characterized in that, the thickness of described oxide skin(coating) is 100 dust to 200 dusts.
9. semiconductor structure according to claim 8 is characterized in that, the thickness of described polysilicon layer is that 2000 dusts are to 4000 dusts.
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| CN2010102080568A CN102290349A (en) | 2010-06-21 | 2010-06-21 | Semiconductor structure and forming method thereof |
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| CN2010102080568A CN102290349A (en) | 2010-06-21 | 2010-06-21 | Semiconductor structure and forming method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811328A (en) * | 2014-03-05 | 2014-05-21 | 上海先进半导体制造股份有限公司 | Method for preventing formation of polycrystalline particles on back face during multi-layer epitaxial growth and back sealing structure |
| CN111681949A (en) * | 2020-06-22 | 2020-09-18 | 长江存储科技有限责任公司 | Method for processing back of wafer |
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| CN1346511A (en) * | 1999-04-01 | 2002-04-24 | 因芬尼昂技术股份公司 | Method of processing monocrystalline semiconductor disk and partially processed semiconductor disk |
| CN1747136A (en) * | 2004-09-10 | 2006-03-15 | 中芯国际集成电路制造(上海)有限公司 | Corrosion of silicon nitride layer with single-chip substrate as back for IC integrated circuit |
| CN101097857A (en) * | 2006-06-28 | 2008-01-02 | 上海华虹Nec电子有限公司 | Method for reducing high concentration doping extension to epitaxial substrate |
| US20080160647A1 (en) * | 2006-12-29 | 2008-07-03 | Texas Instruments Inc. | Thick oxide film for wafer backside prior to metalization loop |
| CN101740525A (en) * | 2008-11-24 | 2010-06-16 | 合晶科技股份有限公司 | Encapsulation structure for wafer backside |
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2010
- 2010-06-21 CN CN2010102080568A patent/CN102290349A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5676042A (en) * | 1979-11-28 | 1981-06-23 | Shindengen Electric Mfg Co Ltd | Field effect transistor for ion sensor |
| CN1346511A (en) * | 1999-04-01 | 2002-04-24 | 因芬尼昂技术股份公司 | Method of processing monocrystalline semiconductor disk and partially processed semiconductor disk |
| CN1747136A (en) * | 2004-09-10 | 2006-03-15 | 中芯国际集成电路制造(上海)有限公司 | Corrosion of silicon nitride layer with single-chip substrate as back for IC integrated circuit |
| CN101097857A (en) * | 2006-06-28 | 2008-01-02 | 上海华虹Nec电子有限公司 | Method for reducing high concentration doping extension to epitaxial substrate |
| US20080160647A1 (en) * | 2006-12-29 | 2008-07-03 | Texas Instruments Inc. | Thick oxide film for wafer backside prior to metalization loop |
| CN101740525A (en) * | 2008-11-24 | 2010-06-16 | 合晶科技股份有限公司 | Encapsulation structure for wafer backside |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811328A (en) * | 2014-03-05 | 2014-05-21 | 上海先进半导体制造股份有限公司 | Method for preventing formation of polycrystalline particles on back face during multi-layer epitaxial growth and back sealing structure |
| CN103811328B (en) * | 2014-03-05 | 2016-06-22 | 上海先进半导体制造股份有限公司 | When preventing multilayer epitaxial from growing, the back side forms method and the back of the body seal structure of polycrystalline particle |
| CN111681949A (en) * | 2020-06-22 | 2020-09-18 | 长江存储科技有限责任公司 | Method for processing back of wafer |
| CN111681949B (en) * | 2020-06-22 | 2021-05-18 | 长江存储科技有限责任公司 | Method for processing back of wafer |
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