CN102110649A - Method for correcting failures of quiescent current in aluminum gate CMOS - Google Patents
Method for correcting failures of quiescent current in aluminum gate CMOS Download PDFInfo
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- CN102110649A CN102110649A CN2009102440518A CN200910244051A CN102110649A CN 102110649 A CN102110649 A CN 102110649A CN 2009102440518 A CN2009102440518 A CN 2009102440518A CN 200910244051 A CN200910244051 A CN 200910244051A CN 102110649 A CN102110649 A CN 102110649A
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Abstract
The invention relates to the manufacture technology of aluminum gate CMOSs (complementary metal oxide semiconductor), in particular to a method for correcting failures of quiescent current in an aluminum gate CMOS. The method is improved on the basis of the traditional manufacture technology of the aluminum gate CMOSs and comprises the step of conducting primary implantation technology of N-shaped irons to increase the surface concentration of the substrate after preparation of an N-shaped substrate. N-shaped irons implanted in the substrate form N wells automatically on the substrate during the diffusion process of a high-temperature furnace tube, so that the influence of the substrate concentration change on the electricity leakage of a PMOS (P-channel metal oxide semiconductor) tube can be reduced and the purpose of correcting failures of quiescent current in a circuit can be achieved.
Description
Technical field
The present invention relates to the manufacture craft of alum gate complementary metal oxide semiconductors (CMOS), be specifically related to a kind of method that alum gate CMOS static electric current lost efficacy of improving.
Background technology
Complementary metal oxide semiconductors (CMOS) (CMOS) is voltage-controlled amplifying device, is the raw material that a kind of large-scale application is made in integrated circuit (IC) chip.CMOS is by PMOS (P type oxide semiconductor) and the common formation of NMOS (N type oxide semiconductor), and PMOS and NMOS are structurally alike fully, and different is the doping type that leak in substrate and source.Briefly, PMOS is on the substrate of N type silicon, forms the doped region of P type by selecting to mix, as the source-drain area of PMOS; NMOS is on the substrate of P type silicon, forms the doped region of N type by selecting to mix, as the source-drain area of NMOS.The manufacture craft of CMOS generally includes N trap CMOS technology, P trap CMOS technology, two trap CMOS technology.P trap CMOS technology is to make the P trench transistor on N type silicon substrate, makes the N trench transistor in the P trap, and its trap can adopt epitaxy, diffusion method or ion injection method to form.P trap CMOS process application gets the earliest, also be use the widest technology, be applicable to the circuit of standard CMOS circuitry and CMOS and bipolar NPN compatibility.
2.0 traditional μ m and above alum gate complementary metal oxide semiconductors (CMOS) manufacture craft generally adopt P trap CMOS manufacture craft, PMOS is the single trap technology that directly is produced on the N type substrate, adopt the transistorized structure of CMOS that this technology makes as shown in Figure 2, among the figure, D is drain electrode, G is a grid, and S is a source electrode, and B is a substrate.A uncertainty of this technology is usually can cause the PMOS parameter fluctuation bigger owing to the fluctuation of N type substrate concentration is big, when N type substrate concentration hour, PMOS leaks electricity easily, makes the quiescent current of entire circuit bigger than normal.
Summary of the invention
The objective of the invention is to defective, a kind of method that alum gate CMOS static electric current lost efficacy of improving is provided, thereby improve the service behaviour of complementary metal oxide semiconductors (CMOS) at existing alum gate complementary metal oxide semiconductors (CMOS) manufacture craft.
For achieving the above object, technical scheme of the present invention is as follows: a kind of method of improving the inefficacy of alum gate CMOS static electric current, this method is based on P trap CMOS manufacture craft, after being ready for the N type substrate base of making alum gate CMOS, carrying out earlier N type ion on substrate injects, increase substrate surface concentration, and then carry out follow-up alum gate CMOS manufacturing process steps.
Further, the aforesaid method of improving the inefficacy of alum gate CMOS static electric current, wherein, described follow-up alum gate CMOS manufacture craft specifically comprises the steps:
(1) substrate after the injection of N type ion being carried out P trap gluing handles;
(2) substrate behind the gluing is carried out the exposure of P trap;
(3) substrate after the exposure being carried out the P trap develops;
(4) substrate after developing is carried out P trap etching;
(5) substrate after the etching being carried out P trap ion injects;
(6) processing of removing photoresist;
(7) utilize high temperature to push away trap, on substrate, form N trap and P trap;
(8) on the N trap, make the PMOS transistor, on the P trap, make nmos pass transistor.
Further, the aforesaid method that alum gate CMOS static electric current lost efficacy, the described N type ion injection employing P-ion of improving; The energy range that ion injects is 100Kev to 160Kev; The dosage range that ion injects is 2E11cm
-2To 4E11cm
-2
Further, the aforesaid method of improving the inefficacy of alum gate CMOS static electric current, in the step (5) of follow-up alum gate CMOS manufacture craft, P trap ion injects and adopts the B+ ion, and the energy range that ion injects is 100Kev to 160Kev; The dosage range that ion injects is 2E12cm
-2To 8E12cm
-2
Further, the aforesaid method of improving the inefficacy of alum gate CMOS static electric current, in the step (7) of follow-up alum gate CMOS manufacture craft, the temperature range that high temperature pushes away trap is 1000 ℃ to 1200 ℃, and pushing away the trap time is 10 hours to 15 hours.
Beneficial effect of the present invention is as follows: the present invention improves on the basis of traditional P trap CMOS manufacture craft, carries out the general notes technology of N type ion behind sheet under the N type substrate base earlier one time, to increase substrate surface concentration.The N type ion that injects on the substrate forms the N trap automatically in the trap technology that pushes away of high temperature furnace pipe on substrate, change the influence that the PMOS pipe is leaked electricity thereby alleviate substrate concentration, reaches and improves the purpose that the circuit quiescent current lost efficacy.
Description of drawings
Fig. 1 is the method flow diagram of the specific embodiment of the invention;
The CMOS transistor arrangement schematic diagram that Fig. 2 makes for traditional P trap CMOS manufacture craft;
The CMOS transistor arrangement schematic diagram of Fig. 3 for adopting the method for the invention to make;
Fig. 4 is quiescent current and the voltage relationship schematic diagram that does not carry out the PMOS pipe of N type ion injection;
Fig. 5 is quiescent current and the voltage relationship schematic diagram that carries out the PMOS pipe of N type ion injection.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in detail.
As shown in Figure 1, the method for improving the inefficacy of alum gate CMOS static electric current provided by the present invention is the improvement on P trap CMOS manufacture craft basis, specifically comprises the steps:
Step S01 prepares to be used to make the alum gate CMOS N type substrate base of (comprising NMOS and PMOS transistor), and substrate is a N type silicon wafer.
Step S02 carries out N type ion and injects on substrate, increase substrate concentration.N type ion injects and adopts the P-ion; The energy range that ion injects is 100Kev to 160Kev; The dosage range that ion injects is 2E11cm
-2To 4E11cm
-2
Step S03 carries out P trap gluing to the substrate after the injection of N type ion and handles.The centrifugal force that produces when utilizing substrate to rotate will drip in on-chip glue and throw away.Under the acting in conjunction of photoresist surface tension and substrate rotary centrifugal force, the final uniform photoresist film of generate thickness.Film thickness is controlled by the concentration of substrate rotating speed and glue, and required thickness is suitable, and even film layer adheres to good.
Step S04 carries out the exposure of P trap to the substrate behind the gluing.Lithography mask version is aimed at the substrate of coating photoresist, through lithography mask version irradiation substrate, the optical characteristics of the photoresist that receives illumination is changed with light source.To pay special attention to the selection and the aligning of exposure light source in the exposure.The wavelength of light source has very big influence to the photonasty of photoresist, and every kind of photoresist all has absworption peak and the absorption region of oneself, and it is only just relatively responsive to the light of wavelength in absorption region, and therefore the exposure light source of selecting must satisfy the photobehavior of photoresist.
Step S05 carries out the P trap to the substrate after the exposure and develops.Develop and to fall unwanted photoresist with developing solution dissolution exactly, with the figure transfer on the lithography mask version to photoresist.Positive glue only stays the part that is not subjected to illumination and forms figure after overexposure and developing; And negative glue only stays illumination and partly forms figure after overexposure and developing.The selection of developer solution and developing time is very important to the influence of development effect.The selection principle of developer solution is: that part of photoresist film that needs are removed dissolves soon, and solubility is big, and is minimum to that part of photoresist film solubility that needs keep.
Step S06 adopts wet etching, the P trap is shown the zone of opening carry out etching.Wet etching is that the etching material is immersed in the technology of corroding in the corrosive liquid; etching is exactly that part of the getting rid of that is not covered and protect by photoresist (through the overexposure and the back of developing) in the film of institute's deposit before the gluing, reaches the purpose of the figure transfer on the photoresist to its subsurface material.Because the present invention is based on P trap CMOS manufacture craft, therefore, etching technics mainly is the P well region that makes nmos pass transistor by lithography.
Step S07 carries out P trap ion to the substrate after the etching and injects.P trap ion injects and adopts the B+ ion, and the energy range that ion injects is 100Kev to 160Kev; The dosage range that ion injects is 2E12cm
-2To 8E12cm
-2
Step S08, the processing of removing photoresist.Photoresist does not need the diaphragm of etch areas except be used as the figure transfer media from the lithography mask version to the wafer in photoetching process when also being used as etching.After etching was finished, photoresist was die on, and its thorough removal need be finished the operation of this process and removed photoresist exactly.In addition, residual all ingredients also will be disposed in the etching process.The method of removing photoresist commonly used has that solvent removes photoresist, three kinds of the removing of photoresist by oxidation and the removing of photoresist by plasma.
Step S09 utilizes high temperature to push away trap, forms N trap and P trap on substrate.Push away trap is meant that the utilization pyroprocess makes impurity distribute and spread in silicon chip technology, concrete technology is carried out in high temperature furnace pipe, and high temperature pushes away the temperature of trap more than 1000 ℃, general desirable 1000 ℃ to 1200 ℃, push away the trap time above 10 hours, general desirable 10 hours to 15 hours.After pushing away trap and finishing, N trap and P trap have been formed on the substrate automatically.
Step S 10, make the PMOS transistor on the N trap, make nmos pass transistor on the P trap.The technical process of this step and traditional CMOS manufacture craft are identical, have comprised source electrode, the drain electrode of nmos pass transistor, the making of grid, and the making of the transistorized source electrode of PMOS, drain electrode, grid.
The CMOS transistor arrangement that the method for the invention is made as shown in Figure 3, be similar to the CMOS transistor that two trap CMOS manufacture crafts obtain, different is the CMOS transistor that obtains with conventional P trap CMOS manufacture craft shown in Figure 2, formed N trap and P trap on N type substrate base respectively, the PMOS pipe is produced on the N trap.The formation of N trap has increased the surface concentration of N type substrate, changes the influence that the PMOS pipe is leaked electricity thereby alleviated substrate concentration.
In traditional handicraft, do not carry out the quiescent current of the PMOS pipe that N type ion injects and voltage relationship as shown in Figure 4, from then on the IV curve of tested static electric current as can be seen, when not adopting N type ion implantation technology, during the 5V test, its quiescent current has reached 14 microamperes, quiescent current is big, can not satisfy the requirement that electric current uses fully.
The quiescent current of the PMOS pipe that N type ion injects and voltage relationship have been carried out among the present invention as shown in Figure 5, from then on the IV curve of tested static electric current as can be seen, after having adopted N type ion implantation technology, owing on N type substrate base, formed the N trap, increased the surface concentration of N type substrate, during the 5V test, its quiescent current is 220 to receive peace, with adopting N type ion implantation technology the gap of two orders of magnitude is arranged before, make quiescent current obtain very big improvement, satisfy the instructions for use of electric current fully.
The above only is one embodiment of the present of invention, and in order to restriction the present invention, these explanations and embodiment only consider as an example that they all belong to by within the indicated protection scope of the present invention and spirit of claims.
Claims (10)
1. one kind is improved the method that alum gate CMOS static electric current lost efficacy, this method is based on P trap CMOS manufacture craft, it is characterized in that: after being ready for the N type substrate base of making alum gate CMOS, carrying out earlier N type ion on substrate injects, increase substrate surface concentration, and then carry out follow-up alum gate CMOS manufacturing process steps.
2. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 1, it is characterized in that: described follow-up alum gate CMOS manufacture craft specifically comprises the steps:
(1) substrate after the injection of N type ion being carried out P trap gluing handles;
(2) substrate behind the gluing is carried out the exposure of P trap;
(3) substrate after the exposure being carried out the P trap develops;
(4) substrate after developing is carried out P trap etching;
(5) substrate after the etching being carried out P trap ion injects;
(6) processing of removing photoresist;
(7) utilize high temperature to push away trap, on substrate, form N trap and P trap;
(8) on the N trap, make the PMOS transistor, on the P trap, make nmos pass transistor.
3. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 1 or 2 is characterized in that: described N type ion injects and adopts the P-ion.
4. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 3 is characterized in that: the energy range that described N type ion injects is 100Kev to 160Kev.
5. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 4 is characterized in that: the dosage range that described N type ion injects is 2E11cm
-2To 4E11cm
-2
6. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 2 is characterized in that: in the step (5) of follow-up alum gate CMOS manufacture craft, P trap ion injects and adopts the B+ ion.
7. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 6 is characterized in that: in the step (5) of follow-up alum gate CMOS manufacture craft, the energy range that P trap ion injects is 100Kev to 160Kev.
8. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 7 is characterized in that: in the step (5) of follow-up alum gate CMOS manufacture craft, the dosage range that P trap ion injects is 2E12cm
-2To 8E12cm
-2
9. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 2, it is characterized in that: in the step (7) of follow-up alum gate CMOS manufacture craft, the temperature range that high temperature pushes away trap is 1000 ℃ to 1200 ℃.
10. the method for improving the inefficacy of alum gate CMOS static electric current as claimed in claim 9, it is characterized in that: in the step (7) of follow-up alum gate CMOS manufacture craft, it is 10 hours to 15 hours that high temperature pushes away the trap time.
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| CN2009102440518A CN102110649A (en) | 2009-12-28 | 2009-12-28 | Method for correcting failures of quiescent current in aluminum gate CMOS |
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| CN2009102440518A CN102110649A (en) | 2009-12-28 | 2009-12-28 | Method for correcting failures of quiescent current in aluminum gate CMOS |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681460A (en) * | 2013-11-28 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Testing method and testing structure for ion injection and semiconductor device |
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| CN1130442A (en) * | 1994-03-28 | 1996-09-04 | 精工电子工业株式会社 | Semiconductor device for detecting light and radiation and method of manufacturing the device |
| JP2006032543A (en) * | 2004-07-14 | 2006-02-02 | Seiko Instruments Inc | Semiconductor integrated circuit device |
| CN1992224A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of manufacturing complementary metal oxide semiconductor image sensor |
| JP2008182004A (en) * | 2007-01-24 | 2008-08-07 | Renesas Technology Corp | Semiconductor integrated circuit |
| CN101443916A (en) * | 2004-12-29 | 2009-05-27 | 半导体咨询有限责任公司 | Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells |
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2009
- 2009-12-28 CN CN2009102440518A patent/CN102110649A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1130442A (en) * | 1994-03-28 | 1996-09-04 | 精工电子工业株式会社 | Semiconductor device for detecting light and radiation and method of manufacturing the device |
| JP2006032543A (en) * | 2004-07-14 | 2006-02-02 | Seiko Instruments Inc | Semiconductor integrated circuit device |
| CN101443916A (en) * | 2004-12-29 | 2009-05-27 | 半导体咨询有限责任公司 | Apparatus and method for improving drive strength, leakage and stability of deep submicron MOS transistors and memory cells |
| CN1992224A (en) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | Method of manufacturing complementary metal oxide semiconductor image sensor |
| JP2008182004A (en) * | 2007-01-24 | 2008-08-07 | Renesas Technology Corp | Semiconductor integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681460A (en) * | 2013-11-28 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Testing method and testing structure for ion injection and semiconductor device |
| CN104681460B (en) * | 2013-11-28 | 2017-11-10 | 中芯国际集成电路制造(上海)有限公司 | A kind of ion injection test method, test structure and semiconductor devices |
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Application publication date: 20110629 |