CN105575895B - A kind of method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard - Google Patents
A kind of method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard Download PDFInfo
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- CN105575895B CN105575895B CN201610098374.0A CN201610098374A CN105575895B CN 105575895 B CN105575895 B CN 105575895B CN 201610098374 A CN201610098374 A CN 201610098374A CN 105575895 B CN105575895 B CN 105575895B
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 95
- 239000010703 silicon Substances 0.000 claims abstract description 95
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 94
- 239000010931 gold Substances 0.000 claims abstract description 40
- 229910052737 gold Inorganic materials 0.000 claims abstract description 40
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 39
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- SDDGNMXIOGQCCH-UHFFFAOYSA-N 3-fluoro-n,n-dimethylaniline Chemical compound CN(C)C1=CC=CC(F)=C1 SDDGNMXIOGQCCH-UHFFFAOYSA-N 0.000 claims abstract description 20
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910001930 tungsten oxide Inorganic materials 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052711 selenium Inorganic materials 0.000 claims abstract description 10
- 239000011669 selenium Substances 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 7
- 238000001035 drying Methods 0.000 claims description 21
- 239000003292 glue Substances 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 16
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 238000004528 spin coating Methods 0.000 claims description 12
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 11
- 229910001887 tin oxide Inorganic materials 0.000 claims description 11
- 238000011161 development Methods 0.000 claims description 9
- 238000000206 photolithography Methods 0.000 claims description 9
- 238000002207 thermal evaporation Methods 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 9
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 6
- 239000005864 Sulphur Substances 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000010792 warming Methods 0.000 claims description 6
- 238000007654 immersion Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000013461 design Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract 3
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, this method includes：Silica/silicon substrate of exposed pattern is made on silicon chip using photoetching, one layer of 10nm thickness tungsten oxide is deposited on underlay pattern after photoetching, then allow tungsten oxide to react to obtain tungsten selenide with selenium in CVD reacting furnaces, steep and obtain the tungsten selenide thin slice of specific pattern after acetone removes photoresist；Artificial gold thin slice is made above again with same method, tungsten selenide is formed hetero-junctions with artificial gold；Finally recycle the method for photoetching and gold evaporation to make gold electrode, field control band logical transistor array devices are can obtain after removing photoresist.The present invention is utilized respectively the method that p-type assembles altogether with n-type two-dimensional semiconductor material, a field control band logical transistor device for allowing current lead-through in the range of specific grid voltage is made in making heterostructure device on the silicon chip for have oxide layer, there is provided can not a scheme that control electric current opens or closes in the range of the grid voltage of region in a kind of solution past transistor device.
Description
Technical field
It is more particularly to a kind of to utilize two-dimensional semiconductor fabricating yard control band logical transistor array the present invention relates to field of electronic devices
The method of row device
Background technology
Field-effect transistor is a kind of solid semiconductor device, and variable power switch, base are often used as in electronic device applications
In the size of the voltage of input grid, the open and close of source-drain current can be controlled.In current silicon base CMOS device, typically
, under the control of gate field effect by realizing the doping to silicon substrate p-type and N-type toward incorporation boron or phosphorus etc. element in silicon
PMOS is turned under minus gate voltage, otherwise NMOS is turned under positive grid voltage.But there is presently no device can realize only in a certain section of grid voltage
In the range of allow current lead-through, in the function of this grid voltage scope extrinsic current cut-off, limit grid regulation and control electronic device and enter one
Step application.
It is sharp respectively using two-dimensional semiconductor fabricating yard control band logical transistor array devices, the method invention describes one kind
The method assembled altogether with p-type and n-type two-dimensional semiconductor material, making heterostructure device is made only on the silicon chip for have oxide layer
The field of current lead-through is allowed to control band logical transistor device in the range of specific grid voltage.
The content of the invention
The shortcomings that it is a primary object of the present invention to overcome prior art and deficiency, there is provided one kind utilizes two-dimensional semiconductor system
Make the method for field control band logical transistor array devices, this method is utilized respectively the side that p-type assembles altogether with n-type two-dimensional semiconductor material
Method, heterostructure device is made on the silicon chip for have oxide layer and is made only allows the field of current lead-through to control in the range of specific grid voltage
Band logical transistor device.
In order to achieve the above object, the present invention uses following technical scheme：
The invention provides a kind of method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, including with
Under several steps：
Step 1：Taking has the silicon chip of silica oxide layer on a piece of；
Step 2：One layer of photoresist of spin coating on silicon chip；
Step 3：The silicon chip for scribbling photoresist is placed in progress drying glue processing in thermal station；
Step 4：The silicon chip after drying glue is kept flat, and photolithography plate is gently pressed on silicon chip；Irradiate and carry out under exposure light source
Exposure-processed；
Step 5：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed do with secondary water at once afterwards
Only；
Step 6：One layer of 2-100nm thickness tungsten oxide is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument；
Step 7：Tungsten oxide is allowed to react to obtain tungsten selenide with selenium in CVD reacting furnaces, temperature is taken out after dropping to normal temperature；
Step 8：Silicon chip is soaked in acetone to remove photoresist and unnecessary tungsten selenide, makes to leave required shape on silicon chip
The array tungsten selenide thin slice of shape, takes out and dries up from acetone afterwards；
Step 9：Again one layer of photoresist of spin coating and drying glue processing is carried out on silicon chip；
Step 10：The silicon chip after drying glue is kept flat, is aligned under litho machine microscope, makes pattern and step 6 in photolithography plate
In tungsten oxide pattern part overlap, under exposure light source irradiation be exposed processing；
Step 11：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed do with secondary water at once afterwards
Only；
Step 12：One layer of 2-100nm thickness tin oxide is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument；
Step 13：Tin oxide is allowed to obtain artificial gold with reaction of Salmon-Saxl in CVD reacting furnaces, temperature is taken out after dropping to normal temperature；
Step 14：Silicon chip immersion in acetone to remove photoresist and unnecessary artificial gold, make to leave on silicon chip needed for
The tungsten selenide of shape-artificial gold array, takes out and dries up from acetone afterwards；
Step 15：Again one layer of photoresist of spin coating and drying glue processing is carried out on silicon chip；
Step 16：The silicon chip after drying glue is kept flat, is aligned under litho machine microscope, makes pattern and step 14 in photolithography plate
In tungsten selenide-artificial gold array pattern part overlap, under exposure light source irradiation be exposed processing；
Step 17：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed do with secondary water at once afterwards
Only；
Step 18：One layer of 5-50nm thickness gold electrode is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument；
Step 19：Silicon chip 1 is soaked in acetone to remove photoresist and unnecessary gold thin film, make to leave on silicon chip needed for
The tungsten selenide of shape-artificial gold array and the gold electrode communicated therewith, take out and dry up from acetone afterwards；Finally obtained selenizing
Tungsten-artificial gold band logical transistor array devices.
As preferable technical scheme, wherein silicon chip surface silicon dioxide thickness is 10-350nm.
As preferable technical scheme, the wherein rotating speed of spin coating photoresist is 2000-4000rpm, and drying glue treatment temperature is
100 DEG C, time 4min.
As preferable technical scheme, the time that wherein CVD stoves rise to design temperature from normal temperature is 10min, and is being set
At a temperature of constant temperature 5min, afterwards open bell it is naturally cooled to room temperature.
As preferable technical scheme, step 7 is specially：
Silicon chip is put into dual temperature area CVD tube furnaces, pipe front end warm area is put into selenium simple substance, and rear end warm area puts silicon chip, 5
Synchronous that rear end warm area is warming up to 650 DEG C from normal temperature under ml/min argon stream, front end temperature-raising region temperature raising makes selenium liter to 200 DEG C
China, reaction make the tungsten oxide thin slice on silicon chip change into tungsten selenide, and temperature is taken out after dropping to normal temperature.
As preferable technical scheme, step 13 is specially：
Silicon chip is put into dual temperature area CVD tube furnaces, pipe front end warm area is put into sulphur simple substance, and rear end warm area puts silicon chip, 5
Synchronous that rear end warm area is warming up to 650 DEG C from normal temperature under ml/min argon stream, front end temperature-raising region temperature raising makes sulphur liter to 120 DEG C
China, reaction make the tin oxide thin slice on silicon chip change into artificial gold, and temperature is taken out after dropping to normal temperature.
As preferable technical scheme, in the step 6, the thickness of tungsten oxide is 10nm.
As preferable technical scheme, in the step 12, the thickness of tin oxide is 10nm.
As preferable technical scheme, in the step 18, the thickness of gold electrode is 20nm.
The present invention compared with prior art, has the following advantages that and beneficial effect：
Invention describes a kind of method of fabricating yard control band logical transistor array devices, this method is utilized respectively p-type and n
The method that type two-dimensional semiconductor material assembles altogether, making heterostructure device is made only in specific gate on the silicon chip for have oxide layer
The field of current lead-through is allowed to control band logical transistor device in the range of pressure, there is provided one kind solves can not be only in transistor device in the past
The scheme that control electric current opens or closes in the range of the grid voltage of region.
Brief description of the drawings
Fig. 1 is the schematic diagram of control band logical transistor array devices in field of the present invention.
Fig. 2 is the transfer curve test result schematic diagram of control band logical transistor array devices in field of the present invention.
Drawing reference numeral explanation：1 --- tungsten selenide；2 --- gold electrode；3 --- the part that tungsten selenide overlaps with artificial gold；
4 --- silicon chip substrate；5 --- artificial gold.
Embodiment
With reference to embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are unlimited
In this.
Embodiment
As shown in figure 1, a kind of method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard of the present embodiment,
Specifically include following methods：
Step 1：Take the silicon chip (silicon chip substrate 4 i.e. shown in Fig. 1) for having silica oxide layer on a piece of；
Step 2：One layer of photoresist of spin coating on silicon chip；
Step 3：The silicon chip for scribbling photoresist is placed in progress drying glue processing in thermal station；
Step 4：The silicon chip after drying glue is kept flat, and photolithography plate is gently pressed on silicon chip；Irradiate and carry out under exposure light source
Exposure-processed；
Step 5：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed do with secondary water at once afterwards
Only；
Step 6：One layer of 2-100nm thickness tungsten oxide is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument, this
The thickness of tungsten oxide is 10nm in embodiment；
Step 7：Silicon chip is put into dual temperature area CVD tube furnaces, pipe front end warm area is put into selenium simple substance, and rear end warm area puts silicon
Piece, under 5 ml/min argon streams, synchronous that rear end warm area is warming up to 650 DEG C from normal temperature, front end temperature-raising region temperature raising is to 200 DEG C
Selenium is set to distil, reaction makes the tungsten oxide thin slice on silicon chip change into tungsten selenide 1, and temperature is taken out after dropping to normal temperature；
Step 8：Silicon chip is soaked in acetone to remove photoresist and unnecessary tungsten selenide, makes to leave required shape on silicon chip
The array tungsten selenide thin slice of shape, takes out and dries up from acetone afterwards；
Step 9：Again one layer of photoresist of spin coating and drying glue processing is carried out on silicon chip；
Step 10：The silicon chip after drying glue is kept flat, is aligned under litho machine microscope, makes pattern and step 6 in photolithography plate
In tungsten oxide pattern part overlap, under exposure light source irradiation be exposed processing；
Step 11：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed do with secondary water at once afterwards
Only；
Step 12：One layer of 2-100nm thickness tin oxide is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument, this
The thickness of tin oxide is 10nm in embodiment；
Step 13：Silicon chip is put into dual temperature area CVD tube furnaces, pipe front end warm area is put into sulphur simple substance, and rear end warm area is put
Silicon chip, synchronous that rear end warm area is warming up to 650 DEG C from normal temperature under 5 ml/min argon streams, front end temperature-raising region temperature raising to 120
DEG C sulphur is set to distil, reaction makes the tin oxide thin slice on silicon chip change into artificial gold 5, and temperature is taken out after dropping to normal temperature；
Step 14：Silicon chip immersion in acetone to remove photoresist and unnecessary artificial gold, make to leave on silicon chip needed for
The tungsten selenide of shape-artificial gold array, takes out and dries up from acetone afterwards；
Step 15：Again one layer of photoresist of spin coating and drying glue processing is carried out on silicon chip；
Step 16：The silicon chip after drying glue is kept flat, is aligned under litho machine microscope, makes pattern and step 14 in photolithography plate
In tungsten selenide-artificial gold array pattern part it is overlapping (part 3 that tungsten selenide overlaps with artificial gold in Fig. 1), in exposure light source
Lower irradiation is exposed processing；
Step 17：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed do with secondary water at once afterwards
Only；
Step 18：One layer of 5-50nm thickness gold electrode 2 is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument, this
The thickness of gold electrode is 20nm in embodiment；
Step 19：Silicon chip immersion in acetone to remove photoresist and unnecessary gold thin film, make to leave on silicon chip needed for
The tungsten selenide of shape-artificial gold array and the gold electrode 2 communicated therewith, take out and dry up from acetone afterwards；Finally obtained selenium
Change tungsten-artificial gold band logical transistor array devices.
Wherein, silicon chip surface silicon dioxide thickness is 10-350nm.
The rotating speed of spin coating photoresist is 2000-4000rpm in above-mentioned steps 2.
Drying glue treatment temperature is 100 DEG C in above-mentioned steps 3, time 4min.
As shown in Fig. 2 the transfer curve test result of field control band logical transistor array devices, only special in this device
All can be closed mode in this scope extrinsic current with conducting electric current in the range of fixed grid pressure.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (9)
- A kind of 1. method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is characterised in that including following Several steps：Step 1：Taking has the silicon chip of silica oxide layer on a piece of；Step 2：One layer of photoresist of spin coating on silicon chip；Step 3：The silicon chip for scribbling photoresist is placed in progress drying glue processing in thermal station；Step 4：The silicon chip after drying glue is kept flat, and photolithography plate is gently pressed on silicon chip；Irradiate and be exposed under exposure light source Processing；Step 5：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed well at once with secondary water afterwards；Step 6：One layer of 2-100nm thickness tungsten oxide is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument；Step 7：Tungsten oxide is allowed to react to obtain tungsten selenide with selenium in CVD reacting furnaces, temperature is taken out after dropping to normal temperature；Step 8：Silicon chip immersion to remove photoresist and unnecessary tungsten selenide, makes shape needed for being left on silicon chip in acetone Array tungsten selenide thin slice, takes out and dries up from acetone afterwards；Step 9：Again one layer of photoresist of spin coating and drying glue processing is carried out on silicon chip；Step 10：The silicon chip after drying glue is kept flat, is aligned under litho machine microscope, is made in pattern and the step 6 in photolithography plate Tungsten oxide pattern part overlaps, and is irradiated under exposure light source and is exposed processing；Step 11：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed well at once with secondary water afterwards；Step 12：One layer of 2-100nm thickness tin oxide is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument；Step 13：Tin oxide is allowed to obtain artificial gold with reaction of Salmon-Saxl in CVD reacting furnaces, temperature is taken out after dropping to normal temperature；Step 14：Silicon chip is soaked in acetone to remove photoresist and unnecessary artificial gold, makes to leave required shape on silicon chip Tungsten selenide-artificial gold array, take out and dry up from acetone afterwards；Step 15：Again one layer of photoresist of spin coating and drying glue processing is carried out on silicon chip；Step 16：The silicon chip after drying glue is kept flat, is aligned under litho machine microscope, is made in pattern and the step 14 in photolithography plate Tungsten selenide-artificial gold array pattern part overlaps, and is irradiated under exposure light source and is exposed processing；Step 17：Silicon chip after exposure, which is immersed in developer solution, carries out development treatment, is rinsed well at once with secondary water afterwards；Step 18：One layer of 5-50nm thickness gold electrode is deposited on the silicon chip for the figure that develops using vacuum thermal evaporation instrument；Step 19：Silicon chip 1 is soaked in acetone to remove photoresist and unnecessary gold thin film, makes to leave required shape on silicon chip Tungsten selenide-artificial gold array and the gold electrode that communicates therewith, take out and dry up from acetone afterwards；Final obtained tungsten selenide- Artificial gold band logical transistor array devices.
- 2. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is that wherein silicon chip surface silicon dioxide thickness is 10-350nm.
- 3. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is that wherein the rotating speed of spin coating photoresist is 2000-4000rpm, and drying glue treatment temperature is 100 DEG C, time 4min.
- 4. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is, the time that wherein CVD stoves rise to design temperature from normal temperature is 10min, and constant temperature 5min at a set temperature, is beaten afterwards Blow-on lid makes it naturally cool to room temperature.
- 5. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is that step 7 is specially：Silicon chip is put into dual temperature area CVD tube furnaces, pipe front end warm area is put into selenium simple substance, and rear end warm area puts silicon chip, in 5 millis Synchronous that rear end warm area is warming up to 650 DEG C from normal temperature under liter/min argon stream, front end temperature-raising region temperature raising makes selenium liter to 200 DEG C China, reaction make the tungsten oxide thin slice on silicon chip change into tungsten selenide, and temperature is taken out after dropping to normal temperature.
- 6. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is that step 13 is specially：Silicon chip is put into dual temperature area CVD tube furnaces, pipe front end warm area is put into sulphur simple substance, and rear end warm area puts silicon chip, in 5 millis Synchronous that rear end warm area is warming up to 650 DEG C from normal temperature under liter/min argon stream, front end temperature-raising region temperature raising makes sulphur liter to 120 DEG C China, reaction make the tin oxide thin slice on silicon chip change into artificial gold, and temperature is taken out after dropping to normal temperature.
- 7. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is, in the step 6, the thickness of tungsten oxide is 10nm.
- 8. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is, in the step 12, the thickness of tin oxide is 10nm.
- 9. the method according to claim 1 that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard, it is special Sign is, in the step 18, the thickness of gold electrode is 20nm.
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| CN102623382A (en) * | 2012-03-31 | 2012-08-01 | 上海华力微电子有限公司 | Silicon on insulator (SOI)-based manufacturing method for three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor |
| CN103956320A (en) * | 2014-04-16 | 2014-07-30 | 苏州大学 | Method for transferring electrode pattern on arbitrary substrate and constructing electronic device |
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| US7358104B2 (en) * | 2002-10-08 | 2008-04-15 | Samsung Electornics Co., Ltd. | Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion |
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| CN102569516A (en) * | 2012-01-10 | 2012-07-11 | 合肥工业大学 | Method for preparing p-CdS nano wire and p-CdS/n-Si nano p-n node through manganese trioxide (MoO3) surface doping |
| CN102623382A (en) * | 2012-03-31 | 2012-08-01 | 上海华力微电子有限公司 | Silicon on insulator (SOI)-based manufacturing method for three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor |
| CN103956320A (en) * | 2014-04-16 | 2014-07-30 | 苏州大学 | Method for transferring electrode pattern on arbitrary substrate and constructing electronic device |
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