CN102623382A - Silicon on insulator (SOI)-based manufacturing method for three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor - Google Patents
Silicon on insulator (SOI)-based manufacturing method for three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor Download PDFInfo
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Abstract
The invention discloses a silicon on insulator (SOI)-based manufacturing method for a three-dimensional array type silicon nano-wire metal oxide semiconductor field effect transistor (Si-NWFET). The method comprises the following steps of: alternately growing silicon layers and silicon germanium layers on an SOI substrate, forming three-dimensional array type fin-shaped active regions, and forming silicon nano-wires in the fin-shaped active regions, wherein the silicon nano-wires are vertically stacked to form a three-dimensional array; forming gate oxide layers on the surfaces of the silicon nano-wires, the SOI substrate, a source region and a drain region; forming a gate on the SOI substrate between the source region and the drain region; and forming an isolation dielectric layer between the source and drain regions and the gate. By an insulator layer in the SOI substrate, an isolation effect between the gate and the SOI substrate is effectively improved; a process for forming the gate oxide layers on the silicon nano-wires is independently performed, so that the conventional gate oxide layer can be adopted; and in addition, an Si-NWFET is designed by adopting a three-dimensional array vertically-stacked type silicon nano-wire structure, so that the number of the nano-wires is increased, and the integration level and current driving capability of a device are improved.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI.
Background technology
Through dwindle transistorized size improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in the microelectronics industry development always.Current; The physical gate of field-effect transistor is long near 20nm; Gate medium also only has the thickness of several oxygen atomic layers; Improve performance through the size of dwindling conventional field effect transistor and faced some difficulties, this mainly is to have destroyed transistorized switch performance because of short-channel effect under the small size and grid leakage current.
Nano-wire field effect transistor (NWFET, Nano-Wire MOSFET) is expected to solve the problem of short-channel effect and grid leakage current.On the one hand; Channel thickness among the NWFET and width are all less, make grid more approach the various piece of raceway groove, help enhance transistor grid modulation capability; And most of transistors all adopt and enclose the grid structure; Grid is modulated raceway groove from a plurality of directions, has further strengthened the modulation capability of grid, improves the subthreshold value characteristic.Therefore, NWFET can suppress short-channel effect well, makes transistor size be able to further dwindle.On the other hand, NWFET utilizes the rill road of self and encloses the grid structure and improve the grid modulation forces and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced impurity discrete distribution and Coulomb scattering in the raceway groove.For the 1-dimention nano wire channel, because quantum limitation effect, charge carrier so carrier transport receives surface scattering and channel laterally influence little, can obtain higher mobility away from surface distributed in the raceway groove.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Because Si material and technology are occupied dominant position in semi-conductor industry, compare the easier and current process compatible of the making of silicon nanowires field-effect transistor (Si-NWFET) with other materials.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.For the making of Si nano wire, top-down making mainly utilizes photoetching and etching technics, and making from bottom to top is mainly based on the gas-liquid-solid growth mechanism of metal catalytic, in the growth course with catalyst granules as nucleating point.At present, the silicon nanowires of process route preparation from bottom to top not too is fit to the preparation of Si-NWFET owing to its randomness, and the Si-NW in the therefore present silicon nanowires field-effect transistor mainly is through top-down process route preparation.
At present; Field-effect transistor (MOSFET) its preparation process research based on single silicon nanowires is relatively more popular; To be 200710098812.4 disclosure of the Invention like application number a kind of based on the process that approach from top to bottom realizes the bulk silicon nano line structure of passing through of body silicon, effectively suppressed the self-heating effect of device.And a kind of MOSFET preparation method based on silicon nanowires is disclosed in the paper " Fabrication and Characterization of Gate-All-Around Silicon Nanowires onBulk Silicon "; But along with dwindling of silicon nanowires sectional area; The current driving ability of device can receive the restriction of nano wire sectional area; Make the application of Si-NWFET in simulation or radio circuit be restricted; Therefore, the someone begins one's study and adopts many nano wires as transporting raceway groove, to address this problem.
People such as W.W.Fang are at IEEE ELECTRON DEVICE LETTERS; VOL.28; NO.3 has proposed a kind of vertical method for preparing silicon nanowires in the paper of delivering on the MARCH 2007 " Vertically Stacked SiGe Nanowire Array ChannelCMOS Transistors ", makes the silicon nanowires FET device at vertical integrated many silicon nanowires; Thereby make the current driving ability of device increase exponentially, integration density is unaffected simultaneously.Not only can keep the advantage of planar structure field-effect transistor (FET) but also strengthened the grid modulation capability.Its process is to go up alternately growth (Ge/Si Ge)/Si/ (Ge/SiGe)/Si layer at SOI (Silicon on Insulator); And define fin-shaped (Fin) structure above that; Carry out 750 ℃ of dry-oxygen oxidations then; Because the SiGe layer has faster oxidation rate so that SiGe layer oxidized fully than the Si layer, Ge gets into contiguous Si laminar surface and forms the SiGe alloy in the oxidizing process, erodes and obtains three-dimensional pile up, Si nano wire that the surface is wrapped with the SiGe alloy behind the oxidized fully SiGe layer.Carry out thermal oxidation then, form Si on silicon nanowires (SiNW) surface
1-XGe
XO
2As grid oxic horizon, unformed silicon of deposit or polysilicon form grid through photoetching and etching at last again.This method can realize vertical stack type silicon nanowires field-effect transistor structure, but has a shortcoming: in SiGe layer oxidizing process, Ge can be concentrated to the surface of Si layer, removes SiO
2After, be wrapped with the SiGe alloy after one deck concentrates at surface of silicon nanowires.Because GeO
2Water-soluble, it makes subsequent technique face huge inconvenience, in addition, and GeO
2Dielectric constant than SiO
2Little, GeO
2Bigger with the interfacial state of Si, be not suitable for gate oxide as field-effect transistor (FET).
Summary of the invention
The present invention provides a kind of three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI; Can make in the device isolation effect of grid and substrate better; Increase the driving force that electric current drives; Effectively improve the device integrated level, and realize the conventional grid oxic horizon structure of silicon nanowires field-effect transistor.
For solving the problems of the technologies described above, the present invention provides a kind of three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI, comprising:
SOI is provided substrate, and said SOI substrate is followed successively by silicon lining, insulator layer and top layer silicon from bottom to top;
Said SOI substrate surface is handled, said SOI substrate top layer is converted into initial germanium silicon layer;
On the SOI substrate, alternately form silicon layer and follow-up germanium silicon layer, said initial germanium silicon layer and said follow-up germanium silicon layer constitute the germanium silicon layer jointly;
To said germanium silicon layer and silicon layer etching processing, form three-dimensional array type fin-shaped active area, remaining areas is as source-drain area;
In said three-dimensional array type fin-shaped active area, form silicon nanowires, said silicon nanowires is a cubical array vertical stack formula;
Form grid oxic horizon on said silicon nanowires, SOI substrate and source-drain area surface;
On the SOI substrate between the said source-drain area, form grid;
Between said source-drain area and said grid, form the spacer medium layer.
Preferable, said SOI substrate surface to be handled, the concrete operations that said SOI substrate top layer is converted into initial germanium silicon layer are:
Deposit a germanium layer at said SOI substrate surface;
To said germanium layer oxidation processes, the concentrated silicon with said SOI substrate top layer of germanium oxidation forms follow-up germanium silicon layer in the said germanium layer, and said follow-up germanium silicon surface is SiO
2Layer;
Wet method is removed said SiO
2Layer.
Preferable, said silicon layer is at least one deck, and said germanium silicon layer manys one deck than said silicon layer.
Preferable, after said germanium silicon layer and silicon layer etching processing, ion is carried out in the zone between the said source-drain area inject.
Preferable, form on the SOI substrate between the said source-drain area after the grid, said source-drain area is carried out ion inject.
Preferable, said silicon nanowires diameter is between 1 nanometer～1 micron.
Preferable, the cross sectional shape of said silicon nanowires is circular, horizontal track shape or vertical track shape.
Preferable, before forming grid oxic horizon on said silicon nanowires, SOI substrate and the source-drain area, also comprise:
Said silicon nanowires is carried out thermal oxidation;
Etch away the silicon dioxide that said thermal oxidation forms.
Preferable, the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K medium.
Preferable, said high K medium is HfO
2, Al
2O
3, ZrO
2In a kind of or its combination in any.
Preferable, the material of said grid is a polysilicon, amorphous silicon, the combination in any of metal or said polysilicon, unformed silicon and metal.
Preferable, said spacer medium is a silicon dioxide.
Preferable, said etching adopts time normal pressure chemical gas phase etching method
Preferable, said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, and wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
Compared with prior art, the structure based on the three-dimensional array type silicon nanowires field-effect transistor of SOI has following characteristics:
1, based on the SOI substrate, because the existence of insulator layer in the SOI substrate has effectively increased the isolation effect between grid and the SOI substrate;
2, form grid earlier, form the spacer medium layer again, be the back spacer processes, and need not to carry out side wall technology;
3, on silicon nanowires, forming the gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
4, form grid at the fin-shaped active area, the profile of control grid, thus make active area and gate upper surface at same horizontal plane, be beneficial to follow-up contact hole technology;
5, employing comes design of Si nano-wire field effect transistor (Si-NWFET) structure based on the three-dimensional array type silicon nanowire structure of SOI; Nano wire becomes three-dimensional array type to arrange; The nanometer number of lines increases, and has effectively improved the integrated level of device and has strengthened the current driving ability of device.
Description of drawings
Fig. 1 for substrate X-X ' in the present invention's one specific embodiment to generalized section;
Fig. 2 for deposition germanium layer in the present invention's one specific embodiment after X-X ' to generalized section;
Fig. 3 for germanium layer oxidation in the present invention's one specific embodiment after X-X ' to generalized section;
Fig. 4 for X-X ' after removing silicon dioxide in the present invention's one specific embodiment to generalized section;
Fig. 5 for alternating deposit silicon layer in the present invention's one specific embodiment and germanium silicon layer after X-X ' to generalized section;
Fig. 6 in the present invention's one specific embodiment during the channel ion injection technology X-X ' to generalized section;
Fig. 7 is for forming Y-Y ' behind the fin-shaped active area in the present invention's one specific embodiment to generalized section;
Fig. 8 A～8B be respectively X-X ' that etching in the present invention's one specific embodiment removes device behind the germanium silicon layer to and Y-Y ' to generalized section;
Fig. 8 C is for forming the schematic perspective view of device behind the silicon nanowires in the present invention's one specific embodiment;
Fig. 9 is silicon nanowires cross sectional shape sketch map in the present invention's one specific embodiment;
Figure 10 A～10B for gate oxidation process in the present invention's one specific embodiment after the X-X ' of device to generalized section and stereogram;
Figure 11 A～11B be respectively in the present invention's one specific embodiment grid material inject back device X-X ' to and Y-Y ' to generalized section;
Figure 12 A～12B be respectively in the present invention's one specific embodiment remove behind the unnecessary grid material device X-X ' to and Y-Y ' to generalized section;
Figure 13 A～13B be respectively in the present invention's one specific embodiment form behind the grid device X-X ' to and Y-Y ' to generalized section;
Figure 13 C～13D is respectively in the present invention's one specific embodiment and forms device fin-shaped active area and device perspective view behind the grid;
Figure 14 A～14B be respectively in the present invention's one specific embodiment the back isolation technology fill behind the spacer medium device X-X ' to and Y-Y ' to generalized section;
Figure 15 A～15B be respectively in the present invention's one specific embodiment remove behind the unnecessary spacer medium device X-X ' to and Y-Y ' to generalized section;
Device X-X ' was to generalized section when Figure 16 leaked doping for source in the present invention's one specific embodiment;
Figure 17 A～17B for accomplish in the present invention's one specific embodiment after the metal interconnected technology device X-X ' to and Y-Y ' to generalized section;
Figure 18 is silicon nanowires field-effect transistor perspective view in the present invention's one specific embodiment.
Figure 19 is silicon nanowires field-effect transistor schematic top plan view in the present invention's one specific embodiment.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
At first; Shown in figure 19, for clearer description present embodiment, the length direction of the silicon nanowires 131 of definition fin-shaped active area 201 or follow-up formation be X-X ' to; X-X ' is to running through grid 202, source electrode 203 and drain 204, perpendicular to X-X ' to be Y-Y ' to.The preparation method based on the three-dimensional array type Si-NWFET of SOI below in conjunction with the detailed description one embodiment of the invention of Fig. 1 to 19 specifically comprises:
Please with reference to Fig. 1, SOI is provided substrate, the SOI bottom is the silicon lining 11 that is used to provide mechanical support; Be insulator layer on the silicon lining 11, the present invention adopts oxygen buried layer 12 (BOX) as insulator layer, oxygen buried layer 12 upper stratas; Just the top layer of SOI is a silicon layer 13, and wherein the silicon in the silicon layer 13 is monocrystalline silicon;
Said SOI substrate surface is handled, said SOI substrate top layer is converted into initial germanium silicon layer 15 '; Specifically comprise: at first,, form a germanium layer 14 (germanium layer can be replaced by the germanium silicon layer) at the SOI substrate surface please with reference to Fig. 2; Then; Please with reference to Fig. 3, the SOI substrate surface is carried out oxidation processes, germanium layer 14 is seeped in the silicon layer 13 because oxidation concentrates; Form initial germanium silicon layer 15 ', the silicon of initial germanium silicon layer 15 ' upper surface is oxidized into silicon dioxide layer 16; Then, please with reference to Fig. 4, adopt wet etching to remove the silicon dioxide layer 16 of substrate surface, at this moment, the top layer of SOI substrate is converted into initial germanium silicon layer 15 ' by silicon layer 13.
Please with reference to Fig. 5, on the SOI substrate, alternately form silicon layer 13 and follow-up germanium silicon layer 15 ", at first go up epitaxial growth silicon layer 13; the follow-up germanium silicon layer 15 of regrowth at initial silicon germanium layer 15 ' ", be convenient the description, with initial germanium silicon layer 15 ' and follow-up germanium silicon layer 15 " be referred to as germanium silicon layer 15; and by that analogy; wherein the number of silicon layer 13 is at least one deck, germanium silicon layer 15 is than silicon layer one deck more than 13, and the present invention is an example with three layers silicon layer 13.
Please with reference to Fig. 6; Channel region to the SOI substrate carries out the ion injection; Be specially: at first, on germanium silicon layer 15, carry out photoetching process, photoresist 20 covers the zone that is used for follow-up formation source electrode 203 (please with reference to Figure 19) and drain electrode 204 (please with reference to Figure 19); Then carry out ion and inject, remove the photoresist 20 on source electrode 203 and drain electrode 204 surfaces after ion injects and accomplishes.Need to prove that this step is an optional step, device electrically requires can omit under the permission situation.
Please with reference to Fig. 7, to said germanium silicon layer 15 and silicon layer 13 etching processing, form fin-shaped active area 201 (please with reference to Figure 19), remaining areas is as source-drain area, i.e. source electrode 203 and drain electrode 204 zones;
Wherein, Said fin-shaped active area 201 is a cubical array vertical stack formula; Therefore can adopt optical lithography (Photolithography) or electron beam lithography (electron beam lithography); Etching runs through fin-shaped active area 201 unnecessary germanium silicon layer 15 and silicon layer 13 on every side, until oxygen buried layer 12 surfaces that expose substrate
Please with reference to Fig. 8 A～8C, in said fin-shaped active area, form silicon nanowires 131, said silicon nanowires 131 also is a cubical array vertical stack formula; Be specially, selective etch is removed the germanium silicon layer 15 in the fin-shaped active area 201, and is optional, utilizes time normal pressure chemical gas phase etching method to carry out selective etch, can adopt the H under 600～800 degrees centigrade
2With the HCL mist, wherein the dividing potential drop of HCL is greater than 300Torr, till the germanium silicon layer 15 of selective etch step in fin-shaped active area 201 all removed;
Oxidation is carried out on fin-shaped active area 201, SOI substrate and source-drain area surface, the controlled oxidation time, utilized wet processing to remove the SiO on fin-shaped active area 201 and SOI substrate and source and drain areas surface
2Thereby, form silicon nanowires 131 (please with reference to Fig. 8 C).Further, if described thermal oxidation is furnace oxidation (FurnaceOxidation), then the oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), then the oxidization time scope is 1 second to 30 minutes.Remove the silicon dioxide that above-mentioned steps forms through wet processing on silicon nanowires 131 and body silicon 1 and source-drain area surface then.Silicon nanowires 131 diameters that form at last are between 1 nanometer～1 micron.Because the thickness and fin-shaped active area 201 lateral dimensions of silicon layer 13 vary in size; The cross sectional shape of silicon nanowires 131 is also different; Please with reference to Fig. 9, the cross sectional shape of silicon nanowires 131 comprises circle 301, laterally track shape 302 and vertically track shape 303; Preferred cross-sections of the present invention is shaped as circular 301 silicon nanowires 131; Through more advanced figure transfer technology, can more accurately control fin-shaped active area (Fin) physical dimension, thereby more help the Shape optimization of silicon nanowires 131 and the diameter of accurately controlling silicon nanowires 131.。
Please with reference to Figure 10 A～10B; Form grid oxic horizon 17 on said silicon nanowires 131, substrate and source-drain area surface; What wherein grid oxic horizon 17 adopted is conventional grid oxic horizon material, so the material of grid oxic horizon 17 can be the SiO of furnace oxidation, rapid thermal oxidation or ald formation
2Or SiON, also can be for adopting the high K medium layer (high dielectric radio medium) of technique for atomic layer deposition (ALD) deposition, SiON need be under the nitrogen atmosphere; Because the existence of the oxygen buried layer 12 among grid oxic horizon 17 and the SOI makes subsequent gate 202 better with the isolation effect of substrate.
Please, between source-drain area, form grid 202 on the substrate of (in the fin-shaped active area 201) with reference to Figure 11 A～13D; Be specially: at first, please with reference to Figure 11 A～11B, in fin-shaped active area 201, source electrode 203, drain electrode 204 region surface deposition of gate material 18; Grid material 18 can be polysilicon; Amorphous silicon, metal or its combination in any, wherein metal is preferably the metallic compound of aluminium or titanium or tantalum.Then,, adopt cmp to remove fin-shaped active area 201, source electrode 203 and the unnecessary grid material 18 of 204 region surface that drain, make grid material 18 and source-drain area upper surface at same horizontal plane please with reference to Figure 12 A～12B; Then, please with reference to 13A～13D, form grid 202 through photoetching and selective etch technology; Photoetching can be adopted hard mask or photo-resistive mask; The profile of control grid 202, thus make source-drain area and grid 202 upper surfaces at same horizontal plane, be beneficial to follow-up contact hole technology.
Please, between said source-drain area and said grid, form spacer medium 19 with reference to Figure 14 A～15B; Comprise: please with reference to Figure 14 A～14B, substrate, grid 202, source electrode 203 and the 204 surface deposition spacer mediums 19 that drain in the fin-shaped active area, the spacer medium 19 among the present invention is SiO
2Then, please with reference to Figure 15 A～15B, utilize cmp to remove grid 202, source electrode 203 and the unnecessary spacer medium 19 of 204 region surface that drain.The present invention adopts and forms grid 202 earlier, forms spacer medium 19 again, is the back spacer processes, and need not to carry out side wall technology.
Then, please with reference to Figure 16, source and drain areas is carried out ion inject, carry out photoetching process earlier, the 20 covering source electrodes 203 and 204 zones that drain are with exterior portions with photoresist, and removal photoresist 20 and source-drain electrode were annealed after ion injected and accomplishes.Need to prove that this step can be carried out before fin-shaped active area 201 graphical definition, also can carry out afterwards through cmp (CMP) at grid material 18.
At last; Please with reference to Figure 17 A～18; Carry out autoregistration silicon or germanium silicon metal alloy (Salicidation) technology; And draw each port of CMOSFET through back road metal interconnected technology, and said port comprises drain electrode port 22, gate port 23 and source electrode port 24, source electrode 203, grid 202 and 204 region surface that drain are coated with silicon or germanium silicon metal alloy 21.
In sum, compared with prior art, the three-dimensional array type silicon nanowires field-effect transistor structure based on SOI of the present invention has the following advantages:
1, based on the SOI substrate, because the existence of insulator layer (for example being oxygen buried layer) in the SOI substrate has effectively increased the isolation effect between grid and the SOI substrate;
2, form grid earlier, form the spacer medium layer again, be the back spacer processes, and need not to carry out side wall technology;
3, on silicon nanowires, forming the gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
4, form grid at the fin-shaped active area, the profile of control grid, thus make active area and gate upper surface at same horizontal plane, be beneficial to follow-up contact hole technology;
5, employing comes design of Si nano-wire field effect transistor (Si-NWFET) structure based on the three-dimensional array type silicon nanowire structure of SOI; Nano wire becomes three-dimensional array type to arrange; The nanometer number of lines increases, and has effectively improved the integrated level of device and has strengthened the current driving ability of device.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.
Claims (14)
1. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI is characterized in that, comprising:
SOI is provided substrate, and said SOI substrate is followed successively by silicon lining, insulator layer and top layer silicon from down to up;
Said SOI substrate surface is handled, said SOI substrate top layer silicon is converted into initial germanium silicon layer;
On said SOI substrate, alternately form silicon layer and follow-up germanium silicon layer, said initial germanium silicon layer and said follow-up germanium silicon layer constitute the germanium silicon layer jointly;
To said germanium silicon layer and silicon layer etching processing, form the fin-shaped active area, said fin-shaped active area is a three-dimensional array type, remaining areas is as source-drain area;
In said fin-shaped active area, form silicon nanowires, said silicon nanowires three-dimensional array type piles up;
Form grid oxic horizon on said silicon nanowires, SOI substrate and source-drain area surface;
On the SOI substrate between the said source-drain area, form grid;
Between said source-drain area and said grid, form the spacer medium layer.
2. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, said SOI substrate surface is handled, and the concrete operations that said SOI substrate top layer is converted into initial germanium silicon layer are:
Deposit a germanium layer at said SOI substrate surface;
To said germanium layer oxidation processes, the concentrated silicon with said SOI substrate top layer of germanium oxidation forms initial germanium silicon layer in the said germanium layer, and said initial germanium silicon layer upper surface is SiO
2Layer;
Wet method is removed said SiO
2Layer.
3. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that said silicon layer is at least one deck, and said germanium silicon layer manys one deck than said silicon layer.
4. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, after said germanium silicon layer and silicon layer etching processing, ion is carried out in the zone between the said source-drain area inject.
5. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, forms on the SOI substrate between the said source-drain area after the grid, said source-drain area is carried out ion inject.
6. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, said silicon nanowires diameter is between 1 nanometer～1 micron.
7. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, the cross sectional shape of said silicon nanowires is circular, horizontal track shape or vertical track shape.
8. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, before forming grid oxic horizon on said silicon nanowires, SOI substrate and the source-drain area, also comprises:
Said silicon nanowires is carried out thermal oxidation;
Etch away the silicon dioxide that said thermal oxidation forms.
9. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K medium.
10. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 9 is characterized in that said high K medium is HfO
2, Al
2O
3, ZrO
2In a kind of or its combination in any.
11. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that the material of grid is a kind of or its combination in any in polysilicon, amorphous silicon, the metal.
12. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that the material of said spacer medium layer is a silicon dioxide.
13. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 1 is characterized in that, said etching adopts time normal pressure chemical gas phase etching method.
14. the three-dimensional array type silicon nanowires field effect transistor tube preparation method based on SOI as claimed in claim 13; It is characterized in that; Said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body; Wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
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| CN105575895A (en) * | 2016-02-23 | 2016-05-11 | 广东工业大学 | Method for producing field-control band-pass transistor array device by utilizing two-dimensional semiconductor |
| CN108133960A (en) * | 2017-11-15 | 2018-06-08 | 中国科学院微电子研究所 | Ring gate nano line tunneling field-effect transistor of vertical stacking and preparation method thereof |
| CN111435641A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked gate-all-around transistor and preparation method thereof |
| CN111435682A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Multi-channel gate-all-around transistor |
| CN111435643A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of three-dimensional stacked gate-all-around transistor |
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Cited By (6)
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| CN105575895A (en) * | 2016-02-23 | 2016-05-11 | 广东工业大学 | Method for producing field-control band-pass transistor array device by utilizing two-dimensional semiconductor |
| CN105575895B (en) * | 2016-02-23 | 2018-01-23 | 广东工业大学 | A kind of method that band logical transistor array devices are controlled using two-dimensional semiconductor fabricating yard |
| CN108133960A (en) * | 2017-11-15 | 2018-06-08 | 中国科学院微电子研究所 | Ring gate nano line tunneling field-effect transistor of vertical stacking and preparation method thereof |
| CN111435641A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional stacked gate-all-around transistor and preparation method thereof |
| CN111435682A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Multi-channel gate-all-around transistor |
| CN111435643A (en) * | 2019-01-11 | 2020-07-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of three-dimensional stacked gate-all-around transistor |
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