CN101648695B - MEMS bulk silicon technological method for transferring mask layer three-dimensional structure - Google Patents
MEMS bulk silicon technological method for transferring mask layer three-dimensional structure Download PDFInfo
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- CN101648695B CN101648695B CN2009100920351A CN200910092035A CN101648695B CN 101648695 B CN101648695 B CN 101648695B CN 2009100920351 A CN2009100920351 A CN 2009100920351A CN 200910092035 A CN200910092035 A CN 200910092035A CN 101648695 B CN101648695 B CN 101648695B
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Abstract
The invention discloses an MEMS bulk silicon technological method for transferring a mask layer three-dimensional structure, comprising a step of manufacturing the mask layer three-dimensional structure and a step of transferring the mask layer three-dimensional structure to a silicon substrate. Before processing a deep groove structure, the mask layer of the silicon substrate is firstly manufactured, and then N times of imaging processes are carried out on the mask layer for N processing depths corresponding to N different areas on the silicon substrate to form the three-dimensional structure of the mask layer, and then the finished three-dimensional structure of the mask layer is transferred to the silicon substrate by wet etching or dry etching, N times of deep groove structure processes are carried out on the silicon substrate to obtain the MEMS bulk silicon structure with N different depths, and all mask layers are removed after N times of deep groove structure processes to form the MEMS bulk silicon structure with N different depths. The invention reduces the difficulty of imaging and improves the precision of imaging at the same time.
Description
Technical field
The present invention relates to the MEMS bulk silicon technological method that a kind of mask layer three-dimensional structure shifts, relate in particular to the MEMS bulk silicon technological method that a kind of needs carry out repeatedly deep groove structure processing, be mainly used in the development and the production and processing of various MEMS devices.
Background technology
The MEMS technology is the basis of modernized national defence and following high-tech leading industry, and its development will cause weaponry and social life each side generation revolutionary variation.For example, utilize technological silicon micro mechanics device of producing of MEMS and silicon micro-inertia sensor (silicon micro-gyroscope and silicon micro accerometer), realized that volume is little, in light weight with its microminiaturization, integrated; Low and the batch process of cost; It is big also to have measurement category in addition, and good reliability is low in energy consumption; Be easy to realize advantages such as digitlization and intellectuality, it has demand widely at space industry, military field and civil area.In the MEMS technology, the MEMS bulk silicon technological is a kind of main technique technology, grinds in the product at the MEMS device and is used widely, like inertia device and mechanics device etc.
MEMS bulk silicon technological commonly used at present such as Fig. 1 are to shown in Figure 5.As shown in Figure 1, the mask layer 12 after first general is graphical is for the first time transferred on the substrate slice 11; Then the substrate slice among Fig. 1 11 is adopted the silicon substrate film 21 after wet etching or dry etch process processing obtain deep groove structure processing for the first time, as shown in Figure 2, the mask layer after the deep groove structure processing for the first time is 22; Re-using glue spraying equipment is 22 to carry out for the second time graphical post processing and obtain mask layer as shown in the figure 32 to mask layer; Owing to have deep groove structure among Fig. 2; Mask among Fig. 2 is carried out the second time when graphical; Common spin-coating glue evenning table can not carry out graphically deep groove structure, can only use glue spraying equipment to carry out graphically; And then to carrying out the deep trench processing second time behind substrate slice employing dry etching shown in Figure 3 or the wet etching; As shown in Figure 4; 41 for carrying out the silicon substrate film after the deep groove structure processing for the second time; 42 for carrying out the mask layer after the deep groove structure processing for the second time, at last the mask layer among Fig. 4 42 removed the silicon substrate film 51 that obtains after the secondary deep groove structure processing shown in Figure 5.The main technique bottleneck of above-mentioned bulk silicon technological is the graphical of band deep groove structure, and common spin-coating glue evenning table can not carry out graphically the substrate slice of band deep groove structure, and that is with the deep groove structure substrate slice graphically can only use glue spraying equipment.When not having glue spraying equipment, this MEMS bulk silicon technological commonly used can't be proceeded following process.Yet, with do not have deep groove structure before graphically compare, after having deep groove structure, even use glue spraying equipment, in the sheet of silicon substrate film and to each other graphical precision and uniformity also all can variation.When the MEMS bulk silicon technological that carries out three times or more times deep groove structure is processed, also all there is the patterned technology bottleneck of deep groove structure.
Summary of the invention
The problem that the present invention solves is: the deficiency that overcomes existing MEMS bulk silicon technological; The MEMS bulk silicon technological method that provides a kind of mask layer three-dimensional structure to shift; Accomplish the graphical technology of all mask layers in the deep groove structure first being processed, improved patterned precision when having reduced graphical difficulty.
Technical solution of the present invention is: the MEMS bulk silicon technological method that mask layer three-dimensional structure shifts, and mask layer three-dimensional structure preparation process and mask layer three-dimensional structure are to the silicon substrate film transfer step;
The mask layer three-dimensional structure preparation process is: the mask layer that at first prepares silicon substrate film; To corresponding N the working depth of N zones of different on the silicon substrate film thereby mask layer is carried out the three-dimensional structure of N graphical treatment formation mask layer, wherein the mask layer patterns treatment process of each working depth correspondence on the silicon substrate film then;
Mask layer three-dimensional structure to the silicon substrate film transfer step is: transfer to the mask layer three-dimensional structure for preparing on the silicon substrate film through wet etching or dry etch process; On silicon substrate film, carry out N deep groove structure processing; Obtain having the MEMS body silicon structure of N different depth; Between adjacent twice deep groove structure processing mask layer is carried out whole attenuate; Expose the respective regions that silicon substrate film need carry out deep groove structure processing, N time all mask layers are removed in deep groove structure processing back, form the MEMS body silicon structure with N different depth.
The method of in the said mask layer three-dimensional structure preparation process mask layer being carried out N graphical treatment is: N zones of different is designated as An; N N corresponding working depth of zones of different is designated as Dn; Wherein Dn＞Dn-1＞...＞D2＞D1; Then the N time graphical institute corresponding region is designated as Mn, and each graphical treatment corresponding region is M1=A1+A2+...+An-1+An; M2=A2+A3+...+An-1+An; M3=A3+...+An-1+An......Mn-1=An-1+An; Mn=An, wherein n is a natural number.
The degree of depth of said mask layer three-dimensional structure each deep trouth processing in the silicon substrate film transfer step is: the working depth of the n time silicon substrate film deep trouth processing is designated as DSn; DS1=Dn-Dn-1, DS2=Dn-1-Dn-2...DSn-1=D2-D1, DSn=D1, wherein n is a natural number.
Said mask layer is one or more in silica, silicon nitride, phosphosilicate glass, pyrex, boron phosphosilicate glass, aluminium, gold, chromium, tungsten and the photoresist.
Said mask layer three-dimensional structure is taked wet etching or dry etching to the method that mask layer carries out whole attenuate in the silicon substrate film transfer step.
The present invention's advantage compared with prior art is: MEMS bulk silicon technological commonly used still need carry out graphical in the first time after the deep groove structure processing; But common spin-coating glue evenning table can not carry out graphically the substrate slice of band deep groove structure; Can only use special glue spraying equipment; When not having glue spraying equipment, this MEMS bulk silicon technological commonly used can't be proceeded following process; And with preceding graphically the comparing of deep groove structure processing, after there was deep groove structure in silicon substrate film, even use glue spraying equipment, it is big that its technology cost and technology difficulty become, and the graphical precision and the uniformity that reach between sheet in the sheet also all can variation.The present invention at first prepares three-dimensional structure in the deep groove structure first being processed on mask layer; Accomplish all graphical technologies of MEMS bulk silicon technological; Graphical technology is can service precision higher, uniformity and the better common spin coating equipment for evenly dividing glue of uniformity; When reducing graphical equipment requirements and graphical difficulty, patterned precision and uniformity have been improved; When transferring on the silicon substrate film, no longer need graphical technology to wet etching or the dry etch process of the mask layer three-dimensional structure for preparing through standard.Compare with MEMS bulk silicon technological commonly used, the present invention has that technology difficulty is low, cost is low, the high tangible advantage of machining accuracy.
Description of drawings
Fig. 1 is the mask graph sketch map first time of MEMS bulk silicon technological commonly used;
Fig. 2 is the deep groove structure processing first time sketch map of MEMS bulk silicon technological commonly used;
Fig. 3 is the mask graph sketch map second time of MEMS bulk silicon technological commonly used;
Fig. 4 is the deep groove structure processing second time sketch map of MEMS bulk silicon technological commonly used;
Fig. 5 is for using the final result sketch map after the MEMS bulk silicon technological is removed mask always;
Fig. 6 is the mask layer preparation of the embodiment of the invention;
Fig. 7 is that embodiment of the invention mask layer is graphical for the first time;
Fig. 8 is that embodiment of the invention mask layer is graphical for the second time;
Fig. 9 is that embodiment of the invention mask layer is graphical for the third time;
Figure 10 is that embodiment of the invention mask layer the 4th time is graphical;
Figure 11 is that embodiment of the invention mask layer the 5th time is graphical;
Figure 12 is that embodiment of the invention mask layer the 6th time is graphical;
Figure 13 is the silicon substrate film structure after the deep groove structure first time of the embodiment of the invention is processed;
Figure 14 A is the mask layer attenuate after the embodiment of the invention deep groove structure processing for the first time;
Figure 14 B is the silicon substrate film structure after the deep groove structure second time of the embodiment of the invention is processed;
Figure 15 A is the mask layer attenuate after the embodiment of the invention deep groove structure processing for the second time;
Figure 15 B is the silicon substrate film structure after the deep groove structure for the third time of the embodiment of the invention is processed;
Figure 16 A is the mask layer attenuate after the embodiment of the invention deep groove structure processing for the third time;
Figure 16 B is the silicon substrate film structure after the 4th deep groove structure of the embodiment of the invention processed;
Figure 17 A is the mask layer attenuate after the 4th the deep groove structure processing of the embodiment of the invention;
Figure 17 B is the silicon substrate film structure after the 5th deep groove structure of the embodiment of the invention processed;
Figure 18 A is the mask layer attenuate after the 5th the deep groove structure processing of the embodiment of the invention;
Figure 18 B is the silicon substrate film structure after the 6th the deep groove structure processing of the embodiment of the invention;
Figure 19 removes the MEMS body silicon structure of six kinds of different depths behind the mask layer for the embodiment of the invention.
The specific embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is done further detailed description.
The present invention includes mask layer three-dimensional structure preparation and mask layer three-dimensional structure and shift two parts content to silicon substrate film.Mask layer three-dimensional structure prepares process: to the different working depths in each zone on the silicon substrate film, and the once graphical technology of each working depth correspondence, graphical technology is carried out on mask layer.For example; Working depth is divided into the degree of depth 1, the degree of depth 2, the degree of depth 3, the degree of depth 4, the degree of depth 5 and 6 six kinds of degree of depth of the degree of depth; Then corresponding six the graphical technologies of six kinds of degree of depth process six kinds of degree of depth of corresponding patterned area successively on mask layer, form the three-dimensional structure of mask layer.Mask layer three-dimensional structure to the process that silicon substrate film shifts is: after accomplishing mask layer three-dimensional structure processing; Transfer to the three-dimensional structure of mask layer on the silicon substrate film through wet etching and dry etch process again, thus the processing of completion mask layer three-dimensional structure transfer method MEMS bulk silicon technological.
The design rule of bulk silicon technological method of the present invention is: Dn represents the degree of depth n of the deep groove structure on the silicon substrate film, wherein n=1,2, natural numbers such as 3; The deep trouth machining area that then Dn is corresponding is An, wherein n=1,2, natural numbers such as 3; N kind working depth need carry out n time graphical, the n time patterned corresponding region is Mn, wherein n=1,2, natural numbers such as 3.Satisfy regular between the different depth: Dn＞Dn-1＞...＞D4＞D3＞D2＞D1.The patterned corresponding region Mn of homogeneous does not satisfy regular M1=A1+A2+A3+...+An-1+An; M2=A2+A3++...+An-1+An; M3=A3+...+An-1+An; M4=A4+...+An-1+An; Mn-1=An-1+An; Mn=An.Carrying out three-dimensional structure after graphical n time shifts; On silicon substrate film, carry out n deep groove structure processing; Obtain having the MEMS body silicon structure of n kind different depth after n the deep groove structure processing; The working depth of the n time silicon substrate film deep trouth processing is DSn, wherein n=1,2, natural numbers such as 3, DS1=Dn-Dn-1, DS2=Dn-1-Dn-2...DSn-1=D2-D1, DSn=D1.
For example: when six kinds of degree of depth: different depth value D6＞D5＞D4＞D3＞D2＞D1; Graphical corresponding region is M1=A1+A2+A3+A4+A5+A6; M2=A2+A3+A4+A5+A6; M3=A3+A4+A5+A6; M4=A4+A5+A6; M5=A5+A6; M6=A6; DS1=D6-D5; DS2=D5-D4, DS3=D4-D3, DS4=D3-D2, DS5=D2-D1, DS6=D1.
When five kinds of degree of depth: different depth value D5＞D4＞D3＞D2＞D1; Graphical corresponding region is M1=A1+A2+A3+A4+A5; M2=A2+A3+A4+A5; M3=A3+A4+A5; M4=A4+A5; M5=A5; DS1=D5-D4, DS2=D4-D3, DS3=D3-D2, DS4=D2-D1, DS5=D1.
When four kinds of degree of depth: different depth value D4＞D3＞D2＞D1; Graphical corresponding region is M1=A1+A2+A3+A4; M2=A2+A3+A4; M3=A3+A4; M4=A4; DS1=D4-D3, DS2=D3-D2, DS3=D2-D1, DS4=D1.
When three kinds of degree of depth: different depth value D3＞D2＞D1; Graphical corresponding region is M1=A1+A2+A3; M2=A2+A3; M3=A3; DS1=D3-D2, DS2=D2-D1, DS3=D1.
When two kinds of degree of depth: different depth value D2＞D1; Graphical corresponding region is M1=A1+A2; M2=A2; DS1=D2-D1, DS2=D1.
When a kind of degree of depth: depth value is D1; Graphical corresponding region is M1=A1; The depth DS 1=D1 of deep trouth processing for the first time.
The MEMS bulk silicon technological of above-mentioned six kinds of deep groove structure types though the kind of the degree of depth is different, all meets identical design rule.According to the demand of reality processing device, can adjust the processing number of times of wet etching and dry etching, do not influence the integrated artistic flow rules.Wherein the most representative is the MEMS bulk silicon technological with six kinds of degree of depth, and technological process is referring to Fig. 6～Figure 19, wherein mask layer three-dimensional structure preparation as Fig. 6～shown in Figure 12, mask layer three-dimensional structure to the silicon substrate film transfer like Figure 13～shown in Figure 19.
Mask layer three-dimensional structure transfer method MEMS bulk silicon technological at first need prepare mask layer on silicon substrate film, mask layer thickness is TM.On mask layer, prepare the three-dimensional structure of six different depths then through pattern technology; Mask layer can be silica, silicon nitride, phosphosilicate glass, pyrex, boron phosphosilicate glass, aluminium, gold, chromium, tungsten or photoresist, concrete process sequence such as Fig. 6～and shown in Figure 12.
61 is silicon substrate films among Fig. 6, the 62nd, do not carry out patterned mask layer as yet.
71 is silicon substrate films among Fig. 7, the 72nd, and the mask layer after the first time is graphical, patterned area is M1 for the first time.
81 is silicon substrate films among Fig. 8, the 82nd, and the mask layer after the second time is graphical, patterned area is M2 for the second time.
91 is silicon substrate films among Fig. 9, the 92nd, and the mask layer after graphical for the third time, patterned area is M3 for the third time.
101 is silicon substrate films among Figure 10, and 102 is the 4th mask layers after graphical, and the 4th time patterned area is M4.
111 is silicon substrate films among Figure 11, and 112 is the 5th mask layers after graphical, and the 5th time patterned area is M5.
121 is silicon substrate films among Figure 12, and 122 is the 6th mask layers after graphical, and the 6th time patterned area is M6.
After preparing three-dimensional structure on the mask layer; Remove technology through wet etching, dry etching and mask layer; Transfer to the respective regions on the silicon substrate film to the three-dimensional structure on the mask layer; Process the MEMS body silicon structure that possesses six kinds of different depths, concrete process sequence such as Figure 13～shown in Figure 19.
After the mask layer three-dimensional structure preparation, expose silicon substrate film in the zone of M6, silicon substrate film is carried out wet etching or dry etching, carry out the deep groove structure processing first time, working depth is DS1=D6-D5.Shown in figure 13, wherein 131 is silicon substrate films after the deep groove structure processing for the first time, and machining area is M6, the 132nd, and the mask layer after the deep groove structure processing for the first time.
After the deep groove structure processing for the first time, carry out the whole attenuate of mask layer, the thickness of mask layer attenuate is TM/6, shown in Figure 14 A.After the mask layer reduced thickness, expose silicon substrate film in the zone of M5, silicon substrate film is carried out wet etching or dry etching, carry out the deep groove structure processing second time, working depth is DS2=D5-D4, shown in Figure 14 B.In Figure 14 A and Figure 14 B, 1411,1412 is respectively the silicon substrate film before and after the deep groove structure processing for the second time, and machining area is M5, the 142nd, and the mask layer of deep groove structure processing for the second time.
After the deep groove structure processing for the second time, carry out the whole attenuate of mask layer, the thickness of mask layer attenuate is TM/6, shown in Figure 15 A.After the mask layer reduced thickness, expose silicon substrate film in the zone of M4, silicon substrate film is carried out wet etching or dry etching, carry out deep groove structure processing for the third time, working depth is DS3=D4-D3, shown in Figure 15 B.In Figure 15 A and Figure 15 B, 1511 and 1512 is respectively the silicon substrate film before and after the deep groove structure processing for the third time, and machining area is M4, the 152nd, and the mask layer of deep groove structure processing for the third time.
After the deep groove structure processing for the third time, carry out the whole attenuate of mask layer, the thickness of mask layer attenuate is TM/6, shown in Figure 16 A.After the mask layer reduced thickness, expose silicon substrate film in the zone of M3, silicon substrate film is carried out wet etching or dry etching, carry out the 4th deep groove structure processing, working depth is DS4=D3-D2, shown in Figure 16 B.In Figure 16 A and Figure 16 B, 1611 and 1612 is respectively the 4th silicon substrate film before and after the deep groove structure processing, and machining area is M3, and 162 is mask layers of the 4th deep groove structure processing.
After the 4th the deep groove structure processing, carry out the whole attenuate of mask layer, the thickness of mask layer attenuate is TM/6, shown in Figure 17 A.After the mask layer reduced thickness, expose silicon substrate film in the zone of M2, silicon substrate film is carried out wet etching or dry etching, carry out the 5th deep groove structure processing, working depth is DS5=D2-D1, shown in Figure 17 B.In Figure 17 A and Figure 17 B, 1711 and 1712 is respectively the 5th silicon substrate film before and after the deep groove structure processing, and machining area is M2, and 172 is mask layers of the 5th deep groove structure processing.
After the 5th the deep groove structure processing, carry out the whole attenuate of mask layer, the thickness of mask layer attenuate is TM/6, shown in Figure 18 A.After the mask layer reduced thickness, expose silicon substrate film in the zone of M1, silicon substrate film is carried out wet etching or dry etching, carry out the 6th deep groove structure processing, working depth is DS6=D1, shown in Figure 18 B.In Figure 18 A and Figure 18 B, 1811 and 1812 is respectively the 6th silicon substrate film before and after the deep groove structure processing, and machining area is M1, and 182 is mask layers of the 6th deep groove structure processing.
After the 6th the deep groove structure processing, carry out the whole removing of mask layer and remove, obtain having the MEMS body silicon structure of six kinds of different depths, shown in figure 19.
After the processing of MEMS body silicon structure; Metallize, wafer bonding technology, chip bonding process; Accomplish the integrated artistic flow process; Metallization process can be sputtering technology, evaporation technology, low-pressure chemical vapor phase deposition (LPCVD) technology, metal oxide chemical vapor deposition (MOCVD) technology, and used metal can be one or more in gold, titanium, tungsten, platinum, chromium, silver, aluminium, molybdenum, copper and the nickel.Wafer bonding technology and chip bonding process can be silicon/glass anode linkage, silicon/Si direct bonding, silicon/silicon eutectic metal bonding and silicon/oxidative silicon/silicon hot melt bonding technologies.
The present invention not detailed description is a technology as well known to those skilled in the art.
Claims (1)
1. the MEMS bulk silicon technological method that shifts of mask layer three-dimensional structure, it is characterized in that comprising: mask layer three-dimensional structure preparation process and mask layer three-dimensional structure are to the silicon substrate film transfer step;
The mask layer three-dimensional structure preparation process is: the mask layer that at first prepares silicon substrate film; To corresponding N the working depth of N zones of different on the silicon substrate film thereby mask layer is carried out the three-dimensional structure of N graphical treatment formation mask layer, wherein the mask layer patterns treatment process of each working depth correspondence on the silicon substrate film then;
Mask layer three-dimensional structure to the silicon substrate film transfer step is: transfer to the mask layer three-dimensional structure for preparing on the silicon substrate film through wet etching or dry etch process; On silicon substrate film, carry out N deep groove structure processing; Obtain having the MEMS body silicon structure of N different depth; Between adjacent twice deep groove structure processing mask layer is carried out whole attenuate; Expose the respective regions that silicon substrate film need carry out deep groove structure processing, N time all mask layers are removed in deep groove structure processing back, form the MEMS body silicon structure with N different depth;
The method of in the said mask layer three-dimensional structure preparation process mask layer being carried out N graphical treatment is: N zones of different is designated as An; N N corresponding working depth of zones of different is designated as Dn; Wherein Dn＞Dn-1＞...＞D2＞D1; Then the N time graphical institute corresponding region is designated as Mn, and each graphical treatment corresponding region is M1=A1+A2+...+An-1+An; M2=A2+A3+...+An-1+An; M3=A3+A4+...+An-1+An; ...; Mn-1=An-1+An; Mn=An, wherein n is a natural number;
The degree of depth of said mask layer three-dimensional structure each deep trouth processing in the silicon substrate film transfer step is: the working depth of the n time silicon substrate film deep trouth processing is designated as DSn; DS1=Dn-Dn-1, DS2=Dn-1-Dn-2 ..., DSn-1=D2-D1, DSn=D1, wherein n is a natural number;
Said mask layer is one or more in silica, silicon nitride, phosphosilicate glass, pyrex, boron phosphosilicate glass, aluminium, gold, chromium, tungsten and the photoresist;
Said mask layer three-dimensional structure is taked wet etching or dry etching to the method that mask layer carries out whole attenuate in the silicon substrate film transfer step.
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| CN102001618B (en) * | 2010-10-27 | 2012-11-21 | 天津海鸥表业集团有限公司 | Masking method for deep-etching multi-layer silicon structure by dry method |
| CN102491253B (en) * | 2011-11-29 | 2014-08-20 | 北京大学 | Processing method of different-height silicon structures |
| CN102583225B (en) * | 2012-03-09 | 2015-05-06 | 上海先进半导体制造股份有限公司 | Fabricating method for one-dimensional large-scale multistage-step structure |
| CN106032268A (en) * | 2015-03-20 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing MEMS device |
| CN108069387B (en) * | 2016-11-18 | 2020-01-31 | 上海新微技术研发中心有限公司 | Method for forming various surface-shaped structures on surface of substrate |
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| US5741741A (en) * | 1996-05-23 | 1998-04-21 | Vanguard International Semiconductor Corporation | Method for making planar metal interconnections and metal plugs on semiconductor substrates |
| CN1402047A (en) * | 2002-07-13 | 2003-03-12 | 华中科技大学 | Process for mfg. multi-phase diffraction optic element |
| CN1438544A (en) * | 2003-02-28 | 2003-08-27 | 北京大学 | Method for deep etching multi-layer high depth-width-ratio silicon stairs |
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| US5741741A (en) * | 1996-05-23 | 1998-04-21 | Vanguard International Semiconductor Corporation | Method for making planar metal interconnections and metal plugs on semiconductor substrates |
| CN1402047A (en) * | 2002-07-13 | 2003-03-12 | 华中科技大学 | Process for mfg. multi-phase diffraction optic element |
| CN1438544A (en) * | 2003-02-28 | 2003-08-27 | 北京大学 | Method for deep etching multi-layer high depth-width-ratio silicon stairs |
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