CN101632178A - 短沟道低电压、中间电压和高电压cmos装置 - Google Patents

短沟道低电压、中间电压和高电压cmos装置 Download PDF

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CN101632178A
CN101632178A CN200880007869A CN200880007869A CN101632178A CN 101632178 A CN101632178 A CN 101632178A CN 200880007869 A CN200880007869 A CN 200880007869A CN 200880007869 A CN200880007869 A CN 200880007869A CN 101632178 A CN101632178 A CN 101632178A
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drain electrode
source electrode
epitaxial loayer
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CN101632178B (zh
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蔡军
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Fairchild Semiconductor Corp
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Abstract

低电压、中间电压和高电压CMOS装置具有：上部缓冲层，其具有与源极和漏极相同的导电性类型，且在所述源极和漏极以及栅极下延伸但不经过所述栅极的中部；以及下部块缓冲层，其具有与所述上部缓冲层相反的导电性类型，且从所述上部缓冲层下延伸经过所述栅极的所述中部，从而在所述栅极下形成所述两个块缓冲层的重叠。可使用两个遮蔽层来针对NMOS和PMOS FET两者植入所述上部缓冲层和所述下部块缓冲层。对于中间电压和高电压装置，所述上部缓冲层连同所述下部块缓冲层一起提供resurf区。

Description

短沟道低电压、中间电压和高电压CMOS装置
技术领域
本发明涉及互补MOSFET，且更明确地说，涉及具有LV、MV和HV实施例的CMOS短沟道装置。
背景技术
具有短沟道的MOSFET是有利的，因为它们与常规MOSFET相比，使用芯片上的较少面积，从而允许芯片上的更多功能性，具有较低的接通电阻(Ron)，且具有较快的切换特性。然而，缩短沟道通常会引起一般被称为“短沟道效应”的缺点。此些效应包含到达栅极氧化物中且到达装置衬底中的热载流子注入(HCI)，其影响装置的可靠性，且可使装置的Ron降级。另一短沟道效应是装置的穿通电压的减小，因此，装置的漏极到源极的击穿电压(BVdss)减小。所述效应对于在中间电压和高电压应用中使用的MOSFET来说特别成问题，尤其是在此些MOSFET与低电压电路位于同一裸片上的情况下。
因此，与现有技术短沟道MOSFET相比减小这些短沟道效应的短沟道LV、MV和HV装置是合乎需要的。
另外，可与LV装置放置在同一裸片上的短沟道MV和HV CMOS装置也是合乎需要的。
发明内容
本发明的一种形式包括N沟道MOSFET(NMOS)，其具有位于衬底上的P-外延层，其中源极和漏极形成于所述外延层中，且位于栅极的相对侧，所述栅极位于栅极氧化物上，所述栅极氧化物位于所述外延层上。第一N型缓冲层从源极下横向延伸到外延层的顶部表面处的栅极的离源极最近的第一边缘与所述栅极的中部之间的位置，且第二N型缓冲层从漏极下横向延伸到外延层的顶部表面处的栅极的离漏极最近的第二边缘与所述栅极的中部之间的位置。另外，第一P型块层从第一N型缓冲层横向延伸到外延层的顶部表面处的栅极下比到源极更靠近漏极的位置，且第二P型块层从第二N型缓冲层横向延伸到外延层的顶部表面处的栅极下比到漏极更靠近源极的位置，所述第一和第二P型块层在栅极下的区中彼此上覆。
本发明的另一形式包括P沟道MOSFET(PMOS)，其具有位于衬底上的P-外延层以及形成于所述外延层中的N-槽。源极和漏极形成于外延层中，且位于栅极的相对侧，所述栅极位于栅极上，所述栅极位于外延层上。第一P型缓冲层从源极下横向延伸到外延层的顶部表面处的栅极的离源极最近的第一边缘与所述栅极的中部之间的位置，且第二P型缓冲层从漏极下横向延伸到外延层的顶部表面处的栅极的离漏极最近的第二边缘与所述栅极的中部之间的位置。另外，第一N型块层从第一P型缓冲层横向延伸到外延层的顶部表面处的栅极下比到源极更靠近漏极的位置，且第二N型块层从第二P型缓冲层横向延伸到外延层的顶部表面处的栅极下比到漏极更靠近源极的位置，所述第一和第二N型块层在栅极下的区中彼此上覆。
本发明的又一形式包括形成于衬底上的一对互补N沟道MOSFET(NMOS)与P沟道MOSFET(PMOS)(CMOS)装置，其包含上文所述的NMOS FET和上文所述的PMOSFET。
在再一形式中，本发明包含一种用于通过在P+衬底上生长P-外延层、形成位于所述外延层上的栅极氧化物层且在所述栅极氧化物层上形成栅极来形成N沟道MOSFET(NMOS)的方法。所述方法还包含形成与栅极的相对侧对准的两个上部N型缓冲区，以及与栅极的相对侧对准的两个下部P型块缓冲区，其每一者位于所述上部缓冲区中的每一者的下方，所述下部块缓冲区横向延伸经过栅极的中部，使得所述两个下部块缓冲区在栅极下重叠，上部缓冲区和下部块缓冲区在单个遮蔽操作后形成。
在又一形式中，本发明包含一种用于通过在P+衬底上生长P-外延层，在所述外延层中形成延伸到所述外延层的顶部表面的N-槽，形成位于所述外延层上的栅极氧化物层且在所述栅极氧化物层上形成栅极来形成P沟道MOSFET(PMOS)的方法。所述方法进一步包含形成与栅极的相对侧对准的两个上部P型缓冲区，以及与栅极的相对侧对准的两个下部N型块缓冲区，其每一者位于所述上部缓冲区中的每一者的下方，所述下部块缓冲区横向延伸经过栅极的中部，使得所述两个下部块缓冲区在栅极下重叠，上部缓冲区和下部块缓冲区在单个遮蔽操作后形成。
在额外形式中，本发明包含用于通过根据上文所述的工艺形成NMOS FET且根据上文所述的工艺形成PMOS FET来形成互补MOS(CMOS)装置的方法，N-槽横向延伸越过PMOS FET。
附图说明
结合附图参考对本发明各个实施例的以下描述，将明白且更好地理解本发明的特征和优点以及获得所述特征和优点的方式，其中：
图1A和图1B分别是根据本发明的低电压(LV)N沟道MOSFET(NMOS)和LVP沟道MOSFET(PMOS)的图解视图；
图2A和图2B分别是图1A和图1B中所示的LV NMOS和LV PMOS的其它实施例的图解视图；
图3A和图3B分别是根据本发明的中间电压(MV)N沟道MOSFET(NMOS)和MV P沟道MOSFET(PMOS)的图解视图；
图4A和图4B分别是图3A和图3B中所示的MV NMOS和MV PMOS的其它实施例的图解视图；
图5A和图5B分别是根据本发明的高电压(HV)N沟道MOSFET(NMOS)和HVP沟道MOSFET(PMOS)的图解视图；
图6是被隔离的LV NMOS的图解视图；
图7是用于MV或HV NMOS的隔离区的图解视图；
图8是根据本发明的可用于形成互补MOS(CMOS)装置的主要处理步骤的流程图；
图9是根据本发明的可用于形成分裂式栅极氧化物互补MOS(CMOS)装置的主要处理步骤的流程图；
图10是根据本发明的可用于形成具有被隔离的NMOS FET的互补MOS(CMOS)装置的主要处理步骤的流程图；
图11是标准NMOS FET的图解视图；
图12A和图12B分别展示本发明的LV NMOS和图11的标准NMOS FET的模拟漏极电流密度特性；
图13A和图13B分别展示本发明的LV NMOS和图11的标准NMOS FET的模拟频率转变(Ft)特性；
图14A和图14B分别展示本发明的LV NMOS和图11的标准NMOS FET的模拟跨导特性；
图15A和图15B分别展示本发明的LV NMOS和图11的标准NMOS FET的模拟阈值电压特性；
图16A和图16B分别展示本发明的LV NMOS和图11的标准NMOS FET的模拟击穿电压(BVdss)特性；
图17A和图17B分别展示根据本发明而制作的具有薄栅极氧化物的实验晶体管(ET)的所测量电流-电压和BVdss特性；
图17C展示与用于图17A和图17B的测量相同的ET的所测量阈值电压和跨导；
图18A和图18B分别展示根据本发明而制作的具有厚栅极氧化物的ET的所测量电流-电压和BVdss特性；以及
图18C展示与用于图18A和图18B的测量相同的ET的所测量阈值电压和跨导。
将了解，出于清楚的目的，且在认为适当的情况下，已在图中重复参考标号以指示对应的特征。而且，图中各个对象的相对大小在一些情况下已失真，以更清楚地展示本发明。本文所陈述的实例说明本发明的若干实施例，但不应被解释为以任何方式限制本发明的范围。
具体实施方式
现在转向图式，图1A是低电压(LV)N沟道MOSFET(NMOS)10的图解视图，所述LV N沟道MOSFET具有上面沉积有P-外延(epi)层14的P+衬底12。N+源极16形成于epi层14中，N+源极16与位于N+极16顶部的源极硅化物18接触，且具有连接到其的源极触点20。N+漏极22也形成于epi层14中，N+漏极22与位于N+漏极22顶部的漏极硅化物24接触，且具有连接到其的漏极触点26。栅极28水平位于源极16与漏极22之间，其中栅极氧化物30位于epi层14与栅极28之间。位于栅极28上方且连接到栅极28的栅极硅化物32具有连接到栅极硅化物32的栅极触点34。栅极28和栅极氧化物30具有侧壁氧化物36和38，其在epi层14的顶部表面处水平延伸到源极硅化物18和漏极硅化物24。
N+源极16和N+漏极22两者分别具有形成于其下方的朝漏极22和源极16水平延伸的两个缓冲层。源极16下的上部缓冲层40和漏极22下的上部缓冲层42是N型区，其在epi层14的上部表面处的栅极28的相应最近边缘与栅极28的中部之间水平延伸。源极16下的下部缓冲层44(本文有时将其称为下部块缓冲层44)以及漏极22下的下部缓冲层46(本文有时将其称为下部块缓冲层46)是P型区，其每一者水平延伸经过栅极28的中心，使得两个层44和46彼此覆盖，以在栅极28下形成鞍形区48。
图1B是与图1A互补的CMOS。图1B是具有P+衬底12的低电压(LV)P沟道MOSFET(PMOS)60的图解视图，P-epi层14沉积在P+衬底12上，且N-槽66形成于epi层14中，且延伸到epi层14的顶部表面。P+源极68也形成于epi层14中的N-槽66中，P+源极68与位于P+源极68顶部的源极硅化物70接触，且具有连接到其的源极触点72。P+漏极74也形成于epi层14中的N-槽66中，P+漏极74与位于P+漏极74顶部的漏极硅化物76接触，且具有连接到其的漏极触点78。栅极80水平位于源极68与漏极74之间，其中栅极氧化物82位于epi层14与栅极80之间。位于栅极80上方且连接到栅极80的栅极硅化物84具有连接到栅极硅化物84的栅极触点86。栅极80和栅极氧化物82具有侧壁氧化物88和90，其在epi层14的顶部表面处水平延伸到源极硅化物70和漏极硅化物76。
P+源极68和P+漏极74两者分别具有形成于其下方的朝漏极74和源极68水平延伸的两个缓冲层。源极68下的上部缓冲层92和漏极74下的上部缓冲层94是P型区，其在epi层14的上部表面处的栅极80的相应最近边缘与栅极80的中部之间水平延伸。源极68下的下部缓冲层96(本文有时将其称为下部块缓冲层96)以及漏极74下的下部缓冲层98(本文有时将其称为下部块缓冲层98)是N型区，其每一者水平延伸经过栅极80的中心，使得两个区96和98彼此覆盖，以在栅极80下形成鞍形区100。
图1A和图1B中所示的LV NMOS和LV PMOS装置与图11中所示类型的标准短沟道NMOS FET相比提供经改进的操作特性。这些经改进的特性包含以下一者或一者以上：较高的穿通电压；较高的击穿电压(BVdss)；较低的接通电阻(Ron)；较低的漏极到源极电容(Cds)；较高的跨导(gm)；较快的切换速度以及Ron、gm和漏极饱和电流(IDsat)的减到最小的降级。与双缓冲层40、44；42、46；92、96以及94、98组合的鞍形掺杂轮廓48和100形成用于源极/漏极结的分级掺杂轮廓，以提供经改进的穿通电压和较高的BVdss。分级掺杂轮廓还增加漏极和源极耗尽区，以提供较低的Cds，其又提供较快的切换速度。上部缓冲层40、42、92和94的侧壁间隔物36、38、88和90下的深度和水平延伸允许沟道电子或空穴在epi层14中相对较深地扩散，以使热载流子注入效应减到最小，且从而减轻Ron、gm和IDsat的降级，且为低Ron提供有效较小沟道长度。低Ron和较低的Cds提供经改进的gm。
图2A和图2B分别是图1A和图1B中所示的装置10和60，其栅极和栅极氧化物经修改以分别形成分裂式栅极氧化物装置106和120。在图2A中，LV NMOS装置106具有栅极112，其具有带两个厚度的分裂式栅极氧化物114，即位于栅极112的离源极16最近的部分下的薄栅极氧化物区116，以及位于栅极112的离漏极22最近的部分下的厚栅极氧化物区114。上部缓冲层108和110进一步在栅极112下接着在图1A中的对应的上部缓冲层40和42下横向延伸。漏极22下的上部缓冲层110大致延伸到薄栅极氧化物区116与厚栅极氧化物区118之间的边界。在图2B中，LV PMOS装置120具有栅极122，其具有带两个厚度的分裂式栅极氧化物124，即位于栅极122的离源极68最近的部分下的薄栅极氧化物区126，以及位于栅极122的离漏极74最近的部分下的厚栅极氧化物区128。上部缓冲层130和132进一步在栅极124下接着在图1B中的对应的上部缓冲层92和94下横向延伸。漏极74下的上部缓冲层132大致延伸到薄栅极氧化物区126与厚栅极氧化物区128之间的边界。
分裂式栅极114、124减小由于分裂式栅极氧化物114、124的较厚区118、128处栅极112、122与epi层14的较大间隔而导致的密勒(Miller)反馈电容，因此降低反向转移电容(Crss)。分裂式栅极112、122还分别减少由于栅极112、122与漏极22、74之间减小的电场而导致的HCI问题。由于有效沟道长度被减小到分裂式栅极氧化物114、124的较薄区116、126的长度，因此gm因接通装置106、120所需的栅极电荷较低而存在改进。
在图1A的装置10、图1B的装置60、图2A的装置106和图2B的装置120中，缓冲层40、42、44、46、92、94、96、98、108、110、130和132植入为与栅极28、80、112和122自对准。源极16、68、源极硅化物18、70、漏极22、74以及漏极硅化物24、76形成为与栅极侧壁氧化物36、38、88和90自对准。NMOS装置10和106中的上部和下部缓冲层两者针对N型掺杂和P型掺杂(其可通过离子植入)使用同一掩模。类似地，PMOS装置60和120中的上部和下部缓冲层两者针对P型掺杂和N型掺杂两者使用同一掩模。因此，仅需要两个掩模来形成CMOS装置中的缓冲层。
图3A和图3B分别展示图1A和图1B的装置10、60的中间电压(MV)版本134和136。在图3A和图3B中，源极16、68和漏极22、74已相对于栅极28、80横向隔开。因此，在图3A中，源极16下的上部缓冲层138和下部缓冲层140形成源极16与栅极28之间的resurf区142。类似地，漏极22下的上部缓冲层144和下部缓冲层146形成漏极22与栅极28之间的resurf区148。在图3B中，源极68下的上部缓冲层150和下部缓冲层152形成源极68与栅极80之间的resurf区154。类似地，漏极74下的上部缓冲层156和下部缓冲层158形成漏极74与栅极80之间的resurf区160。尽管图3A和图3B中的装置134、136在栅极28和80的两侧具有resurf区142、148、154和160，其对于施加到漏极和源极的电压的极性可切换极性的应用来说是合适的，但在漏极电压总是大于源极电压的应用中，源极将不需要与栅极横向隔开，因此较小了装置的大小。
图4A和图4B中的装置160和162分别是图3A和图3B的装置134和136，其具有图4A中的分裂式栅极氧化物114和图4B中的分裂式栅极氧化物124、具有图4A中的上部缓冲层164和166，且具有图4B中的上部缓冲层168和170。上部缓冲层164、166、168和170与图3A和图3B中的上部缓冲层138、144、150和156相比，分别进一步在其相应的栅极114和124下延伸。图4A中的漏极22下的上部缓冲层166横向延伸到大致薄氧化物区116与厚氧化物区118之间的边界。类似地，图4B中的漏极74下的上部缓冲层170横向延伸到大致薄氧化物区126与厚氧化物区128之间的边界。
与缺乏resurf型漂移区的常规NMOS和PMOS晶体管相比，Resurf区142、148、154和160允许上部缓冲器138、144、150和156中的较高掺杂浓度或栅极与漏极和源极之间的较短间隔。
图5A和图5B分别展示图1A和图1B的装置10、60的高电压(HV)版本180和182。在制造图5A和图5B中所示的HV NMOS和HV PMOS装置的过程中，针对图5A中的场氧化物区200和202以及图5B中的场氧化物区204和206下面的装置漂移区而形成图5A中的上部缓冲层184和186、下部缓冲器192和194以及图5B中的上部缓冲层188和190、下部缓冲器196和198。这些缓冲层通过高能量植入而形成，高能量植入可经过场氧化物，因此存在与位于装置源极/漏极和栅极区域处或场氧化物下面的缓冲层有关的上部缓冲层或下部缓冲层的有差别的结深度。还使用场氧化物作为掩模来分别形成图5A中的源极224和漏极226以及分别形成图5B中的源极228和漏极230。在图5A中，源极硅化物232形成于源极224上，且漏极硅化物234形成于漏极226上。在图5B中，源极硅化物236形成于源极228上，且漏极硅化物238形成于漏极230上。
在图5A中，栅极240位于栅极氧化物242上，位于两个场氧化物200、202之间的区中，且与场氧化物重叠。栅极硅化物244位于栅极240上，且具有栅极触点246。类似地，在图5B中，栅极248位于栅极氧化物250上，位于两个场氧化物204、206之间的区中，且与场氧化物重叠。栅极硅化物252位于栅极248上，且具有栅极触点254。在图5A和图5B中，源极硅化物232、236分别具有源极触点256、258，且漏极硅化物234、238分别具有漏极触点260、262。
类似于图4A和图4B，resurf区264、266、268和269由上部和下部缓冲层形成。
图6是放置在包括N吸收器的隔离环272内的被隔离的LV NMOS 270的图解视图。隔离环272具有位于隔离环272的N吸收器的表面上的多个硅化物层274，其又具有隔离触点276。场氧化物区278、280、282和284位于隔离环272的N吸收器上，位于硅化物层274外部的区中。形成于P-epi层14中的是延伸越过隔离环的N埋入层286，以及位于N埋入层286顶部且也延伸越过隔离环272的P-底部层288。图6中将第二隔离环展示为一对P-阱290，其形成于场氧化物区280和282下，且从P-epi层14的顶部表面延伸到底部层288。P-底部层288和P-阱290的掺杂浓度大致比P-epi层14的掺杂浓度大三个数量级。
同一隔离结构(尽管在水平上必要地扩展)可与如图7中所示的MV NMOS装置和HV NMOS装置一起使用，其中MV NMOS装置和HV NMOS装置将被插入椭圆形296中。
图8是本发明的实施例中用来分别形成图1A、图1B、图3A和图3B的互补MOSFET10、60和134、136的主要处理步骤的连续列表300。下表含有对由图8的流程图中的框中的每一者表示的功能的描述。
  方框参考编号   功能
  302   形成P-Epi层
  304   P-型起始晶片
  306   使用N-槽掩模层形成用于PMOS装置的N-槽
  308   使用场氧化物掩模层形成场氧化物
  309   使用P-阱掩模层形成P-阱
  310   将薄(栅极)氧化物下放于晶片上
  312   使用电阻器掩模层来下放多晶硅电阻器
  314   使用栅极掩模层形成栅极
  316   使用NMOS缓冲掩模层将P型块缓冲层和N型缓冲层植入NMOS装置中
  318   使用PMOS缓冲掩模层将N型块缓冲层和P型缓冲层植入PMOS装置中
  320   形成栅极侧壁氧化物
  322   使用N+型源极和漏极掩模层将N+源极和漏极植入NMOS装置中
  324   使用P+型源极和漏极掩模层将P+源极和漏极植入PMOS装置中
  326   使用硅化物掩模层形成硅化物区
  328   沉积层间电介质
  330   使用触点掩模层在层间电介质中形成触点开口
  332   使用金属1掩模层形成金属1
  334   沉积金属间电介质
  336   使用通路掩模层打开金属间电介质中的通路
  338   使用金属2掩模层形成金属2
  340   钝化氧化物沉积
  342   使用线接合垫掩模层打开钝化的线接合垫。
为了避免不必要的混乱，对过程步骤的以下叙述将大体上仅参考图1A和图1B中的参考编号。如图8中所示，P-epi层14通过沉积在P-型起始晶片或衬底12上而形成，如分别在框302和304中所指示。在P MOSFET中，使用N-槽掩模层将N-槽66植入epi层14中，如框306中所指示。接着，生长场氧化物(如图5A和图5B中的场氧化物200、202、204和206)，如框308中所指示。P-阱290(有时被称为沟道中止层)在场氧化物处理后形成，以在技术中支持装置之间的隔离。对于被隔离装置架构(图6和图7)，P-阱290也用于p-型隔离环的部分。薄氧化物层(其部分将变成栅极氧化物)形成于晶片上，如框310中所指示，随后使用电阻器掩模层在场氧化物上沉积并遮蔽多晶硅电阻器，如框312中所指示。使用栅极掩模层，多晶硅栅极28、80形成于薄氧化物层上，如框314中所指示。
使用NMOS缓冲掩模层来植入NMOS下部块缓冲层44、46以及上部缓冲层40、42，如框316中所指示，随后使用PMOS缓冲掩模层来植入PMOS下部块缓冲层96、98以及上部缓冲层92、94，如框318中所指示。通过用所沉积的二氧化硅覆盖晶片且各向异性地蚀刻二氧化硅来形成栅极侧壁氧化物36、38、88和90，如框320中所指示。使用N+掩模层来植入NMOS源极和漏极16、22，如框322中所指示，随后使用P+掩模层来植入PMOS源极和漏极68、74，如框324中所指示。使用硅化物掩模层来形成源极硅化物18、70、栅极硅化物32、84以及漏极硅化物24、76，如框326中所指示。
沉积层间电介质，如框328中所指示，且使用触点掩模层来形成接触孔，如框330中所指示。如框332中所指示，使用金属1掩模层来沉积并蚀刻第一金属层，在所述第一金属层上沉积金属间电介质，如框334所指示，且使用通路掩模层对金属间电介质进行蚀刻，如框336中所指示。如框338所指示，使用金属2掩模层来沉积并蚀刻第二金属层，随后如框340中所指示，沉积钝化层，使用线接合垫掩模层来通过所述钝化层暴露线接合垫，如框342所指示。(图中未展示由框328到342中所指示的过程形成的结构)。
如图8中所示，使用15个遮蔽层来形成图1A、图1B、图3A和图3B中部分展示的两个金属版本全硅化物互补MOSFET，包含多晶硅电阻器遮蔽层。
图9是在本发明的实施例中用来分别形成图1A、图1B、图3A、图3B、图5A和图5B的互补MOSFET 10、60；134、136以及180、182，以及图2A、图2B、图4A和图4B的互补MOSFET 106、120；以及160、162的主要处理步骤的连续列表350。下表含有对图9的流程表中的框中的每一者所表示的功能的描述。
  方框参考编号   功能
  304   P-型起始晶片
  302   形成P-Epi层
  306   使用N-槽掩模层形成PMOS装置的N-槽
  308   使用场氧化物掩模层形成场氧化物
  309   使用P-阱掩模层形成P-阱
  310   将初始厚栅极氧化物下放于晶片上
  352   使用厚栅极氧化物掩模层移除所界定的薄栅极氧化物区，且接着生长薄栅极氧化物
  312   使用电阻器掩模层下放多晶硅电阻器
  314   使用栅极掩模层形成栅极
  316   使用NMOS缓冲掩模层将P型块缓冲层和N型缓冲层植入NMOS装置中
  318   使用PMOS缓冲掩模层将N型块缓冲层和P型缓冲层植入PMOS装置中
  320   形成栅极侧壁氧化物
 322   使用N+型源极和漏极掩模层将P+源极和漏极植入PMOS装置中
 324   使用P+型源极和漏极掩模层将P+源极和漏极植入PMOS装置中
 326   使用硅化物掩模层形成硅化物区
 328   沉积层间电介质
 330   使用触点掩模层形成层间电介质中的触点开口
 332   使用金属1掩模层形成金属1
 334   沉积金属间电介质
 336   使用通路掩模层打开金属间电介质中的通路
 338   使用金属2掩模层形成金属2
 340   钝化氧化物沉积
 342   使用线接合垫掩模层打开钝化的线接合垫。
所述过程步骤与图8中所示的过程步骤相同，只是多了使用厚栅极氧化物掩模层来生长厚栅极氧化物，如框352中所指示。对于图1A、图1B、图3A、图3B、图5A和图5B的互补MOSFET，使用厚氧化物来形成栅极氧化物，其比框310中所指示的薄氧化物层厚。对于图2A、图2B、图4A和图4B的互补MOSFET，使用框352中所指示的厚栅极氧化物来形成分裂式栅极氧化物114和124的厚侧。
图10是本发明的实施例中用来形成图6和图7中所示的被隔离的NMOS FET的主要处理步骤的连续列表360。下表含有对图10的流程表中的框中的每一者所表示的功能的描述。
  方框参考编号   功能
  304   P-型起始晶片
  362   使用埋入层掩模层形成用于NMOS装置的N埋入层和P-底部层
  302   形成P-Epi层
  306   使用N槽掩模层形成用于PMOS装置的N槽
  364   使用N吸收器掩模层形成用于NMOS装置的N吸收器隔离环
  366   使用场氧化物掩模层形成场氧化物
  309   使用P-阱掩模层形成P-阱
  310   将初始厚栅极氧化物下放于晶片上
  344   使用厚栅极氧化物掩模层移除所界定的薄栅极氧化物区，且接着生长薄栅极氧化物
  312   使用电阻器掩模层下放多晶硅电阻器
  314   使用栅极掩模层形成栅极
  316   使用NMOS缓冲掩模层将P型块缓冲层和N型缓冲层植入NMOS装置中
  318   使用PMOS缓冲掩模层将N型块缓冲层和P型缓冲层植入PMOS装置中
  320   形成栅极侧壁氧化物
  322   使用N+型源极和漏极掩模层将N+源极和漏极植入NMOS装置中
  324   使用P+型源极和漏极掩模层将P+源极和漏极植入PMOS装置中
 326   使用硅化物掩模层形成硅化物区
 328   沉积层间电介质
 330   使用触点掩模层在层间电介质中形成触点开口
 332   使用金属1掩模层形成金属1
 334   沉积金属间电介质
 336   使用通路掩模层打开金属间电介质中的通路
 338   使用金属2掩模层形成金属2
 340   钝化氧化物沉积
 342   使用线接合垫掩模层打开钝化的线接合垫。
如图10中所示，已向图9中的处理步骤添加了使用埋入层掩模层来形成N埋入层286和P-埋入层288(如框362所指示)的额外处理步骤。还添加了添加N吸收器隔离环272(如框364中所指示)的步骤。
图11是标准NMOS装置380的图解视图，标准NMOS装置380具有P+衬底382、P-epi层384以及P阱386，P阱386形成于epi层384中，且延伸到epi层384的上部表面。N+源极和漏极区388和390分别形成于epi层384的上部表面中且位于栅极392的具有栅极侧壁氧化物394和396的相对侧。源极硅化物398、栅极硅化物400、具有漏极硅化物402分别位于源极388、栅极392和漏极390上方。两个浅N低掺杂漏极(LDD)区404和406分别位于栅极侧壁氧化物394和396下方，且分别接触源极388和漏极390。
图12A、图13A、图14A、图15A和图16A展示图1中所示类型的具有0.35微米栅极长度的5伏LV NMOS FET 10的2D模拟Si级操作特性，且图12B、图13B、图14B、图15B和图16B展示图11中所示类型的标准5伏NMOS FET 380的2D模拟Si级操作特性。图12A和图12B展示针对相应的晶体管计算出的漏极特性。如可看出，NMOS FET10与标准NMOS FET 380相比具有较高的漏极电流密度。NMOS FET 10在8V的BVdss下具有0.853mA/微米的峰值2D漏极电流密度，而标准NMOS FET 380也在8V的BVdss下具有0.462mA/微米的峰值漏极电流密度，其表示漏极电流密度增加了85％。图13A和图13B展示针对相应的本征晶体管计算出的频率转变(Ft)。如可看出，NMOS FET 10与标准的NMOS FET 380相比具有较高的Ft。NMOS FET 10具有43GHz的峰值Ft，而标准的NMOS FET 380具有23GHz的峰值Ft，其表示快了1.87倍的Ft。图14A和图14B展示针对相应的本征晶体管计算出的跨导。如可看出，NMOS FET 10与标准NMOSFET 380相比具有较高的跨导。NMOS FET 10具有2.20×10-4西门子的峰值跨导，而标准NMOS FET 380具有1.35×10-4西门子的峰值跨导，其表示跨导增加了63％。
图15A和图15B展示两个装置在栅极氧化物为
Figure G2008800078691D00111
的情况下均具有0.7V的阈值电压。图16A和图16B展示两个装置均具有约8V的BVdss。
图17A到图18C展示图13A中所示类型的MV NMOS FET 134的实验晶体管(ET)数据。图17A到图17C是具有在26.8V的BVdss下具有约24.6mOhm·mm2的Rsp的薄栅极氧化物
Figure G2008800078691D00121
的ET的所测量特性。在图17A中，曲线420展示针对5V的栅极到源极电压(Vgs)而测得的漏极电流对漏极到源极电压的特性，曲线422是针对4V的Vgs，曲线424是针对3V的Vgs，曲线426是针对2V的Vgs，曲线428是针对1V的Vgs，且曲线430是针对0V的Vgs。图17B展示ET的所测量击穿电压特性，且图17C展示ET的所测量阈值电压特性(曲线440)和跨导(曲线424)。
图18A到图18C是具有在22.6V的BVdss下具有约21.8mOhm·mm2的Rsp的厚栅极氧化物
Figure G2008800078691D00122
的ET的所测量特性。在图18A中，曲线450展示针对16V的栅极到源极电压(Vgs)而测得的漏极电流对漏极到源极电压的特性，曲线452是针对14V的Vgs，曲线454是针对12V的Vgs，曲线456是针对10V的Vgs，曲线458是针对8V的Vgs，曲线460是针对6V的Vgs、曲线462是针对4V的Vgs，且曲线464是针对2V的Vgs。图18B展示ET的所测量击穿电压特性，且图18C展示ET的所测量阈值电压特性(曲线470)和跨导(曲线472)。
虽然已参考特定实施例描述了本发明，但所属领域的技术人员将理解，可在不脱离本发明的范围的情况下，作出各种改变，且均等物可代替其元件。另外，在不脱离本发明的范围的情况下可作出许多修改以使特定情形或材料适应本发明的教示。
因此，希望本发明不限于被揭示为预期用于实行本发明的最佳模式的特定实施例，而是本发明将包含处于所附权利要求书的范围和精神内的所有实施例。

Claims (38)

1.一种N沟道MOSFET(NMOS)，其包括：
a)P-外延层，其位于衬底上；
b)源极和漏极，其形成于所述外延层中，且位于栅极的相对侧上，所述栅极位于栅极上，所述栅极位于所述外延层上；
c)第一N型上部缓冲层，其从所述源极下横向延伸到所述外延层的顶部表面处的所述栅极的离所述源极最近的第一边缘与所述栅极的中部之间的位置；
d)第二N型上部缓冲层，其从所述漏极下横向延伸到所述外延层的顶部表面处的所述栅极的离所述漏极最近的第二边缘与所述栅极的所述中部之间的位置；
e)第一P型下部块层，其从所述第一N型缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述源极更靠近所述漏极的位置；以及
f)第二P型下部块层，其从所述第二N型缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述漏极更靠近所述源极的位置，所述第一和第二P型块层在所述栅极下的区中彼此上覆。
2.根据权利要求1所述的NMOS，其中所述栅极氧化物具有多个厚度，以形成分裂式栅极氧化物。
3.根据权利要求2所述的NMOS，其中离所述漏极最近的所述栅极氧化物比离所述源极最近的所述栅极氧化物厚。
4.根据权利要求1所述的NMOS，其中所述源极最接近离所述源极最近的第一栅极侧壁氧化物，且所述漏极且所述漏极最接近离所述漏极最近的第二栅极侧壁氧化物。
5.根据权利要求1所述的NMOS，其中所述源极与所述栅极间隔开。
6.根据权利要求5所述的NMOS，其中所述第一N型上部缓冲层和所述第一P型下部块缓冲层形成所述栅极与所述源极之间的resurf区。
7.根据权利要求5所述的NMOS，其中所述漏极与所述栅极间隔开。
8.根据权利要求7所述的NMOS，其中所述第二N型上部缓冲层和所述第二P型下部块缓冲层形成所述栅极与所述漏极之间的resurf区。
9.根据权利要求1所述的NMOS，其中所述源极与所述栅极间隔开，以形成所述栅极与所述源极之间的resurf区，所述resurf区至少部分地在场氧化物下。
10.根据权利要求1所述的NMOS，其中所述漏极与所述栅极间隔开，以形成所述栅极与所述漏极之间的resurf区，所述resurf区至少部分地在场氧化物下。
11.根据权利要求1所述的NMOS，其进一步包含：
a)N埋入层，其位于所述外延层中，位于所述第一和第二下部块缓冲层下方；
b)P-底部层，其为位于所述N埋入层上方且位于所述第一和第二块区下方的所述外延层；
c)N吸收器环，其围绕所述源极、所述栅极、所述漏极、所述第一和第二上部缓冲层以及所述第一和第二下部块层，所述N埋入层和所述P-底部层延伸到所述N吸收器环的内周边；以及
d)P-阱环，其从所述外延层的所述顶部表面延伸到所述P-底部层；且
e)其中所述源极、所述漏极、所述第一和第二N型上部缓冲层以及所述第一和第二P型下部块层、所述N埋入层和所述P-底部层在所述第一与第二P-阱之间。
12.一种P沟道MOSFET(PMOS)，其包括：
a)P-外延层，其位于衬底上；
b)N-槽，其形成于所述外延层中；
b)源极和漏极，其形成于所述外延层中，且位于栅极的相对侧上，所述栅极位于栅极上，所述栅极位于所述外延层上；
c)第一P型上部缓冲层，其从所述源极下横向延伸到所述外延层的顶部表面处的所述栅极的离所述源极最近的第一边缘与所述栅极的中部之间的位置；
d)第二P型上部缓冲层，其从所述漏极下横向延伸到所述外延层的顶部表面处的所述栅极的离所述漏极最近的第二边缘与所述栅极的中部之间的位置；
e)第一N型下部块缓冲层，其从所述第一N型上部缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述源极更靠近所述漏极的位置；以及
f)第二N型下部块缓冲层，其从所述第二N型上部缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述漏极更靠近所述源极的位置，所述第一和第二N型块层在所述栅极下的区中彼此上覆。
13.根据权利要求12所述的PMOS，其中所述栅极氧化物具有多个厚度，以形成分裂式栅极氧化物。
14.根据权利要求13所述的PMOS，其中离所述漏极最近的所述栅极氧化物比离所述源极最近的所述栅极氧化物厚。
15.根据权利要求12所述的PMOS，其中所述源极最接近离所述源极最近的第一栅极侧壁氧化物，且所述漏极且所述漏极最接近离所述漏极最近的第二栅极侧壁氧化物。
16.根据权利要求12所述的PMOS，其中所述源极与所述栅极间隔开。
17.根据权利要求16所述的PMOS，其中所述第一N型下部块缓冲层和所述第一P型上部缓冲层形成所述栅极与所述源极之间的resurf区。
18.根据权利要求16所述的PMOS，其中所述漏极与所述栅极间隔开。
19.根据权利要求18所述的PMOS，其中所述第二N型下部块缓冲层和所述第二P型上部缓冲层形成所述栅极与所述漏极之间的resurf区。
20.根据权利要求12所述的PMOS，其中所述源极与所述栅极间隔开，以形成所述栅极与所述源极之间的resurf区，所述resurf区至少部分地在场氧化物下。
21.根据权利要求12所述的PMOS，其中所述漏极与所述栅极间隔开，以形成所述栅极与所述漏极之间的resurf区，所述resurf区至少部分地在场氧化物下。
22.一种形成于衬底上的互补N沟道MOSFET(NMOS)与P沟道MOSFET(PMOS)(CMOS)装置对，其包括：
a)NMOS，其包括：
i)P-外延层，其位于所述衬底上；
ii)源极和漏极，其形成于所述外延层中，且位于栅极的相对侧上，所述栅极位于栅极上，所述栅极位于所述外延层上；
iii)第一N型上部缓冲层，其从所述源极下横向延伸到所述外延层的顶部表面处的所述栅极的离所述源极最近的第一边缘与所述栅极的中部之间的位置；
iv)第二N型上部缓冲层，其从所述漏极下横向延伸到最接近于所述外延层的所述顶部表面处的所述栅极的离所述漏极最近的第二边缘的位置；
v)第一P型下部块缓冲层，其从所述第一N型缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述源极更靠近所述漏极的位置；
vi)第二P型下部块缓冲层，其从所述第二N型缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述漏极更靠近所述源极的位置，所述第一和第二P型块层在所述栅极下的区中彼此上覆；
b)PMOS，其包括：
i)N-槽，其形成于所述外延层中；
ii)源极和漏极，其形成于所述外延层中，且位于栅极的相对侧上，所述栅极位于栅极上，所述栅极位于所述外延层上；
iii)第一P型上部缓冲层，其从所述源极下横向延伸到所述外延层的顶部表面处的所述栅极的离所述源极最近的第一边缘与所述栅极的中部之间的位置；
iv)第二P型上部缓冲层，其从所述漏极下横向延伸到最接近于所述外延层的所述顶部表面处的所述栅极的离所述漏极最近的第二边缘的位置；
v)第一N型下部块缓冲层，其从所述第一P型缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述源极更靠近所述漏极的位置；以及
vi)第二N型下部块缓冲层，其从所述第二P型缓冲层下横向延伸到所述外延层的所述顶部表面处的所述栅极下比到所述漏极更靠近所述源极的位置，所述第一和第二N型块层在所述栅极下的区中彼此上覆。
23.一种形成N沟道MOSFET(NMOS)的方法，其包括以下步骤：
a)在P+衬底上生长P-外延层；
b)形成位于所述外延层上的栅极氧化物层；
c)在所述栅极氧化物层上形成栅极；以及
d)在单个遮蔽操作之后，形成与所述栅极的相对侧自对准的两个N型上部缓冲层以及与所述栅极的相对侧自对准的两个P型下部块缓冲层，其每一者位于所述上部缓冲层中的一者下方，所述下部块缓冲层横向延伸经过所述栅极的中部，使得所述两个下部块缓冲区在所述栅极下重叠。
24.根据权利要求23所述的方法，其进一步包含在所述两个上部缓冲区的第一者中形成N+源极且在所述两个上部缓冲区的第二者中形成N+漏极的步骤。
25.根据权利要求24所述的方法，其中所述源极和所述漏极位于所述栅极的相对侧上。
26.根据权利要求23所述的方法，其中将所述栅极氧化物层形成为具有不同厚度。
27.根据权利要求26所述的方法，其中所述漏极位于所述栅极的一侧上，所述侧覆盖所述栅极氧化物的比所述栅极的所述源极的一侧厚的部分。
28.根据权利要求23所述的方法，其进一步包含形成横向围绕所述NMOS的N型隔离环的步骤，所述隔离环从所述衬底延伸到所述外延层的顶部表面。
29.一种形成P沟道MOSFET(PMOS)的方法，其包括以下步骤：
a)在P+衬底上生长P-外延层；
b)在所述外延层中形成N-槽，其延伸到所述外延层的顶部表面；
c)形成位于所述外延上的栅极氧化物层；
d)在所述栅极氧化物层上形成栅极；以及
e)在单个遮蔽操作之后，形成与所述栅极的相对侧自对准的两个P型上部缓冲层以及与所述栅极的相对侧自对准的两个N型下部块缓冲层，其每一者位于所述上部缓冲层中的一者下方，所述下部块缓冲层横向延伸经过所述栅极的中部，使得所述两个下部块缓冲区在所述栅极下重叠。
30.根据权利要求29所述的方法，其进一步包含在所述两个上部缓冲区的第一者中形成P+源极且在所述两个上部缓冲区的第二者中形成P+漏极的步骤。
31.根据权利要求30所述的方法，其中所述源极和所述漏极位于所述栅极的相对侧上。
32.根据权利要求29所述的方法，其中将所述栅极氧化物层形成为具有不同厚度。
33.根据权利要求32所述的方法，其中所述漏极位于所述栅极的一侧上，所述侧覆盖所述栅极氧化物的比所述栅极的离所述源极最近的一侧厚的部分。
34.一种形成互补MOS(CMOS)装置的方法，其包括以下步骤：
a)依据根据权利要求23所述的过程来形成NMOS FET；以及
b)依据根据权利要求29所述的过程来形成PMOS FET，所述N-槽横向延伸越过所述PMOS FET。
35.根据权利要求34所述的方法，其进一步包含在所述NMOS FET中和所述PMOSFET中的所述两个上部缓冲区的第一者中形成源极，且在所述NMOS FET中和所述PMOS FET中的所述两个上部缓冲区的第二者中形成漏极的步骤。
36.根据权利要求35所述的方法，其中所述源极和所述漏极位于所述栅极的相对侧上。
37.根据权利要求34所述的方法，其中将所述栅极氧化物层形成为不同厚度。
38.根据权利要求37所述的方法，其中所述漏极位于所述栅极的一侧上，所述侧覆盖所述栅极氧化物的比所述栅极的离所述源极最近的一侧厚的部分。
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