CN101599462B - Production method of high and low voltage devices based on thin epitaxy - Google Patents

Production method of high and low voltage devices based on thin epitaxy Download PDF

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CN101599462B
CN101599462B CN2009100324156A CN200910032415A CN101599462B CN 101599462 B CN101599462 B CN 101599462B CN 2009100324156 A CN2009100324156 A CN 2009100324156A CN 200910032415 A CN200910032415 A CN 200910032415A CN 101599462 B CN101599462 B CN 101599462B
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buried regions
pipe
inject
disk
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CN101599462A (en
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蒋红利
肖志强
乔明
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WUXI ZHONGWEI MICROCHIPS CO Ltd
WUXI I-CORE ELECTRONICS Co Ltd
University of Electronic Science and Technology of China
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WUXI ZHONGWEI MICROCHIPS CO Ltd
WUXI I-CORE ELECTRONICS Co Ltd
University of Electronic Science and Technology of China
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Abstract

The invention relates to a production method of high and low voltage devices based on thin epitaxy, in particular to an implementation technology of high and low voltage compatibility design and technology for a 600V high voltage LDMOS device, a 20V low voltage device with low cost based on thin epitaxy in which each device is separated. In the invention, 15 block structure layers are used to realize integrated compatibility design of each high and low voltage device. Compared with the traditional power integrated circuit, the difference of the design of each device is that the epitaxy thickness is changed from the thick epitaxy of above 20mu m to the thin epitaxy of 8-9mu m, and double RESURF LDMOS structure without the floating field polar plate is adopted, which can withstand above 700V voltage. In the compatibility design of the high and low voltage device, N is epitaxy for developing an N buried layer and a P buried layer to improve separation generating and voltage voltage collaborating, a P trap and a P buried layer are used for generating pair-communicating separation, and P trap compatibility forms an LDMOS tagma, an NMOS trap region, an NPN tube base region and a voltagestabilizing diode trap region.

Description

High-low voltage device manufacture method based on thin epitaxy
Technical field
The present invention relates to a kind of production method of integrated circuit, specifically a kind of production method of high and low voltage devices based on thin epitaxy.
Background technology
The development of power semiconductor technologies comes from various demands of applications, as the sixties in 20th century to the eighties, be mainly used in industry and electric power system.And recent two decades comes, because 4C industry (Communication, communication; Computer, computer; Consumer, consumer appliances; Developing rapidly Car, automotive electronics), power semiconductor technologies have covered a plurality of military projects, the civil area that is related to the national science and technology development.Power semiconductor has passed through the development of decades, on the device manufacturing technology, improve constantly, from not control the rectifying tube that commutation is turn-offed, the thyristor (SCR) of half control commutation cut-off current type control is the discrete device of representative (DD), develop into grid turn-off thyristor (GTO), high power transistor (GTR), power MOSFET and insulated gate bipolar transistor (IGBT) are the power IC device of representative (PID), develop into intelligent power integrated circuit (SPIC) again, high-voltage power integrated circuit (HVIC) is the power integrated circuit of representative (PIC) stage.Along with further developing and the continuous expansion of application of science and technology level; it is unified that SPIC, HVIC will be tending towards; PIC will be to having higher output voltage, power output, intelligent power model (IPM) development of integrated more function module, more perfect defencive function.
High-voltage power integrated circuit (HVIC), come across later stage nineteen seventies the earliest,, reduced the parts number in the system, interconnecting number and solder joint number because single-chip is integrated, not only improve reliability, the stability of system, and reduced system power dissipation, volume, weight and cost.But because at that time power semiconductor is mainly bipolar transistor SCR, GTO etc., the required drive current of power device is big, drives and the protective circuit complexity, does not make substantial progress in the research of nineteen seventies HVIC.Until the eighties; because mos gate control, Novel MOS class power device such as the appearance of power MOSFET, IGBT etc. with characteristics such as high input impedance, low driving power consumption, easy protections; make drive circuit simple; and easily and power device integrated; just driven the development of HVIC rapidly, but complicated system design and expensive technology cost have limited the application of HVIC.After entering the nineties, the design and craft level of HVIC improves constantly, and the ratio of performance to price improves constantly, and HVIC has progressively entered the practical stage.Existing serial so far HVIC product comes out, comprise the MOS intelligent switch, electric power management circuit, half-bridge or full-bridge inverter, two-phase stepping motor driver, three-phase brushless motor driver, the single-phase chopper of direct current machine, the special-purpose HVIC of PWM, switch integrated regulator etc.The technology trends of HVIC is that operating frequency is higher, voltage is higher, and is more powerful, power consumption is lower and function is more complete.
The main feature of high-voltage power integrated circuit (HVIC) has been integrated high voltage power device, low-voltage signal control and processing, protective circuit etc., and have the high-voltage power fan-out capability.Have many remarkable advantages such as volume is little, in light weight, antijamming capability is strong, reliability is high, long service life, be widely used in civil areas such as motor-driven, frequency control, display driver, Switching Power Supply, communication, automotive electronics, aviation electronics, at military electronic applications, replace equally as being implemented to high-voltage power integrated circuit from discrete device gradually in the modules such as frequency control related in military TT﹠C system, radar system, the microwave telecommunication system, motor-driven, power amplification, power supply.
At present, also to rely on external import in commercial market applications such as display driver, motor-driven, industrial automation, computer power supply, instrument control, consumer electronics.Corresponding application of military field also can only adopt the product of civilian level or technical grade, does not have the product of army's grade to provide substantially.Nonetheless, there are military use such as communication, avionic product also usually to face embargo and stop production, therefore grasp particularly necessary and urgent that core technology with autonomous property right shows for part.The high-performance smart-power IC key technology that exploitation has independent intellectual property right has very great significance to ensureing China's national defense safety.
High-voltage power integrated circuit is integrated high-low voltage devices such as high voltage power device, low-voltage signal control and processing, protective circuit on single-chip.Compare with common low-voltage circuit, the technology more complicated of high-voltage power integrated circuit, device architecture and technological process closely rely on, and have determined the performance parameter of circuit jointly.The research of high-voltage power integrated circuit relates to all many-sides such as device physics, processes and circuit design, its key core technology is difficult to break through, so the high-voltage power integrated circuit product is captured by several well-known integrated device manufacturing (IDM) manufacturers in the world basically.The update of high-voltage power integrated products is slow with respect to digital IC, added value is high, and as the core technology secret, each IDM manufacturer all holds in close confidence its technological process, device model, device architecture etc.
In order to satisfy the withstand voltage demand improve constantly, at present, most of in the world IDM manufacturer adopts the CD or the BCD technology of thick epitaxial material on high resistivity substrate (epitaxial thickness is 20um) more.Mainly adopted the CD process design technology of high-low pressure compatibility as the serial 600V high pressure grid-driving integrated circuit of IR company, epitaxy layer thickness is more than the 20um, what the 600V high voltage structures adopted is the LDMOS structure of the floating barnyard pole plate (Poly2) of band of 600V, IR company is based on the technology of oneself researching and developing, complex process, the photoetching technique of counterpoint of externally delaying has proposed higher requirement, processing and manufacturing difficulty for domestic process unit.The traditional thick epitaxy technology exists process heat process time length, knot to isolate big, the thick outer deficiencies such as photo-etching mark is fuzzy of delaying of horizontal proliferation simultaneously.
And the serial 600V high-voltage power integrated circuit that Fairchild company releases has adopted the BCD process design technology based on 600V high-low pressure compatibility on about 7um thin epitaxy material, and body silicon high-voltage technology and SOI high-pressure process are arranged.Processing line based on oneself realizes, complex process, and cost is higher.
Except the processing line of each IDM manufacturer oneself, Foundry line such as X-FAB, the TSMC etc. of each standard just progressively release 700V high-low pressure BCD compatible technology at present, develop based on the processing line about 1um, these technologies all adopt the above thick epitaxy technique of 20um, and the 600V high voltage structures adopts LDMOS device or VDMOS device.Complex process, cost is higher, and specific aim is not strong, and is not very ripe, is is also researching and developing and continuing to optimize improvement.
Goal of the invention
The objective of the invention is to design a kind of production method of high and low voltage devices based on thin epitaxy, this method is produced the 600V high-voltage driving circuit on the processing line at home, requirement realizes the compatibility design of 600V high tension apparatus and devices such as 20V low voltage CMOS, NPN device and 5～6V voltage-stabiliser tube in an integrated circuit, guarantee the circuit reliability energy, and production cost is low, process stabilizing is controlled, be suitable for domestic processing line produces in batches, thereby can be used in the design and the manufacturing of 600V high-voltage power integrated circuit.
As requested, the present invention is based on the thin epitaxy of 8～9um and carry out manufacturing and designing of 600V high-voltage power integrated circuit, the 600V high tension apparatus has adopted double buffering (RESURF) lateral direction bilateral diffusion MOS pipe (LDMOS) structure of the floating barnyard pole plate (NFFP) of nothing of band high pressure interconnection line (HVI) to design, each low-voltage device accomplishes compatible design as far as possible, and technology realizes based on designing and developing on the domestic 3um standard technology line.
According to technical scheme provided by the invention, the manufacture method of described high-low voltage device based on thin epitaxy comprises the steps:
Step 1, material are prepared: choose P type＜100〉the P-substrate in crystal orientation, as disk;
Step 2, the formation of P buried regions and N buried regions: growth one deck thermal oxide layer and deposit one deck silicon nitride are as injecting screen on disk, carry out the photoetching of P buried regions again and inject, utilize photoresist to do the locality protection of barrier layer, inject boron difluoride in the zone that the P buried regions is arranged with non-P buried regions; On disk, carry out the photoetching of N buried regions after removing photoresist and inject, utilize photoresist to do the locality protection of barrier layer, inject arsenic, carry out the annealing of P buried regions and N buried regions again in the zone that the N buried regions is arranged with non-N buried regions;
Step 3, the growth of N-extension: the region growing field oxide of non-P buried regions and non-N buried regions is done to stop the thermal oxide layer of growing then above P buried regions and N buried regions on disk; Afterwards at whole wafer superficial growth N-epitaxial loayer;
Step 4, a formation of layer falls in P trap and P: carry out the photoetching of P trap and inject on disk, utilize photoresist to do the locality protection of barrier layer with non-P trap, inject B in the zone that the P trap is arranged 11Ion doping; On disk, carry out the photoetching injection that a layer falls in P then, utilize photoresist to do the barrier layer locality protection of layer is fallen in non-P, having P to fall the zone injection B of a layer 11Ion doping carries out the knot that layer falls in P trap and P again, makes to be infused in the P trap and a B of layer falls in P 11The ionic impurity diffusion forms dark P trap and dark P and falls a layer;
Step 5, N pipe notes and the formation of annotating of P pipe: on disk, carry out the photoetching that annotate N pipe field, utilize photoresist to do the barrier layer with a non-N pipe locality protection of annotating, a N pipe zone of annotating an injection B ion doping is being arranged, carry out a N pipe notes knot then, make to be infused in the B ionic impurity diffusion that annotate N pipe field, form a dark N pipe notes; On disk, carry out the photoetching of annotating of P pipe then: utilize photoresist to do the barrier layer with a non-P pipe locality protection of annotating, a P pipe zone of annotating an injection P ion doping is being arranged, carry out a P pipe notes knot then, make to be infused in the P ionic impurity diffusion that annotate P pipe field, form dark P and manage a notes;
Step 6, the formation of active area: at whole wafer superficial growth one deck thermal oxide layer and deposit one deck silicon nitride masking layer as active area, be the chemical wet etching of active area then, utilize photoresist that active area is protected, the employing dry method is carried out etching with the silicon nitride of non-active area, then at the place of non-active area growth field oxide;
Step 7, the formation of grid oxygen: utilize the field oxide of non-active area to do to stop that erode whole thermal oxide layers and silicon nitride layer above the active area, the thermal oxide layer of growing again forms pre-grid oxygen on active area, erode whole silicon dioxide again, regrowth one deck thermal oxide layer is as grid oxygen;
Step 8, the formation of polysilicon: be deposited on the whole wafer surface with low-pressure vapor phase and form polysilicon layer, carry out the photoetching of polysilicon, utilize photoresist that the locality protection of polysilicon will be arranged, utilize dry etching to remove the polysilicon of no photoresist protection zone, form polysilicon gate and polycrystalline interconnection line figure;
Step 9, the lightly doped formation of N-light dope and P-: on disk, carry out the photoetching of N-light dope and inject, utilize photoresist to do the barrier layer, inject the P ion doping in the zone that the N-light doping section is arranged with the lightly doped locality protection of non-N-; Carrying out the lightly doped photoetching of P-then on disk injects, utilize photoresist to do the barrier layer with the lightly doped locality protection of non-P-, there being the lightly doped zone of P-to inject the B ion doping, carry out the knot that light dope injects again, make to be infused in N-light dope and the lightly doped ionic impurity diffusion of P-;
Step 10, the highly doped and highly doped formation of P+ of N+: on disk, carry out the highly doped photoetching of N+ and inject, utilize photoresist to do the barrier layer locality protection that non-N+ is highly doped, having the highly doped zone of N+ to inject the P ion doping; On disk, carry out the highly doped photoetching of P+ then and inject, utilize photoresist to do the barrier layer locality protection that non-P+ is highly doped, the area B ion doping of the highly doped injection of P+ is being arranged.
In described step 1, described material is P type＜100〉the P-substrate 1 of crystal orientation 75-130 Ω cm.
In described step 2, the described thermal oxide layer of growth one deck 36～44nm and the described silicon nitride of deposit one deck 135～165nm on described disk.
In described step 3, the field oxide of the region growing 620～680nm of non-P buried regions and N buried regions on described disk; 36～44nm thermal oxide layer of above P buried regions and N buried regions territory, growing; At the N-epitaxial loayer of whole wafer superficial growth 8～9um, concentration is 2E15cm-3, withstand voltage with the lateral direction bilateral diffusion MOS tube device that guarantees 600V.
In step 6, at whole wafer superficial growth one deck 54～66nm thermal oxide layer and deposit one deck 180～220nm silicon nitride masking layer as active area; Field oxide at the place of non-active area growth 1300～1500nm.
In step 7, erode 70～90nm silicon nitride layer above the active area, the thermal oxide layer of the 70～90nm that grows on active area again forms pre-grid oxygen; The thermal oxide layer of growth 70～90nm is as grid oxide layer.
Characteristics of the present invention are as follows:
(1) device of the present invention designs based on 8～9um N-thin epitaxy of growing on the P-substrate, reducing the requirement to mask aligner, and has reduced horizontal proliferation.
(2) device of the present invention and architectural feature, isolation structure between voltage stabilizing didoe tube device that it is 5～6V that the device that comprises among the present invention has 600V pair of RESURFLDMOS device, 20V low voltage CMOS device, 20V low voltage dipole NPN device, voltage stabilizing and high-low voltage device, independent epi island has adopted minimum level to realize the integrated compatible design of each device.
LDMOS tubular construction: adopted double buffering (RESURF) lateral direction bilateral diffusion MOS pipe (LDMOS) structure of not having floating barnyard pole plate (NFFP) to design, mainly by the P-the field oxide of drain region under fall layers 6 and N-extension 2 formed two REUSRF structures, the polycrystalline grid are done the grid field plate.
Each device architecture of low pressure: withstand voltage for the 20V that guarantees low-voltage device, the emitter of the drain terminal of nmos device, NPN device has adopted N-light doping section 11 to form, and the drain terminal of nmos device has adopted P-light doping section 12 to form.
The compatible design of each device: P trap 5 is used to form the tagma of LDMOS, the well region of NMOS, the base of NPN pipe simultaneously, the well region of voltage stabilizing didoe, and P trap 5 has also formed one by one independently epi island with 3 pairs of logical isolation of P buried regions simultaneously.
(3) technology of device architecture realizes among the present invention, based on increasing on single polycrystalline list aluminium (SPSM) CMOS of the standard 3um technology basis and adjusting that some levels realize.Process using P type＜100〉the P-backing material of crystal orientation 75-130 Ω cm, at first photoetching is successively injected boron difluoride and arsenic to form P buried regions 3 and N buried regions 4 respectively on P-substrate 1; On disk, grow the again N-type extension 2 of 8～9 μ m; Twi-lithography injects boron, pushes away that trap forms P trap 5 respectively and a layer 6 falls in P-; On disk, carry out the photoetching injection that N manages field notes 7 and a P pipe notes 8 then, the conventional selective oxidation silicon technology (LOCOS technology) of employing is formed with the field oxide 21 on source region 9 and the non-active area, and the growth thermal oxide layer forms the gate oxide 20 of 70～90nm on active area 9; Deposit polysilicon and photoetching corrosion form polysilicon layer 10 again, successively carry out the photoetching of N-light dope 11, P-light dope 12 afterwards and inject on disk, carry out that N+ is highly doped 13, the photoetching of P+ highly doped 14 is injected again.Being contact hole, aluminum steel photoetching corrosion and the passivation hole perforate formation in the common process at last, is to guarantee the withstand voltage and power device overcurrent capability of high-voltage LDMOS pipe, and dielectric layer and aluminum steel layer are thicker than common process.
Advantage of the present invention is: 1, the present invention is based on the thin epitaxy of 8～9um, with respect to thick epitaxy technology more than traditional 20um, help reducing to the requirement of mask aligner and the horizontal proliferation that reduces to finish; 2, based on the LDMOS structure and low pressure NMOS structure ratio of thin epitaxy, only increasing P-falls layer and has promptly reached requirement of withstand voltage, tradition LDMOS structure needs to increase floating barnyard pole plate (Poly2) again and reaches withstand voltage purpose, LDMOS of the present invention is simple in structure, required level is minimum, withstand voltage having reached more than the 700V, low pressure each more than the device withstand voltage 30V; 3, the compatibility of each device architecture of the present invention is very high, same level obtains utilizing at a plurality of devices, reduces technology cost and process complexity as far as possible, and process stabilizing is controlled, the batch process of suitable high-voltage power integrated circuit, technology mask release of the present invention has 15 versions; 4, structure of the present invention can be used in the design of 600V high-voltage power integrated circuit, and level is simple, the reliability height.
Description of drawings
Fig. 1 a is a 600V high-voltage LDMOS device structural representation on the thin epitaxy.
Fig. 1 b is a 600V high-voltage LDMOS device section of structure on the thin epitaxy.
Fig. 2 a is a 20V NMOS structural representation.
Fig. 2 b is a 20V PMOS structural representation.
Fig. 3 is a 20V NPN structural representation.
Fig. 4 is a 5.3V voltage stabilizing didoe structural representation.
Fig. 5 is the isolation structure schematic diagram between independent island.
Fig. 6 is the schematic diagram of the compatible design of all devices.
Each digital implication explanation among the figure: 1:P-substrate.The 2:N-extension.The 3:P buried regions.The 4:N buried regions.5:P trap layer.A layer falls in 6:P-.A 7:N pipe notes.A 8:P pipe notes.10: polysilicon.The 11:N-light dope.The 12:P-light dope.13:N+ is highly doped.14:P+ is highly doped.16: the metal aluminium lamination.20: gate oxide.21: field oxide.The grid exit of 30:LDMOS pipe.The source electrode exit of 31:LDMOS pipe.The drain electrode exit of 32:LDMOS pipe.33: the negative pole exit of voltage stabilizing didoe.34: the anodal exit of voltage stabilizing didoe.35: the base terminal of bipolar NPN pipe.36: the emitter exit of bipolar NPN pipe.37: the collector terminal of bipolar NPN pipe.The grid exit of 38:NMOS pipe.The source electrode exit of 39:NMOS pipe.The drain electrode exit of 40:NMOS pipe.The grid exit of 41:PMOS pipe.The source electrode exit of 42:PMOS pipe.The drain electrode exit of 43:PMOS pipe.
Embodiment
1, based on each high-low voltage device structure of thin epitaxy
(1) 600V LDMOS device architecture
Profile as shown in Figure 2, the LDMOS tubular construction has adopted double buffering (RESURF) lateral direction bilateral diffusion MOS pipe (LDMOS) structure of not having floating barnyard pole plate (NFFP) to design.Withstand voltage for guaranteeing, directly form at drain terminal by the N-extension 2 on the independent island, there is P-under field oxide to fall a layer 6 on the N-extension and N-extension 2 has formed two REUSRF structures, the drain terminal exit has N+, there is polycrystalline to surround around the N+, and polycrystalline is across crossing gate oxide 20 and field oxide 21, and the drain terminal contact hole is connected across on N+ and the polycrystalline simultaneously, draws the drain terminal exit 32 that forms the LDMOS pipe by metal aluminium lamination 16 then; The tagma of LDMOS pipe is made in the P trap 5 on the N-extension, across crossing the grid that gate oxide 20 and field oxide 21 have formed the field plate structure, draws the grid end exit 30 that forms the LDMOS pipe by contact hole on the polycrystalline grid and aluminum steel by polycrystalline again; The source end is highly doped 13 by N+, P+ highly doped 14 directly receives together, and N+ is highly doped, P+ is highly doped also has a N pipe notes 7 down in order to reduce the volume resistance of LDMOS pipe, end in contact hole, source is connected across simultaneously that N+ is highly doped, highly doped the going up of P+ forms butt hole, draws the source end exit 31 that forms the LDMOS pipe by the metal aluminium lamination.
(2) low voltage CMOS structure
Profile as shown in Figure 2, wherein Fig. 2 a is low pressure NMOS pipe, drain terminal is formed by the N-light doping section 11 in the P trap 5 and punctures withstand voltage to improve NMOS pipe drain terminal, drain terminal exit 40 is formed by the N+ on the N-light doping section 11 highly doped 13, source end exit 39 is highly doped 13 by the N+ in the P trap 5, highly doped 14 butt joints of P+ form, and also has the N pipe to annotate 7 volume resistances in order to reduction NMOS pipe below the P+ highly doped 14; Fig. 2 b is low pressure PMOS pipe, drain terminal is formed by the P-light doping section 12 on the N-extension 2 and punctures withstand voltage to improve PMOS pipe drain terminal, drain terminal exit 43 is formed by the P+ on the P-light doping section 12 highly doped 14, source end exit 42 is highly doped 14 by the P+ on the N-extension 2, highly doped 13 butt joints of N+ form, and also has the P pipe to annotate 8 volume resistances in order to reduction PMOS pipe below the N+ highly doped 13.The grid exit 38 of NMOS pipe, PMOS pipe, the grid exit 41 of PMOS pipe is formed by polycrystalline 10.8 isolation that are used to form between the low voltage CMOS device are annotated in a N pipe notes 7, P pipe field, to improve a field cut-in voltage, improve the anti-breech lock ability of device,
(3) bipolar NPN structure
Profile as shown in Figure 3, adopt vertical NPN structure, collector electrode directly is made of N-extension 2, current collection exit 37 is formed by the N+ on the N-extension 2 highly doped 13, also have a P pipe notes 8 below the N+ highly doped 13 in order to reduce collector resistance, the base is formed by P trap 5, base terminal 35 is formed by the P+ on the P trap 5 highly doped 14, also have a N pipe notes 7 below the P+ highly doped 14 in order to reduce base resistance, emitter is formed by N-light doping section 11, emitter exit 36 is formed by the N+ on the N-light doping section 11 highly doped 13, and N-light doping section 11 is in order to improve the withstand voltage of NPN pipe.
(4) voltage stabilizing didoe structure
Profile as shown in Figure 4, the voltage stabilizing didoe positive pole is annotated 7 by the pipe of the N in the P trap 5 and is formed, anodal exit 34 is formed by a N pipe P+ highly doped 14 that annotate above 7, voltage stabilizing didoe negative pole and negative pole exit 33 are formed by the N+ highly doped 13 on the N pipe field notes 7.
(5) isolation structure between each independent island
Profile is formed up and down by P buried regions 3 on the P-substrate 1 and P trap 5 and to isolate logical as shown in Figure 5, makes P buried regions 3 link to each other with P-substrate 1, and to form one by one independently epi island, the isolation structure contact is drawn by P trap 5 interior P+ highly doped 14 and formed.
The whole compatible project organization schematic diagram of device is as shown in Figure 6 in the 600V high-voltage power integrated circuit of Xing Chenging at last.
2, based on thin epitaxy each the height device making method
Be the main technique flow process that compatible device forms below, correspondence forms each device level as shown in Figure 6, and feature is as follows:
Step 1, material are prepared: choose P type＜100〉the P-substrate 1 of crystal orientation 75-130 Ω cm, as disk;
Step 2; P buried regions 3 and N buried regions 4 form: growth one deck 36～44nm thermal oxide layer and deposit one deck 135～165nm silicon nitride are as injecting screen on P-substrate 1; carrying out the photoetching of P buried regions 3 again injects; utilize photoresist to do the barrier layer non-P buried regions 3 is protected, inject boron difluoride BF at P buried regions 3 2On disk, carry out the photoetching of N buried regions 4 after removing photoresist and inject, utilize photoresist to do the barrier layer non-N buried regions 4 is protected, inject arsenic As, carry out buried regions annealing again at N buried regions 4.
Step 3, N-extension 2 growth: the field oxide of the region growing 620～680nm of non-P buried regions and N buried regions is done to stop on disk, 36～44nm thermal oxide layer of growing above P buried regions 3 and N buried regions 4 are the zone then; At the N-epitaxial loayer 2 of whole wafer superficial growth 8～9um, concentration is 2E15cm-3 afterwards, withstand voltage with lateral direction bilateral diffusion MOS pipe (LDMOS) device that guarantees 600V.
Step 4, P trap 5 and P fall a layer 6 and form: carry out 5 photoetching of P trap and inject on disk, utilize photoresist to do the barrier layer non-P trap 5 is protected, inject B in the zone of P trap 5 11Ion doping; On disk, carry out the photoetching that layer 6 falls in P then and inject, utilize photoresist to do the barrier layer and a layer 6 is fallen in non-P protect, fall a layer 6 at P and inject B 11Ion doping carries out the knot that layer 6 falls in P trap 5 and P again, makes to be infused in P trap 5 and a B of layer 6 falls in P 11The ionic impurity diffusion forms dark P trap 5 and dark P and falls a layer 6.
Step 5, N pipe notes 7 and P pipe field are annotated 8 and are formed: carry out N and manage a photoetching of notes 7 on disk, utilizing photoresist to do the barrier layer protects a non-N pipe notes 7, inject the B ion dopings at a N pipe notes 7, carry out N pipe notes 7 knot then, make the B ionic impurity diffusion that is infused in N pipe field notes 7, form a dark N pipe notes; On disk, carry out the photoetching of a P pipe notes 8 then; utilize photoresist to do the barrier layer a non-P pipe notes 8 are protected, annotate 8 in P pipe field and inject the P ion doping, carry out P then and manage notes 8 knot; make the P ionic impurity diffusion that is infused in P pipe field notes 8, form a dark P pipe notes.
Step 6; active area 9 forms: at whole wafer superficial growth one deck 54～66nm thermal oxide layer and the deposit one deck 180～220nm silicon nitride masking layer as active area; be the chemical wet etching of active area 9 then; utilize photoresist that active area 9 is protected; the employing dry method is carried out etching with the silicon nitride of non-active area, the field oxide 21 of the 1300～1500nm that grows in the place of non-active area then.
Step 7, grid oxygen 20 forms: utilize the field oxide of non-active area to do to stop, erode whole thermal oxide layers and 70～90nm silicon nitride layer above the active area 9, the thermal oxide layer of growth 70～90nm forms pre-grid oxygen on active area 9 again, erodes whole silicon dioxide SiO again 2, the thermal oxide layer of growth 70～90nm is as grid oxide layer 20.
Step 8, the formation of polysilicon 10: be deposited on the whole wafer surface with low-pressure vapor phase and form polysilicon layer, carry out the photoetching of polysilicon 10, utilize photoresist that multi-crystal silicon area is protected, utilize dry etching to remove the polysilicon of no photoresist protection zone, form polysilicon gate and polycrystalline interconnection line figure;
Step 9, N-light doping section 11 and P-light doping section 12 form: carry out 11 photoetching of N-light doping section and inject on disk, utilize photoresist to do the barrier layer non-N-light doping section is protected, inject the P ion doping at N-light doping section 11; Carrying out the photoetching of P-light doping section 12 then on disk injects; utilizing photoresist to do the barrier layer protects non-P-light doping section; inject the B ion doping at P-light doping section 12, carry out the knot that light dope injects again, make to be infused in N-light doping section and the diffusion of P-light doping section ionic impurity.
Step 10, N+ highly doped 13 and P+ highly doped 14 forms: carry out highly doped 13 photoetching of N+ and inject on disk, utilize photoresist to do the barrier layer and protect non-N+ is highly doped, at the highly doped injection of N+ P ion doping; On disk, carry out the photoetching of P+ highly doped 14 then and inject, utilize photoresist to do the barrier layer and protect non-P+ is highly doped, at the highly doped injection of P+ B ion doping.
Utilize contact hole, aluminum steel photoetching corrosion and the perforate of passivation hole in the common process to form at last, for guaranteeing the withstand voltage and power device overcurrent capability of high-voltage LDMOS pipe, dielectric layer and aluminum steel layer are thicker than common process, before-metal medium layer thickness is 1630～1770nm, and aluminum steel thickness is 1620～1980nm.
Technological achievement of the present invention and application.Each device withstand voltage and electrical quantity performance are up to standard among the present invention, and wherein the LDMOS pipe is withstand voltage is about 780V, and low pressure NMOS manages about withstand voltage 36V, and low pressure PMOS manages more than the withstand voltage 40V, and bipolar NPN manages about withstand voltage 36V, and voltage stabilizing didoe voltage stabilizing value is 5.3V.The compatible design of each device is good in this invention, and all structures are used for the design of high-voltage power integrated circuit, and total mask release is 15 versions.
The technology of the present invention is mainly used in and is integrated with 600V high tension apparatus, 30V designing and developing with the high-voltage power integrated circuit of interior low voltage CMOS, twin-stage NPN or 5.3V voltage-stabiliser tube simultaneously, we utilize this invention art designs to go out three sample, the IR2103 of the compatible IR of difference company, IR2110, the IR2111 circuit, carry out the flow manufacturing on 58 3um processing lines at home, the compatible raw sample circuit of the every key parameter index of the circuit that flow goes out.
Utilize the present invention can develop more 600V high-voltage power integrated circuit product.

Claims (1)

1. manufacture method based on the high-low voltage device of thin epitaxy is characterized in that:
Step 1, material are prepared: choose P type＜100〉the P-substrate (1) in crystal orientation, as disk;
Step 2, the formation of P buried regions (3) and N buried regions (4): growth one deck thermal oxide layer and deposit one deck silicon nitride are as injecting screen on disk, carrying out the photoetching of P buried regions (3) again injects, utilize photoresist to do the locality protection of barrier layer, inject boron difluoride in the zone that P buried regions (3) is arranged with non-P buried regions; On disk, carry out the photoetching of N buried regions (4) after removing photoresist and inject, utilize photoresist to do the locality protection of barrier layer, inject arsenic, carry out the annealing of P buried regions (3) and N buried regions (4) again in the zone that N buried regions (4) is arranged with non-N buried regions;
Step 3, the growth of N-extension (2): the region growing field oxide of non-P buried regions and non-N buried regions is done to stop on disk, then at the top of P buried regions (3) and N buried regions (4) growth thermal oxide layer; Afterwards at whole wafer superficial growth N-epitaxial loayer (2);
Step 4, a formation of layer (6) falls in P trap (5) and P: carry out P trap (5) photoetching and inject on disk, utilize photoresist to do the locality protection of barrier layer with non-P trap, inject B in the zone that P trap (5) is arranged 11Ion doping; On disk, carry out the photoetching injection that a layer (6) falls in P then, utilize photoresist to do the barrier layer locality protection of layer is fallen in non-P, having P to fall the zone injection B of a layer (6) 11Ion doping carries out the knot that layer (6) falls in P trap and P again, makes to be infused in the P trap and a B of layer falls in P 11The ionic impurity diffusion forms dark P trap (5) and dark P and falls a layer (6);
Step 5, the formation of (8) is annotated in N pipe notes (7) and P pipe field: carry out the photoetching that (7) are annotated in N pipe field on disk, utilize photoresist to do the barrier layer with a non-N pipe locality protection of annotating, inject the B ion doping in the zone that a N pipe notes (7) are arranged, carry out N pipe notes (7) knot then, make to be infused in the B ionic impurity diffusion that (7) are annotated in N pipe field, form a dark N pipe notes (7); On disk, carry out the photoetching of a P pipe notes (8) then: utilize photoresist to do the locality protection that (8) are annotated non-P pipe field on the barrier layer, inject the P ion doping in the zone that a P pipe notes (8) are arranged, carry out P pipe notes (8) knot then, make to be infused in the P ionic impurity diffusion that (8) are annotated in P pipe field, form a dark P pipe notes (8);
Step 6, the formation of active area (9): at whole wafer superficial growth one deck thermal oxide layer and deposit one deck silicon nitride masking layer as active area (9), be the chemical wet etching of active area (9) then, utilize photoresist that active area (9) is protected, the employing dry method is carried out etching with the silicon nitride of non-active area, then at the place of non-active area growth field oxide (21);
Step 7, the formation of grid oxygen (20): utilize the field oxide (21) of non-active area to do to stop, erode whole thermal oxide layers and silicon nitride layer above the active area (9), the thermal oxide layer of growing on active area (9) forms pre-grid oxygen again, erode whole silicon dioxide again, regrowth one deck thermal oxide layer is as grid oxygen (20);
Step 8, the formation of polysilicon (10): be deposited on the whole wafer surface with low-pressure vapor phase and form polysilicon layer, carry out the photoetching of polysilicon (10), utilize photoresist that the locality protection of polysilicon (10) will be arranged, utilize dry etching to remove the polysilicon (10) of no photoresist protection zone, form polysilicon gate and polycrystalline interconnection line figure;
Step 9, the formation of N-light dope (11) and P-light dope (12): on disk, carry out N-light dope (11) photoetching and inject, utilize photoresist to do the barrier layer, inject the P ion doping in the zone that N-light doping section (11) is arranged with the lightly doped locality protection of non-N-; Carrying out the photoetching of P-light dope (12) then on disk injects, utilize photoresist to do the locality protection of barrier layer with non-P-light dope (12), inject the B ion doping in the zone that P-light dope (12) is arranged, carry out the knot that light dope injects again, make the ionic impurity diffusion that is infused in N-light dope (11) and P-light dope (12);
Step 10, N+ highly doped (13) and P+ highly doped (14) form: carry out N+ highly doped (13) photoetching and inject on disk, utilize photoresist to do the barrier layer locality protection that non-N+ is highly doped, inject the P ion doping in the zone that N+ highly doped (13) is arranged; On disk, carry out the photoetching of P+ highly doped (14) then and inject, utilize photoresist to do the barrier layer locality protection that non-P+ is highly doped, at the area B ion doping that has P+ highly doped (14) to inject;
And in step 1, described material is P type＜100〉the P-substrate (1) of crystal orientation 75-130 Ω cm;
In step 2, the described thermal oxide layer of growth one deck 36～44nm and the described silicon nitride of deposit one deck 135～165nm on described disk;
In described step 3, the field oxide of the region growing 620～680nm of non-P buried regions and N buried regions on described disk; 36～44nm thermal oxide layer of above P buried regions and N buried regions territory, growing; At the N-epitaxial loayer (2) of whole wafer superficial growth 8～9um, concentration is 2E15cm-3, withstand voltage with the lateral direction bilateral diffusion MOS tube device that guarantees 600V;
In described step 6, at whole wafer superficial growth one deck 54～66nm thermal oxide layer and deposit one deck 180～220nm silicon nitride masking layer as active area; Field oxide (21) at the place of non-active area growth 1300～1500nm;
In described step 7, erode 70～90nm silicon nitride layer above the active area (9), the thermal oxide layer of the 70～90nm that grows on active area again forms pre-grid oxygen; The thermal oxide layer of growth 70～90nm is as grid oxide layer (20).
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* Cited by examiner, † Cited by third party
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CN102005480B (en) * 2010-10-28 2012-05-09 电子科技大学 High-voltage low-on-resistance LDMOS device and manufacturing method thereof
CN102569084B (en) * 2010-12-16 2014-04-16 北大方正集团有限公司 P-type high-concentration doped silicon and technology for preparing P-channel MOS (Metal Oxide Semiconductor) pipe of BCD products
CN102184944B (en) * 2011-04-29 2013-01-02 南京邮电大学 Junction terminal structure of lateral power device
CN102983162A (en) * 2011-09-05 2013-03-20 旺宏电子股份有限公司 Semiconductor device and manufacturing method thereof
US9214457B2 (en) 2011-09-20 2015-12-15 Alpha & Omega Semiconductor Incorporated Method of integrating high voltage devices
CN102496624B (en) * 2011-12-27 2014-02-12 上海先进半导体制造股份有限公司 Integrated floating basin isolation structure in high voltage BCD technology
CN104282549B (en) * 2013-07-03 2018-12-04 无锡华润上华科技有限公司 A kind of guard method of backside structure
CN103413830B (en) * 2013-08-16 2016-08-31 电子科技大学 A kind of laterally high-voltage MOSFET and manufacture method thereof
CN103972064B (en) * 2014-05-26 2017-01-11 上海先进半导体制造股份有限公司 Technique for inhibiting self doping of P-type impurities in epitaxial process of silicon with P-type buried layer
CN105405887A (en) * 2014-09-11 2016-03-16 北大方正集团有限公司 Semiconductor device
CN105161538A (en) * 2015-08-07 2015-12-16 电子科技大学 Transverse high-pressure device and manufacturing method thereof
CN110120423B (en) * 2019-05-05 2022-03-22 南京邮电大学 LDMOS device and preparation method thereof
CN111785634B (en) * 2020-06-30 2024-03-15 上海华虹宏力半导体制造有限公司 LDMOS device and process method
CN113410232A (en) * 2021-06-15 2021-09-17 西安微电子技术研究所 CMOS integrated circuit chip for inhibiting latch-up effect and preparation process thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359664A (en) * 2007-07-31 2009-02-04 上海贝岭股份有限公司 N type LDMOS device in BCD process, layout making and manufacturing method
CN101452933A (en) * 2008-12-30 2009-06-10 电子科技大学 BCD semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359664A (en) * 2007-07-31 2009-02-04 上海贝岭股份有限公司 N type LDMOS device in BCD process, layout making and manufacturing method
CN101452933A (en) * 2008-12-30 2009-06-10 电子科技大学 BCD semiconductor device and manufacturing method thereof

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
乔明 等.基于薄外延技术的高压BCD兼容工艺.《半导体学报》.2007,第28卷(第11期),1742-1747.
乔明.基于高低压兼容工艺的高压驱动集成电路.中国博士学位论文全文数据库.2008,正文2页7-11行，52页最后一行-53页第5行、表3-2、附图1-1（a）. *
乔明等.基于薄外延技术的高压BCD兼容工艺.《半导体学报》.2007,第28卷(第11期),1742-1747. *

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