Summary of the invention
Technical problem to be solved by this invention provides a kind of wireless baseband chips in base station side testing apparatus and method, can solve to adopt conventional test methodologies to be difficult to judge the problem that whether normal chip operation to be measured is according to the system test result.
In order to solve the problems of the technologies described above, the invention provides a kind of testing apparatus of wireless baseband chips in base station side, comprise interconnective chip to be measured and controller unit; Wherein:
Chip to be measured is used for the measurand as up reliability testing;
Controller unit, be used to control the generation time point of the uplink antenna data flow of chip to be measured, and in correct time window up running parameter of chip configuration to be measured and generation uplink antenna data flow, by inquiring about the state of chip to be measured, and the up result of reading chip output to be measured, and up result and up reference result compared, judge the correctness of the up result of chip to be measured.
Further,
Chip to be measured is used for the measurand as descending reliability testing;
Controller unit, be used to control the acquisition time point of the uplink/downlink antenna data flow of chip to be measured, in correct time window, be the chip configuration downlink working parameter to be measured and the uplink/downlink antenna data flow of gathering chip to be measured, and uplink/downlink antenna data flow and the descending reference result who gathers compared, and the downlink working state of inquiring about chip to be measured, judge chip downlink processing result's to be measured correctness.
Further, controller unit comprises main control unit and the control unit of falling forward, wherein:
Fall forward and control the unit, be connected with chip to be measured and main control unit respectively, be used under the control of main control unit, the data from main control unit that receive are preserved, and export the uplink antenna data flow to chip to be measured at the time point of appointment; Perhaps, at the appointed time put from chip to be measured and gather the uplink/downlink antenna data flow, judging downlink processing result's correctness, and the judged result of downlink processing is preserved;
Main control unit is used for respectively fall forward control unit and chip to be measured are carried out parameter configuration and status poll, writes the uplink antenna data of digital baseband antenna to the control unit of falling forward, and as up test and excitation usefulness, and reads the uplink antenna data from the control unit of falling forward; And the correctness of judging line output on the chip to be measured; Perhaps, write the uplink/downlink antenna data of digital baseband antenna,, and read the judged result of downlink processing from the control unit of falling forward as descending reference usefulness as a result to the control unit of falling forward.
Further, the control unit of falling forward is field programmable logic array FPGA, and main control unit is a processor; Wherein, processor is a processor physically, or a plurality of processor, and a plurality of processors are of the same type or dissimilar.
Further, FPGA contains the memory unit access controller, hangs with memory cell under the FPGA, is used under the control of memory unit access controller the data space as FPGA; Hang with memory cell under the processor, be used for data space as processor.
Further, chip to be measured is a chip or a plurality of chip in concrete physics realization; Perhaps, chip to be measured is on same hardware single board, or on different hardware single board; Chip to be measured comprises wherein one or both of up function and descending function.
In order to solve the problems of the technologies described above, the invention provides a kind of method of testing of wireless baseband chips in base station side, relate to chip to be measured and controller unit in the testing apparatus; This method step is:
(a) write test case, prepare running parameter, upstream or downstream data, reference result and the expecting state of described chip to be measured;
(b) starting test starts working;
(c) controller unit disposes chip to be measured, is that chip to be measured produces the uplink antenna data flow in correct time window, and chip to be measured is exported up result according to the data flow of configuration parameter and input;
(d) controller unit is inquired about the up operating state of chip to be measured, and up result and up reference result are compared, to judge the correctness of the up result of chip to be measured.
Further, step (c) or controller unit dispose chip to be measured, chip to be measured is according to the business data flow output uplink/downlink antenna data flow of configuration parameter and input, and controller unit is gathered the described uplink/downlink antenna data flow of chip to be measured in correct time window; Step (d) controller unit compares uplink/downlink antenna data flow and descending reference result, and inquires about the downlink working state of chip to be measured, to judge chip downlink processing result's to be measured correctness.
Further, controller unit comprises main control unit and the control unit of falling forward, in the preceding step that also comprises of step (c):
The main control unit visit is fallen forward and is controlled the operating state of unit, and is the control configuration of cells running parameter of falling forward;
Main control unit writes the control unit of falling forward with uplink antenna data flow or descending reference result, and the generation time point of uplink antenna data flow or the acquisition time point of uplink/downlink antenna data flow are informed the control unit of falling forward;
Step (c) servant control unit is pressed generation time point and is produced the uplink antenna data flow, and perhaps, acquisition time point collection uplink/downlink antenna data flow is pressed in the control unit of falling forward;
Step (d) main control unit is judged the correctness of the up result of chip to be measured; Perhaps, chip downlink processing result's to be measured correctness is judged in the control unit of falling forward, and preserves result of determination; Treat that main control unit visit obtains.
Further, the comparison of up result and up reference result, perhaps uplink/downlink antenna data flow and descending reference result's comparison is bit-level relatively.
Testing apparatus and method that the present invention proposes, reach the required running parameter of configuration wireless baseband chips to be measured in correct time window by the generation time point of control upstream digital baseband I Q data flow, the acquisition time point of descending digital baseband IQ data flow, can judge whether chip to be measured exports correct result on correct time point, and in concrete reliability testing process, can judge accurately that normally whether chip operation to be measured; Simultaneously, the present invention also can be used for print function and performance test under the common indoor environment situation, can remedy wireless special test equipment and can't finish the defective of fixed time point bit-level calibration function, and can alleviate the demand of many cover test environments, help to save R﹠D costs the substantive test instrument; Have, the present invention also can be used for the FPGA prototype verification in wireless baseband chips (the being not limited to base station side) R﹠D process again, also is applicable to the testing scheme of the radio base band function that direct employing FPGA realizes.
Embodiment
Explain technical scheme of the present invention in detail below in conjunction with the drawings and specific embodiments.
Fig. 2 has provided the structural representation of wireless baseband chips in base station side RTA reliability test assembly one embodiment of the present invention, and this device comprises: clock-signal generator 201, field programmable logic array FPGA202 and the memory cell 203 of hanging down thereof, wireless baseband chips to be tested 204, processor 205 and the memory cell 206 of hanging down thereof; Wherein:
Clock-signal generator 201, be connected with FPGA 202, wireless baseband chips to be tested 204 and processor 205 respectively, be used for providing correct clock, reset signal and timing signal to them, make each functional unit correct input clock is arranged, on can being resetted and be carried out regularly reliably synchronously so that collaborative work well.
FPGA 202, be connected with memory cell 203, wireless baseband chips to be tested 204 and processor 205 respectively, be used under the control of processor 205, upstream digital base band antenna data that receiving processor 205 writes or descending digital baseband antenna data, and with its preservation; Export satisfactory uplink antenna data flow to chip 204 to be measured, and the state information of chip output to be measured is preserved; Or gather the uplink/downlink antenna data flow of its outputs from chip to be measured 204, and the result of chip 204 outputs to be measured is carried out bit-level relatively with reference result, export results' correctness to judge chip 204 to be measured, and judged result is preserved.
FPGA 202 adopts the IQ data stream interface to realize being connected with chip 204 to be measured, can be convenient to support the chip to be measured 204 of different interface type requirement.
Memory cell 203 is used for the judged result of the downlink processing of the state information of up, uplink/downlink antenna data that storage of processor 205 writes FPGA 202, chip to be measured 204 outputs and 202 pairs of chips 204 outputs to be measured of FPGA.
Wireless baseband chips 204 to be measured is connected with processor 205, is used for the measurand as the radio base band processing capacity.
Chip 204 to be measured can be on same hardware single board with being connected of other functional module, also can be not on same hardware single board; Chip 204 to be measured can comprise up function and descending function simultaneously, also can only comprise up function or descending function, can be a chip or a plurality of chip in concrete physics realization.
Processor 205, be connected with memory cell 206, be used to realize parameter configuration and status poll, write upstream digital base band antenna data or descending digital baseband antenna data to FPGA 202 to FPGA 202, respectively as up test and excitation with and descending reference result usefulness; Read the judged result of the up processing of upstream digital base band antenna data and 202 pairs of chip 204 outputs to be measured of FPGA from FPGA 202; Realization is to the parameter configuration and the status poll of chip 204 to be measured, write the downlink service data that it needs to chip 204 to be measured, read the downlink processing result of chip 204 outputs to be measured, and itself and reference result are carried out bit-level relatively, judge the correctness of 204 times line outputs of chip to be measured.
Processor 205 is physically a processor not necessarily, can be (can be adaptive with chip 204 interfaces to be measured) a plurality of of the same type or dissimilar processors.
The memory cell 206 that processor is hung down is used for the data space as processor 205, the data that storage will write the data of FPGA 202, chip to be measured 204, read from FPGA 202, chip to be measured 204.
Description by above testing apparatus as can be seen, in fact processor 205 has been formed controller unit with FPGA 202, be used to control the generation time point of uplink antenna data flow of chip to be measured and the acquisition time point of uplink/downlink antenna data flow, and in correct time window, be the up running parameter of chip configuration to be measured and produce described uplink antenna data flow, or from chip collection uplink/downlink antenna data flow to be measured, and, judge the correctness of described chip uplink and downlink result to be measured respectively according to the up result of chip to be measured and the downstream data flow of collection.Wherein, FPGA 202 is controlled the unit as the servant of controller unit, 205 main control units as controller unit of processor.The control unit employing FPGA 202 that falls forward realizes it mainly being the flexibility of considering interface, is convenient to dock with the chip to be measured of various functions, if Interface Matching can certainly adopt microcontroller, microprocessor chip or nonshared control unit chip to realize.
Divide uplink flow process and downlink flow process for the workflow that wireless baseband chips 204 carries out reliability testing, below will describe in detail to it respectively.
As shown in Figure 3, the flow process that wireless baseband chips 204 to be measured is carried out reliability testing may further comprise the steps:
Step 301 is write test case, prepares the reference result of running parameter, upstream or downstream business datum, chip to be measured 204 outputs of wireless baseband chips 204 to be measured and expecting state etc.;
Step 302 starts test and starts working;
Startup comprises: clock-signal generator provides correct clock, reset signal, timing signal to controller unit and chip to be measured, and applies the reliability test condition, the reliability testing of beginning upstream or downstream;
Step 303, controller unit correctly dispose chip to be measured;
Step 304, controller unit are that chip to be measured produces the uplink antenna data flow in correct time window, and chip to be measured is according to the upstream output result of configuration and input; Perhaps, chip to be measured is according to the business data flow output result of configuration and input, and controller unit is gathered the uplink/downlink antenna data flow in correct time window;
That is to say that up in the step 304, descending two both can separately have been carried out respectively, and see also subsequent figures 4a and Fig. 4 b in testing uplink or downflow; Also can be unified in the same flow process and carry out.
Step 305 reads the operating state of chip to be measured;
Step 306 is judged chip to be measured output result's correctness.
Fig. 4 a has provided the flow process of the up reliability testing embodiment of wireless baseband chips 204 to be measured, may further comprise the steps:
Step 401, write appropriate test case according to the reliability testing demand, and according to test case be ready in required active configuration parameter of chip to be measured 204 and the test process may updated parameters, uplink antenna data flow (can produce), the reference result (can produce) of chip to be measured 204 outputs and the desired value of chip to be measured 204 some state spaces etc. by the algorithm simulating link by the algorithm simulating link;
Step 402, clock-signal generator 201 provide correct clock, reset signal, timing signal to FPGA 202, chip to be measured 204 and processor 205, so as each functional unit on obtaining regularly synchronously;
Step 403 applies the reliability test condition, begins up reliability testing;
Step 404, processor 205 visit FPGA 202 operating states and configuration effort parameters;
Step 405, processor 205 writes FPGA 202 (can deposit the memory cell 203 that it is hung down in) to the uplink antenna data flow of test case appointment, and the upstream data transmitting time point of appointment in the test case is informed FPGA 202;
Step 406, processor 205 disposes chip 204 to be measured (comprise and may carry out parameter update at follow-up time point) according to the running parameter of test case appointment in correct time window;
Step 407, FPGA 202 produces the uplink antenna data flow by the fixed time point and gives chip 204 to be measured;
Step 408, chip 204 to be measured is handled according to the uplink antenna data flow of configuration parameter and input, and the output result is given processor 205;
Step 409, the up operating state of processor 205 inquiries chip 204 to be measured;
Step 410, processor 205 is according to the actual result (comprising the output time point) of the reference result of chip 204 outputs to be measured, chip to be measured 204 outputs and the state information of reading from chip 204 to be measured, the correctness of result of determination.
Fig. 4 b has provided the flow process of the descending reliability testing embodiment of chip 204 to be measured, may further comprise the steps:
Step 411, determine appropriate test case according to the reliability testing demand, and be ready to according to test case in the active configuration parameter of chip to be measured 204 of its appointment and the test process may updated parameters, supporting downlink service data (can adopt controlled random number), the reference result (can produce) of chip to be measured 204 outputs and the desired value of chip to be measured 204 some state spaces etc. by the algorithm simulating link;
Step 412, clock-signal generator 201 provide correct clock, reset signal, timing signal to FPGA 202, chip to be measured 204 and processor 205, so as each functional unit on obtaining regularly synchronously;
Step 413 applies experimental condition, begins descending reliability testing;
Step 414, processor 205 visit FPGA 202 operating states and configuration effort parameters;
Step 415, processor 205 writes FPGA202 (can deposit the memory cell 203 that it is hung down in) to the reference result of 204 times line outputs of chip to be measured, and uplink/downlink antenna data acquisition time point is informed FPGA 202;
Step 416, processor 205 disposes chip 204 to be measured (comprise and may carry out parameter update at follow-up time point) and writes supporting downlink service data according to the running parameter of test case appointment in correct time window;
Step 417, chip 204 to be measured is handled according to the downlink service data of configuration parameter and input, and the output result;
Step 418, FPGA 202 gathers the descending digital baseband IQ data flow of chip 204 outputs to be measured by the fixed time point;
Step 419, FPGA 202 is according to the real processing results of the reference result of chip 204 outputs to be measured, chip to be measured 204 outputs, judge chip to be measured 204 output results' correctness, and judged result is deposited in the memory space in the FPGA 202, or deposit in the plug-in memory cell 203;
Step 420, the memory cell of processor 205 visit FPGA 202 is to obtain the judged result of FPGA 202; Simultaneously, inquire about the downlink working state of chip 204 to be measured, according to judged result of obtaining and the comprehensive correctness of judging chip 204 work to be measured of state information.
Fig. 5 has provided another embodiment of the present invention---be used for WCDMA NodeB baseband chip RTA reliability test assembly structural representation.The device that present embodiment relates to is realized on a PCB veneer, provides power supply, clock, timing signal, debug serial port, network interface, SerDes interface etc. by the baseband board outside.
Clock/reset signal in the present embodiment/timing generator 501 becomes single-ended clock chip, clock driver, watchdog chip, timing signal process chip by difference and forms, clock, reset signal, required clock, reset signal and the timing signal etc. of timing signal conversion cost device other parts that the outside is provided, make each functional unit on obtaining regularly synchronously, and collaborative work well.
On-the-spot FPGA 502 in the present embodiment adopts 1 Altera Stratix Series FPGA to realize, concrete model is EP1S20F780C7; The memory cell 503 that FPGA hangs for 502 times adopts 2 identical DDR SDRAM to realize, concrete model is MT46V16M16P-6T.The FPGA 502 inner DDR of use controllers are realized the read and write access to DDR SDRAM 503, and the operating frequency of DDR clock is 100MHz.
Wireless baseband chips to be tested in the present embodiment comprises up function and descending function simultaneously, but on two phy chips, realize, be respectively descending chip-level of WCDMA NodeB base band and HSDPA symbol level coprocessor 504, the up chip-level coprocessor 505 of WCDMA NodeB base band.
FPGA 502 realizes being connected with it by the up chip-level coprocessor 505 self-defining interfaces of WCDMA NodeB base band, embodies the flexibility of adopting the FPGA device to realize this interface; Simultaneously, FPGA 502 realizes being connected with it by descending chip-level of WCDMA NodeB base band and HSDPA symbol level coprocessor 504 self-defining interfaces, embodies the flexibility of adopting the FPGA device to realize this interface.
The processor of 3 different models of processor adopting in the present embodiment realizes that wherein 1 is the CPU 510 of PowerPC series, and concrete model is MPC8270ZUUPE; Other 2 TI C6000 series DSP 1 508, DSP2 506 that are respectively same model, concrete model is TMS320C6416DGLZA6E3.
The memory cell that processor is hung down in the present embodiment adopts the memory cell that matches with 3 processors, and wherein, CPU hangs 4 SDRAM 511 down, and concrete model is MT48LC16M16A2TG-75; Each DSP hangs 1 SDRAM (507,509) respectively down, and concrete model is HY57V561620T-H.
CPU 510 realizes and being connected of SDRAM 511 that by bus 60X Bus SDRAM 511 is as the data storage cell of CPU510; And CPU510 links to each other by the existing 32 bit bit wides of the HPI cause for gossip of bus 60X Bus and DSP1 508, DSP2 506, and schedule information is mutual etc. when working in order to the control of the loading that realizes the DSP program, the operation of DSP program start and test platform.
CPU510 realizes that by local bus Local Bus and FPGA 502 16 bit bit wides link to each other, in order to realize that FPGA 502 running parameters dispose and writing of the reading of operating state, upstream digital base band antenna data and writing with retaking of a year or grade and reading descending test result etc. of retaking of a year or grade, descending reference result.
DSP2 506 realizes and being connected of SDRAM 507 that by EMIFB SDRAM507 is as the data storage cell of DSP2 506.
DSP2 506 realizes and being connected of descending chip-level of WCDMA NodeB base band and HSDPA symbol level coprocessor 504 by EMIFA, in order to reading of the writing of the configuration of realization WCDMA descending chip-level of NodeB base band and HSDPA symbol level coprocessor 504 running parameters, downlink service data, the descending chip-level of WCDMA NodeB base band and HSDPA symbol level coprocessor 504 operating states etc.Descending chip-level of WCDMA NodeB base band and HSDPA symbol level coprocessor 504 are operated under the SBSRAM mode, and clock frequency is up to 100MHz, read time-delay and will be configured to 3 clock cycle, write time-delay and are configured to for 0 clock cycle.
DSP1 508 realizes and being connected of SDRAM 509 that by EMIFB SDRAM509 is as the data storage cell of DSP1 508.
DSP1 508 realizes and being connected of the up chip-level coprocessor 505 of WCDMA NodeB base band by EMIFA, in order to configuration, the chip-level of realizing up chip-level coprocessor 505 running parameters of WCDMA NodeB base band handle export the result read with and the reading etc. of operating state.The up chip-level coprocessor 505 of WCDMA NodeB base band is operated under the SBSRAM mode, and clock frequency is up to 100MHz, reads time-delay and will be configured to 3 clock cycle, writes time-delay and is configured to for 0 clock cycle.
In above-mentioned specific embodiment, uplink and downlink are respectively to realize on two chips, and concrete test also is the test of separately carrying out up, descending chip respectively according to Fig. 3 and Fig. 4.Though in the true application of WCDMA base station side is up, descending collaborative work, and uplink has feedback information to offer descending chip.In the test job of detailed programs, for up, descending chip being separated independent test so that test failure is positioned, the present invention has all considered this factor in test platform, and accurately constructs for this feedback information of descending chip configuration with DSP2.
Adopt said method of the present invention and device, can accurately control the generation time point of upstream digital baseband I Q data flow, processor can obtain the up processing output result of wireless baseband chips to be tested, and realizes the real-time results judgement of bit-level; Simultaneously, can accurately control the acquisition time point of descending digital baseband IQ data flow; Programmable logic array FPGA can obtain the downlink processing output result of wireless baseband chips to be measured, and realizes the real-time results judgement of bit-level; In concrete reliability testing process, can accurately judge whether operate as normal of wireless baseband chips to be measured.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.