CN101557598B - Device and method for testing wireless baseband chips in base station side - Google Patents
Device and method for testing wireless baseband chips in base station side Download PDFInfo
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- CN101557598B CN101557598B CN2008100904284A CN200810090428A CN101557598B CN 101557598 B CN101557598 B CN 101557598B CN 2008100904284 A CN2008100904284 A CN 2008100904284A CN 200810090428 A CN200810090428 A CN 200810090428A CN 101557598 B CN101557598 B CN 101557598B
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Abstract
The invention relates to a device for testing wireless baseband chips in a base station side, which comprises mutually connected chips to be tested and a controller unit, wherein the chips to be tested are used as uplink and downlink tested objects, and the controller unit controls the generation of the data stream of an uplink antenna of the chips to be tested or collects the data stream of a downlink antenna of the chips to be tested at a right time point. The method comprises the steps: inquiring the state of the chips to be tested, reading uplink processing results output by the chips to be tested, comparing the uplink processing results with uplink parameter results, or comparing collected downlink antenna data streams with downlink parameter results, and inquiring the downlink operating state of the chips to be tested so as to respectively judge the correctness of the uplink processing results and the downlink processing results of the chips to be tested. The invention can make up the defect that a special wireless testing instrument can not achieve the function of bit-order calibration at a specified time point, alleviates the requirements of a plurality of sets of testing environments to a plurality of testing instruments and saves the costs of research and development.
Description
Technical field
The present invention relates to Design of Digital Integrated Circuit and measuring technology in the wireless communication field, relate in particular to wireless baseband chips in base station side RTA reliability test assembly and method in the communication apparatus.
Background technology
In the R﹠D process of wireless baseband chips in base station side, need be placed on wireless baseband chips and carry out reliability testing in the real application systems.Provided the schematic diagram of traditional base station side apparatus reliability test system as Fig. 1.Whole test system comprises: wireless terminal 101, wireless terminal 102, radio-frequency apparatus 103, reliability testing environment 104, radio base band equipment 105, base station controller 106, core net 107, wireless baseband chips to be tested is positioned in the radio base band equipment 105, and radio base band equipment 105 itself is positioned in the reliability testing environment 104.
In the side apparatus reliability testing of traditional base station, generally be to apply experimental condition (than exacting terms more under the normal condition) earlier, begin professional test such as CS territory (such as " making a phone call ") or PS territory (such as " FTP download ") or CS territory+PS territory mixing then, last phenomenon according to concrete test draws test result according to standards such as the world or country or industry or enterprises.Such as: standard codes such as State Standard of the People's Republic of China GB/T 17618, GB/T 17626.1: if relevant professional standard technical committee or product technology standard do not provide different specification requirements, result of the test should be carried out following classification by the service conditions of being tried equipment and functional specification.
A) performance is normal in the specification requirement limit value;
B) function or performance are temporary transient reduces or forfeiture, but can recover voluntarily;
C) function or performance are temporary transient reduces or forfeiture, but needs the operator to intervene or system reset;
D) because of equipment (element) or software damage, or loss of data and cause the function that can not return to normal condition voluntarily to reduce or forfeiture.
In concrete reliability testing process, if (relevant with reliability conditions) mistake takes place wireless baseband chips to be tested, but because machine system has certain fault-tolerant ability in concrete communication, radio base band equipment 105 functions and performance also may be normal; If any mistake does not take place wireless baseband chips to be tested, but other hardware or software on the radio base band equipment 105 make a mistake, and also may cause radio base band equipment 105 faults.Therefore be difficult to judge whether operate as normal of wireless baseband chips to be tested according to the test result of whole radio base band equipment 105.
Summary of the invention
Technical problem to be solved by this invention provides a kind of wireless baseband chips in base station side testing apparatus and method, can solve to adopt conventional test methodologies to be difficult to judge the problem that whether normal chip operation to be measured is according to the system test result.
In order to solve the problems of the technologies described above, the invention provides a kind of testing apparatus of wireless baseband chips in base station side, comprise interconnective chip to be measured and controller unit; Wherein:
Chip to be measured is used for the measurand as up reliability testing;
Controller unit, be used to control the generation time point of the uplink antenna data flow of chip to be measured, and in correct time window up running parameter of chip configuration to be measured and generation uplink antenna data flow, by inquiring about the state of chip to be measured, and the up result of reading chip output to be measured, and up result and up reference result compared, judge the correctness of the up result of chip to be measured.
Further,
Chip to be measured is used for the measurand as descending reliability testing;
Controller unit, be used to control the acquisition time point of the uplink/downlink antenna data flow of chip to be measured, in correct time window, be the chip configuration downlink working parameter to be measured and the uplink/downlink antenna data flow of gathering chip to be measured, and uplink/downlink antenna data flow and the descending reference result who gathers compared, and the downlink working state of inquiring about chip to be measured, judge chip downlink processing result's to be measured correctness.
Further, controller unit comprises main control unit and the control unit of falling forward, wherein:
Fall forward and control the unit, be connected with chip to be measured and main control unit respectively, be used under the control of main control unit, the data from main control unit that receive are preserved, and export the uplink antenna data flow to chip to be measured at the time point of appointment; Perhaps, at the appointed time put from chip to be measured and gather the uplink/downlink antenna data flow, judging downlink processing result's correctness, and the judged result of downlink processing is preserved;
Main control unit is used for respectively fall forward control unit and chip to be measured are carried out parameter configuration and status poll, writes the uplink antenna data of digital baseband antenna to the control unit of falling forward, and as up test and excitation usefulness, and reads the uplink antenna data from the control unit of falling forward; And the correctness of judging line output on the chip to be measured; Perhaps, write the uplink/downlink antenna data of digital baseband antenna,, and read the judged result of downlink processing from the control unit of falling forward as descending reference usefulness as a result to the control unit of falling forward.
Further, the control unit of falling forward is field programmable logic array FPGA, and main control unit is a processor; Wherein, processor is a processor physically, or a plurality of processor, and a plurality of processors are of the same type or dissimilar.
Further, FPGA contains the memory unit access controller, hangs with memory cell under the FPGA, is used under the control of memory unit access controller the data space as FPGA; Hang with memory cell under the processor, be used for data space as processor.
Further, chip to be measured is a chip or a plurality of chip in concrete physics realization; Perhaps, chip to be measured is on same hardware single board, or on different hardware single board; Chip to be measured comprises wherein one or both of up function and descending function.
In order to solve the problems of the technologies described above, the invention provides a kind of method of testing of wireless baseband chips in base station side, relate to chip to be measured and controller unit in the testing apparatus; This method step is:
(a) write test case, prepare running parameter, upstream or downstream data, reference result and the expecting state of described chip to be measured;
(b) starting test starts working;
(c) controller unit disposes chip to be measured, is that chip to be measured produces the uplink antenna data flow in correct time window, and chip to be measured is exported up result according to the data flow of configuration parameter and input;
(d) controller unit is inquired about the up operating state of chip to be measured, and up result and up reference result are compared, to judge the correctness of the up result of chip to be measured.
Further, step (c) or controller unit dispose chip to be measured, chip to be measured is according to the business data flow output uplink/downlink antenna data flow of configuration parameter and input, and controller unit is gathered the described uplink/downlink antenna data flow of chip to be measured in correct time window; Step (d) controller unit compares uplink/downlink antenna data flow and descending reference result, and inquires about the downlink working state of chip to be measured, to judge chip downlink processing result's to be measured correctness.
Further, controller unit comprises main control unit and the control unit of falling forward, in the preceding step that also comprises of step (c):
The main control unit visit is fallen forward and is controlled the operating state of unit, and is the control configuration of cells running parameter of falling forward;
Main control unit writes the control unit of falling forward with uplink antenna data flow or descending reference result, and the generation time point of uplink antenna data flow or the acquisition time point of uplink/downlink antenna data flow are informed the control unit of falling forward;
Step (c) servant control unit is pressed generation time point and is produced the uplink antenna data flow, and perhaps, acquisition time point collection uplink/downlink antenna data flow is pressed in the control unit of falling forward;
Step (d) main control unit is judged the correctness of the up result of chip to be measured; Perhaps, chip downlink processing result's to be measured correctness is judged in the control unit of falling forward, and preserves result of determination; Treat that main control unit visit obtains.
Further, the comparison of up result and up reference result, perhaps uplink/downlink antenna data flow and descending reference result's comparison is bit-level relatively.
Testing apparatus and method that the present invention proposes, reach the required running parameter of configuration wireless baseband chips to be measured in correct time window by the generation time point of control upstream digital baseband I Q data flow, the acquisition time point of descending digital baseband IQ data flow, can judge whether chip to be measured exports correct result on correct time point, and in concrete reliability testing process, can judge accurately that normally whether chip operation to be measured; Simultaneously, the present invention also can be used for print function and performance test under the common indoor environment situation, can remedy wireless special test equipment and can't finish the defective of fixed time point bit-level calibration function, and can alleviate the demand of many cover test environments, help to save R﹠D costs the substantive test instrument; Have, the present invention also can be used for the FPGA prototype verification in wireless baseband chips (the being not limited to base station side) R﹠D process again, also is applicable to the testing scheme of the radio base band function that direct employing FPGA realizes.
Description of drawings
Fig. 1 is the schematic diagram of traditional base station side apparatus reliability test system;
Fig. 2 is a wireless baseband chips in base station side RTA reliability test assembly structural representation of the present invention;
Fig. 3 is a wireless baseband chips in base station side method for testing reliability flow chart of the present invention;
Fig. 4 a is the inventive method is carried out the uplink test to a chip to be measured workflow diagram;
Fig. 4 b is the inventive method is carried out the downlink test to a chip to be measured workflow diagram;
Fig. 5 carries out reliability testing for the present invention to WCDMA NodeB baseband chip device example structure schematic diagram.
Embodiment
Explain technical scheme of the present invention in detail below in conjunction with the drawings and specific embodiments.
Fig. 2 has provided the structural representation of wireless baseband chips in base station side RTA reliability test assembly one embodiment of the present invention, and this device comprises: clock-signal generator 201, field programmable logic array FPGA202 and the memory cell 203 of hanging down thereof, wireless baseband chips to be tested 204, processor 205 and the memory cell 206 of hanging down thereof; Wherein:
Clock-signal generator 201, be connected with FPGA 202, wireless baseband chips to be tested 204 and processor 205 respectively, be used for providing correct clock, reset signal and timing signal to them, make each functional unit correct input clock is arranged, on can being resetted and be carried out regularly reliably synchronously so that collaborative work well.
FPGA 202, be connected with memory cell 203, wireless baseband chips to be tested 204 and processor 205 respectively, be used under the control of processor 205, upstream digital base band antenna data that receiving processor 205 writes or descending digital baseband antenna data, and with its preservation; Export satisfactory uplink antenna data flow to chip 204 to be measured, and the state information of chip output to be measured is preserved; Or gather the uplink/downlink antenna data flow of its outputs from chip to be measured 204, and the result of chip 204 outputs to be measured is carried out bit-level relatively with reference result, export results' correctness to judge chip 204 to be measured, and judged result is preserved.
FPGA 202 adopts the IQ data stream interface to realize being connected with chip 204 to be measured, can be convenient to support the chip to be measured 204 of different interface type requirement.
The memory cell 206 that processor is hung down is used for the data space as processor 205, the data that storage will write the data of FPGA 202, chip to be measured 204, read from FPGA 202, chip to be measured 204.
Description by above testing apparatus as can be seen, in fact processor 205 has been formed controller unit with FPGA 202, be used to control the generation time point of uplink antenna data flow of chip to be measured and the acquisition time point of uplink/downlink antenna data flow, and in correct time window, be the up running parameter of chip configuration to be measured and produce described uplink antenna data flow, or from chip collection uplink/downlink antenna data flow to be measured, and, judge the correctness of described chip uplink and downlink result to be measured respectively according to the up result of chip to be measured and the downstream data flow of collection.Wherein, FPGA 202 is controlled the unit as the servant of controller unit, 205 main control units as controller unit of processor.The control unit employing FPGA 202 that falls forward realizes it mainly being the flexibility of considering interface, is convenient to dock with the chip to be measured of various functions, if Interface Matching can certainly adopt microcontroller, microprocessor chip or nonshared control unit chip to realize.
Divide uplink flow process and downlink flow process for the workflow that wireless baseband chips 204 carries out reliability testing, below will describe in detail to it respectively.
As shown in Figure 3, the flow process that wireless baseband chips 204 to be measured is carried out reliability testing may further comprise the steps:
Startup comprises: clock-signal generator provides correct clock, reset signal, timing signal to controller unit and chip to be measured, and applies the reliability test condition, the reliability testing of beginning upstream or downstream;
That is to say that up in the step 304, descending two both can separately have been carried out respectively, and see also subsequent figures 4a and Fig. 4 b in testing uplink or downflow; Also can be unified in the same flow process and carry out.
Step 305 reads the operating state of chip to be measured;
Step 306 is judged chip to be measured output result's correctness.
Fig. 4 a has provided the flow process of the up reliability testing embodiment of wireless baseband chips 204 to be measured, may further comprise the steps:
Step 401, write appropriate test case according to the reliability testing demand, and according to test case be ready in required active configuration parameter of chip to be measured 204 and the test process may updated parameters, uplink antenna data flow (can produce), the reference result (can produce) of chip to be measured 204 outputs and the desired value of chip to be measured 204 some state spaces etc. by the algorithm simulating link by the algorithm simulating link;
Step 402, clock-signal generator 201 provide correct clock, reset signal, timing signal to FPGA 202, chip to be measured 204 and processor 205, so as each functional unit on obtaining regularly synchronously;
Step 403 applies the reliability test condition, begins up reliability testing;
Step 404, processor 205 visit FPGA 202 operating states and configuration effort parameters;
Step 405, processor 205 writes FPGA 202 (can deposit the memory cell 203 that it is hung down in) to the uplink antenna data flow of test case appointment, and the upstream data transmitting time point of appointment in the test case is informed FPGA 202;
Step 406, processor 205 disposes chip 204 to be measured (comprise and may carry out parameter update at follow-up time point) according to the running parameter of test case appointment in correct time window;
Step 407, FPGA 202 produces the uplink antenna data flow by the fixed time point and gives chip 204 to be measured;
Step 408, chip 204 to be measured is handled according to the uplink antenna data flow of configuration parameter and input, and the output result is given processor 205;
Step 409, the up operating state of processor 205 inquiries chip 204 to be measured;
Step 410, processor 205 is according to the actual result (comprising the output time point) of the reference result of chip 204 outputs to be measured, chip to be measured 204 outputs and the state information of reading from chip 204 to be measured, the correctness of result of determination.
Fig. 4 b has provided the flow process of the descending reliability testing embodiment of chip 204 to be measured, may further comprise the steps:
Step 413 applies experimental condition, begins descending reliability testing;
Fig. 5 has provided another embodiment of the present invention---be used for WCDMA NodeB baseband chip RTA reliability test assembly structural representation.The device that present embodiment relates to is realized on a PCB veneer, provides power supply, clock, timing signal, debug serial port, network interface, SerDes interface etc. by the baseband board outside.
Clock/reset signal in the present embodiment/timing generator 501 becomes single-ended clock chip, clock driver, watchdog chip, timing signal process chip by difference and forms, clock, reset signal, required clock, reset signal and the timing signal etc. of timing signal conversion cost device other parts that the outside is provided, make each functional unit on obtaining regularly synchronously, and collaborative work well.
On-the-spot FPGA 502 in the present embodiment adopts 1 Altera Stratix Series FPGA to realize, concrete model is EP1S20F780C7; The memory cell 503 that FPGA hangs for 502 times adopts 2 identical DDR SDRAM to realize, concrete model is MT46V16M16P-6T.The FPGA 502 inner DDR of use controllers are realized the read and write access to DDR SDRAM 503, and the operating frequency of DDR clock is 100MHz.
Wireless baseband chips to be tested in the present embodiment comprises up function and descending function simultaneously, but on two phy chips, realize, be respectively descending chip-level of WCDMA NodeB base band and HSDPA symbol level coprocessor 504, the up chip-level coprocessor 505 of WCDMA NodeB base band.
The processor of 3 different models of processor adopting in the present embodiment realizes that wherein 1 is the CPU510 of PowerPC series, and concrete model is MPC8270ZUUPE; Other 2 TIC6000 series DSP 1 508, DSP2 506 that are respectively same model, concrete model is TMS320C6416DGLZA6E3.
The memory cell that processor is hung down in the present embodiment adopts the memory cell that matches with 3 processors, and wherein, CPU hangs 4 SDRAM 511 down, and concrete model is MT48LC16M16A2TG-75; Each DSP hangs 1 SDRAM (507,509) respectively down, and concrete model is HY57V561620T-H.
CPU510 realizes and being connected of SDRAM 511 that by bus 60X Bus SDRAM 511 is as the data storage cell of CPU510; And CPU510 links to each other by the existing 32 bit bit wides of the HPI cause for gossip of bus 60X Bus and DSP1 508, DSP2 506, and schedule information is mutual etc. when working in order to the control of the loading that realizes the DSP program, the operation of DSP program start and test platform.
CPU510 realizes that by local bus Local Bus and FPGA 502 16 bit bit wides link to each other, in order to realize that FPGA 502 running parameters dispose and writing of the reading of operating state, upstream digital base band antenna data and writing with retaking of a year or grade and reading descending test result etc. of retaking of a year or grade, descending reference result.
In above-mentioned specific embodiment, uplink and downlink are respectively to realize on two chips, and concrete test also is the test of separately carrying out up, descending chip respectively according to Fig. 3 and Fig. 4.Though in the true application of WCDMA base station side is up, descending collaborative work, and uplink has feedback information to offer descending chip.In the test job of detailed programs, for up, descending chip being separated independent test so that test failure is positioned, the present invention has all considered this factor in test platform, and accurately constructs for this feedback information of descending chip configuration with DSP2.
Adopt said method of the present invention and device, can accurately control the generation time point of upstream digital baseband I Q data flow, processor can obtain the up processing output result of wireless baseband chips to be tested, and realizes the real-time results judgement of bit-level; Simultaneously, can accurately control the acquisition time point of descending digital baseband IQ data flow; Programmable logic array FPGA can obtain the downlink processing output result of wireless baseband chips to be measured, and realizes the real-time results judgement of bit-level; In concrete reliability testing process, can accurately judge whether operate as normal of wireless baseband chips to be measured.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (13)
1. the testing apparatus of a wireless baseband chips in base station side is characterized in that, described device comprises interconnective chip to be measured and controller unit; Wherein:
Described chip to be measured is used for the measurand as up reliability testing;
Described controller unit, be used to control the generation time point of the uplink antenna data flow of described chip to be measured, and in correct time window, be the up running parameter of described chip configuration to be measured and produce described uplink antenna data flow, by inquiring about the up operating state of described chip to be measured, and the up result of reading described chip output to be measured, and described up result and up reference result compared, judge the correctness of the up result of described chip to be measured.
2. according to the described device of claim 1, it is characterized in that described controller unit comprises main control unit and the control unit of falling forward, wherein:
Described servant is controlled the unit, be connected with described chip to be measured and described main control unit respectively, be used under the control of described main control unit, the data from described main control unit that receive are preserved, and export the uplink antenna data flow to described chip to be measured at the time point of appointment;
Described main control unit, be used for respectively described servant being controlled the unit and described chip to be measured carries out parameter configuration and status poll, control the uplink antenna data that the unit writes the digital baseband antenna to described servant, use as up test and excitation, and read the output result that chip to be measured is handled according to the uplink antenna data flow of configuration parameter and input, and the correctness of judging line output on the described chip to be measured.
3. according to the described device of claim 2, it is characterized in that it is field programmable logic array FPGA that described servant is controlled the unit, described main control unit is a processor; Wherein, described processor is a processor physically, or a plurality of processor, and described a plurality of processors are of the same type or dissimilar.
4. according to the described device of claim 3, it is characterized in that described FPGA contains the memory unit access controller, hang with memory cell under the described FPGA, be used under the control of described memory unit access controller data space as described FPGA; Hang with memory cell under the described processor, be used for data space as described processor.
5. according to the described device of claim 1, it is characterized in that described chip to be measured is a chip or a plurality of chip in concrete physics realization; Described chip to be measured comprises wherein one or both of up function and descending function.
6. the testing apparatus of a wireless baseband chips in base station side is characterized in that, described device comprises interconnective chip to be measured and controller unit; Wherein:
Described chip to be measured is used for the measurand as descending reliability testing;
Described controller unit, be used to control the acquisition time point of the uplink/downlink antenna data flow of described chip to be measured, in correct time window, be the described chip configuration downlink working parameter to be measured and the described uplink/downlink antenna data flow of gathering described chip to be measured, and the described uplink/downlink antenna data flow and the descending reference result that will gather compare, and the downlink working state of inquiring about chip to be measured, judge described chip downlink processing result's to be measured correctness.
7. according to the described device of claim 6, it is characterized in that described controller unit comprises main control unit and the control unit of falling forward, wherein:
Described servant is controlled the unit, be connected with described chip to be measured and described main control unit respectively, be used under the control of described main control unit, the data from described main control unit that receive are preserved, at the appointed time put from described chip to be measured and gather the uplink/downlink antenna data flow, read the downlink processing result of chip output to be measured, and itself and descending reference result are carried out bit-level relatively, judge the correctness of line output under the chip to be measured, and judged result is preserved;
Described main control unit is used for respectively described servant being controlled the unit and described chip to be measured carries out parameter configuration and status poll, controls the uplink/downlink antenna data that the unit writes the digital baseband antenna to described servant, uses as described descending reference result; Obtain the described judged result of the control unit of falling forward, according to the comprehensive correctness of judging chip operation to be measured of the state information of judged result of obtaining and described chip to be measured.
8. according to the described device of claim 7, it is characterized in that it is field programmable logic array FPGA that described servant is controlled the unit, described main control unit is a processor; Wherein, described processor is a processor physically, or a plurality of processor, and described a plurality of processors are of the same type or dissimilar.
9. according to the described device of claim 8, it is characterized in that described FPGA contains the memory unit access controller, hang with memory cell under the described FPGA, be used under the control of described memory unit access controller data space as described FPGA; Hang with memory cell under the described processor, be used for data space as described processor.
10. according to the described device of claim 6, it is characterized in that described chip to be measured is a chip or a plurality of chip in concrete physics realization; Described chip to be measured comprises wherein one or both of up function and descending function.
11. the method for testing of a wireless baseband chips in base station side relates to chip to be measured and controller unit in the testing apparatus, it is characterized in that, described chip to be measured is as the measurand of up reliability testing, and described method step is:
(a1) write test case, prepare running parameter, upstream data, reference result and the expecting state of described chip to be measured;
(b1) starting test starts working;
(c1) described controller unit disposes described chip to be measured, is that described chip to be measured produces the uplink antenna data flow in correct time window, and described chip to be measured is exported up result according to the described data flow of configuration parameter and input;
(d1) described controller unit is inquired about the up operating state of chip to be measured, and described up result and up reference result are compared, to judge the correctness of the up result of described chip to be measured;
Perhaps, described chip to be measured is as the measurand of descending reliability testing, and described method step is:
(a2) write test case, prepare running parameter, downlink data, reference result and the expecting state of described chip to be measured;
(b2) starting test starts working;
(c2) controller unit disposes chip to be measured, and described chip to be measured is according to the business data flow output uplink/downlink antenna data flow of configuration parameter and input, and described controller unit is gathered the described uplink/downlink antenna data flow of described chip to be measured in correct time window;
(d2) described controller unit compares described uplink/downlink antenna data flow and descending reference result, and inquires about the downlink working state of described chip to be measured, to judge described chip downlink processing result's to be measured correctness.
12. in accordance with the method for claim 11, it is characterized in that described controller unit comprises main control unit and the control unit of falling forward, in the preceding step that also comprises of step (c1):
Described main control unit is visited the operating state that described servant is controlled the unit, and controls the configuration of cells running parameter for described servant;
Described main control unit writes described servant with described uplink antenna data flow and controls the unit, and the generation time point of described uplink antenna data flow is informed that described servant controls the unit;
The described servant of step (c1) is controlled the unit and is produced described uplink antenna data flow by described generation time point; The described main control unit of step (d1) is judged the correctness of the up result of described chip to be measured;
Perhaps, in the preceding step that also comprises of step (c2):
Described main control unit is visited the operating state that described servant is controlled the unit, and controls the configuration of cells running parameter for described servant;
Described main control unit writes described servant with described descending reference result and controls the unit, and the acquisition time point of described uplink/downlink antenna data flow is informed that described servant controls the unit;
The described servant of step (c2) is controlled the unit and is gathered described uplink/downlink antenna data flow by described acquisition time point;
The described servant of step (d2) is controlled the unit described uplink/downlink antenna data flow and descending reference result is compared, and preserves judged result, treats that described main control unit visit obtains.
13. in accordance with the method for claim 11, it is characterized in that, the comparison of described up result and described up reference result, perhaps described uplink/downlink antenna data flow and described descending reference result's comparison is bit-level relatively.
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| CN103780322B (en) * | 2014-01-26 | 2015-09-09 | 中国电子科技集团公司第五十八研究所 | The express network communication chip method of testing of low cost and high reliability and circuit |
| CN105827333A (en) * | 2015-01-07 | 2016-08-03 | 展讯通信（上海）有限公司 | System and method of baseband chip automatic test |
| CN105989897A (en) * | 2015-03-05 | 2016-10-05 | 中兴通讯股份有限公司 | Test method and device of synchronous dynamic random access memory SDRAM |
| CN106341355A (en) | 2015-07-09 | 2017-01-18 | 深圳市中兴微电子技术有限公司 | Digital intermediate frequency processing system detection method and device |
| CN105629153B (en) * | 2015-12-24 | 2018-10-09 | 大唐微电子技术有限公司 | A kind of method of chip testing |
| CN109151860B (en) * | 2018-07-27 | 2021-09-07 | 深圳市极致汇仪科技有限公司 | Test configuration method and system of wireless chip |
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| CN1627671A (en) * | 2003-12-10 | 2005-06-15 | 诺基亚公司 | Radio transmitter testing method, radio transmitter and base station |
| CN1758780A (en) * | 2004-10-09 | 2006-04-12 | 华为技术有限公司 | Reglation testing axiliary interface device of radio base station and testing system using it |
| CN1852541A (en) * | 2005-11-30 | 2006-10-25 | 华为技术有限公司 | Base-station fault detecting method and fault detecting system |
| CN1909427A (en) * | 2005-08-01 | 2007-02-07 | 北京信威通信技术股份有限公司 | Base station up synchronous test method and device |
| CN1980448A (en) * | 2005-12-09 | 2007-06-13 | 中兴通讯股份有限公司 | System and method for detecting base-station NodcB |
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2008
- 2008-04-07 CN CN2008100904284A patent/CN101557598B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1627671A (en) * | 2003-12-10 | 2005-06-15 | 诺基亚公司 | Radio transmitter testing method, radio transmitter and base station |
| CN1758780A (en) * | 2004-10-09 | 2006-04-12 | 华为技术有限公司 | Reglation testing axiliary interface device of radio base station and testing system using it |
| CN1909427A (en) * | 2005-08-01 | 2007-02-07 | 北京信威通信技术股份有限公司 | Base station up synchronous test method and device |
| CN1852541A (en) * | 2005-11-30 | 2006-10-25 | 华为技术有限公司 | Base-station fault detecting method and fault detecting system |
| CN1980448A (en) * | 2005-12-09 | 2007-06-13 | 中兴通讯股份有限公司 | System and method for detecting base-station NodcB |
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| CN101557598A (en) | 2009-10-14 |
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