CN101556924A - Method for bonding and separating silicon wafers - Google Patents
Method for bonding and separating silicon wafers Download PDFInfo
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- CN101556924A CN101556924A CNA2009100986753A CN200910098675A CN101556924A CN 101556924 A CN101556924 A CN 101556924A CN A2009100986753 A CNA2009100986753 A CN A2009100986753A CN 200910098675 A CN200910098675 A CN 200910098675A CN 101556924 A CN101556924 A CN 101556924A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 178
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 172
- 239000010703 silicon Substances 0.000 title claims abstract description 172
- 238000000034 method Methods 0.000 title claims abstract description 74
- 235000012431 wafers Nutrition 0.000 title claims abstract description 61
- 238000005260 corrosion Methods 0.000 claims abstract description 23
- 230000007797 corrosion Effects 0.000 claims abstract description 21
- 238000009792 diffusion process Methods 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 230000003746 surface roughness Effects 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 4
- 230000003014 reinforcing effect Effects 0.000 abstract description 5
- 238000002156 mixing Methods 0.000 abstract description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000007596 consolidation process Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004570 mortar (masonry) Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Abstract
The invention discloses a method for bonding and separating silicon wafers, which includes following steps of: 1) selecting polished silicon wafers of which facades are polished surfaces; 2) setting an oxide layer on the facade of any polished silicon wafer or each polished silicon wafer, leading the facades of every two polished silicon wafers to be opposite, and then performing room temperature bonding; 3) putting a bonding silicon wafer group in a high-temperature furnace for reinforcing; 4) performing corrosion treatment on the reinforced silicon wafer group by using HF solution to remove the oxide layer on the outer surface of the reinforced silicon wafer group; 5) re-blending and diffusing both surfaces of the obtained silicon wafer group and 6) putting the silicon wafer group which is re-blended and diffused in the HF solution for treatment so as to corrode the oxide layer on the bonding surface of the silicon wafer group and obtain two silicon wafers which are separated from each other. The silicon wafer produced by adopting the method has the characteristic of controllable thickness.
Description
Technical field
The present invention relates to a kind of method for bonding and separating silicon wafers.The present invention can be used for preparing the silicon chip of N-/N+, P-/N+ structure.
Background technology
Produce the silicon chip of N-/N+, P-/N+ structure, two kinds of methods are arranged usually: method one is the method for gently mixing silicon at heavily doped silicon chip surface extension one deck; Method two is to carry out thermal diffusion with light doped silicon slice in diffusion furnace to form heavily dopedly on the surface, then the one side of silicon chip is carried out grinding and polishing and realizes said structure.Method one is that the silicon chip quality of the said structure made of epitaxy method is good, but processing cost is higher, and the equipment cost of the epitaxial furnace of its use is also very high, and along with the increase of epitaxial thickness, cost can be higher.In order to reduce cost to process some silicon chips not high, so method two has been arranged to the silicon chip quality requirements.Fig. 1 is that method two is the schematic diagram of example with processing N-/N+, earlier the N-silicon chip is put into diffusion furnace and carry out high temperature expansion phosphorus, two sides at silicon chip forms the N+ layer, then N+ layer simultaneously all being reached a part of N-layer grinds away, polish then and form N-/N+ layer structure, in this process, there is similar half silicon material to be lost by grinding.
Patent of invention CN101186082 provides a kind of method that can reduce the loss of silicon material, its method that adopts (as shown in Figure 2) is a method of utilizing multi-line cutting machine that the thin silicon sheet is divided into two, but there is following defective in this method: 1, the thickness of silicon chip has only a hundreds of micron, making the steel wire of multi-line cutting machine just in time switch to middle in the silicon chip of micron is unusual difficulty, the silicon wafer thickness that adopts above-mentioned line blanking method to process has bigger deviation, TTV can be bigger, directly influences the consistency and the rate of finished products of subsequent device; 2, can be very dirty through the silicon chip after the multi-thread cutting, be difficult to clean up; 3, the method for using line to cut need be used steel wire and sand and make frock clamp etc., causes cost higher.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method for bonding and separating silicon wafers with low cost, adopts this method to make the characteristics that silicon chip has controllable thickness.
In order to solve the problems of the technologies described above, the invention provides a kind of method for bonding and separating silicon wafers, in turn include the following steps:
1), select 2 polished silicon slices for use, the front of every polished silicon slice is burnishing surface;
2), arbitrarily oxide layer is set (is SIO in the front of a slice polished silicon slice therein
2Layer), make then the positive front with another polished silicon slice of the above-mentioned polished silicon slice that has an oxide layer in twos over against after carry out the room temperature bonding;
Perhaps oxide layer all is set in the front of every polished silicon slice, make then the above-mentioned polished silicon slice front that has an oxide layer in twos over against after carry out the room temperature bonding;
Get the bonding silicon chip group;
3), above-mentioned bonding silicon chip group is put in the high temperature furnace reinforces, the reinforced silicon wafer group; Make then to judge: when the outer surface of reinforced silicon wafer group has oxide layer, then enter step 4); When the outer surface of reinforced silicon wafer group does not have oxide layer, then directly enter step 5);
4), the reinforced silicon wafer group is handled with the HF solution corrosion,, wash successively then and dry to remove the oxide layer of reinforced silicon wafer group outer surface;
5), adopt triple method of diffusion, heavily doped diffusion is carried out on the two sides of gained silicon chip group;
6), the silicon chip group after the above-mentioned heavily doped diffusion is put into HF solution handle, to erode the oxide layer of silicon chip group bonding face; Get 2 silicon chips that are separated from each other.
Improvement as method for bonding and separating silicon wafers of the present invention: polished silicon slice is lightly doped polished silicon slice.
Further improvement as method for bonding and separating silicon wafers of the present invention: the surface roughness≤0.8nm in polished silicon slice front.
Further improvement as method for bonding and separating silicon wafers of the present invention: the thickness of oxide layer that is positioned at the polished silicon slice front is 0.3um～3um, surface roughness≤0.8nm.
Because it is relevant that oxidated layer thickness and the silicon chip of subsequent step separate, the thick more silicon chip that helps the back more of oxidated layer thickness separates; But the simultaneous oxidation layer thickness is thick more, and the cost of oxidation also can correspondingly increase.Therefore, the preferred 1.5um～6um of bonded layer place thickness of oxide layer (be two polished silicon slice frontside oxide layer and).
Further improvement as method for bonding and separating silicon wafers of the present invention: the method that oxide layer is set is thermal oxidation method or CVD method (chemical vapour deposition technique).
Because it is little to select for use thermal oxidation method can guarantee that the surface roughness of the oxide layer (being silicon dioxide layer) of gained worsens, so the oxide layer that is generated by thermal oxidation method can be directly used in next step bonding, therefore preferred thermal oxidation method; The temperature of thermal oxidation method is 900～1200 ℃.
When selecting chemical vapour deposition technique (CVD method) for use, make the oxide layer of deposition must be deposited on the front (burnishing surface that promptly is used for bonding) of polished silicon slice; Owing to adopt the oxide layer surface roughness of CVD method gained higher, therefore need carry out chemico-mechanical polishing to the oxide layer in polished silicon slice front, make surface roughness≤0.8nm; Want the amount of skimming of strict control chemico-mechanical polishing, promptly satisfying under the prerequisite of above-mentioned surface roughness, the amount of skimming of chemico-mechanical polishing is the smaller the better; Must can not polish the whole oxide layer that is positioned at the polished silicon slice front, otherwise can cause subsequent step 6) silicon chip can not separate.
Further improvement as method for bonding and separating silicon wafers of the present invention: it is 1000～1200 ℃ that step 3) is reinforced temperature, and the time is 10 minutes～10 hours; Can under aerobic or oxygen free condition, reinforce.It is high more to reinforce temperature, and consolidation time is long more, and bond strength is high more.
Further improvement as method for bonding and separating silicon wafers of the present invention: step 4) is carried out corrosion treatment for the reinforced silicon wafer group directly is immersed in the HF solution, the processing time=(corrosion rate of reinforced silicon wafer group outer surface oxidated layer thickness/HF solution); The mass concentration of HF solution is 5%～50%.
When the front of selecting for use thermal oxidation method to polished silicon slice is provided with oxide layer, can inevitably make the reverse side of this polished silicon slice produce oxide layer equally; Therefore, the silicon chip that adopts the thermal oxidation method gained is through step 2) bonding and the reinforcing of step 3) after, must carry out the HF solution corrosion of step 4) and handle, and then enter the heavily doped diffusion of step 5).And when the front of selecting for use the CVD method to polished silicon slice is provided with oxide layer, divide following two kinds of situations: if the reverse side of A polished silicon slice does not produce oxide layer, the gained silicon chip is through step 2 so) bonding and the reinforcing of step 3) after, need not to carry out the HF solution corrosion processing of step 4), and directly enter the heavily doped diffusion of step 5); If the back side of B polished silicon slice also produces oxide layer, the HF solution corrosion that then needs to carry out step 4) is earlier handled, and enters step 5 then.
The oxidated layer thickness on silicon chip group surface can adopt conventional method to obtain, for example can adopt the direct test silicon wafer of instrument to obtain, be specially: when silicon chip, put the polished silicon slice (hereinafter to be referred as the monitoring silicon chip) that a slice is used to monitor oxidated layer thickness, also this sheet monitoring silicon chip is put into during reinforcing, reinforcing the thickness of oxide layer that finishes back test monitoring silicon chip is exactly the thickness of silicon chip group surface oxide layer.
The HF solution of the variable concentrations that the corrosion rate of HF solution refers to is to SIO
2Corrosion rate; These data can obtain by conventional method, for example specifically can be: the SIO of known thickness
2Layer is surveyed remaining SIO again by after the HF solution corrosion regular hour
2Layer thickness, the HF solution that just can obtain variable concentrations is to SIO
2Corrosion rate be: (corrosion before oxidated layer thickness-remaining oxidated layer thickness)/etching time.
Further improvement as method for bonding and separating silicon wafers of the present invention: the weight percent concentration of HF solution is 〉=40% in the step 6).
Further improvement as method for bonding and separating silicon wafers of the present invention: adopt deionized water rinsing in the step 4).
Method for bonding and separating silicon wafers of the present invention is a kind of elder generation to carry out silicon chip bonding, carries out the method for separating again after the heavily doped processing then.
In the present invention:
1, step 1): the thickness of polished silicon slice is 100～700um, and diameter is 2～12 inches (inch); As bonding face, the front face surface roughness of polished silicon slice is wanted≤0.8nm with the front of polished silicon slice; The reverse side of polished silicon slice can be abradant surface, erosional surface or burnishing surface.
2, bonding method step 2) is conventional silicon chip room temperature Direct Bonding method, and bonding zone air cleaning grade is≤10 grades.
3,, place for a long time or in the process of operation silicon chip group, silicon chip group can be separated because silicon chip group bond strength behind the room temperature bonding is not high; Therefore the high temperature that is provided with step 3) is reinforced, thereby the bond strength of silicon chip is improved, thereby has guaranteed that silicon chip group is at subsequent step 4) the HF corrosion treatment time can not be separated into 2 silicon chips.
Step 3) is reinforced and can be carried out under aerobic or oxygen free condition, and consolidation effect is basic identical.
4, controlled step 4) the corrosion treatment time, purpose is for the oxide layer that can remove the silicon chip group surface, can avoids the SIO of bonding face again
2Be corroded.
5, adopt conventional triple method of diffusion, be used to obtain the isostructural silicon chip of required N-/N+, P-/N+.
Method for bonding and separating silicon wafers of the present invention has the following advantages:
1) silicon chip is clean, cleans easily.
2) silicon chip and the original silicon chip thickness after the separation is basic identical, does not have thickness deviation.
3) TTV before silicon chip TTV and the bonding is basic identical, guarantees consistency of product.
4) the technology cost is low relatively, does not need to use mortar and steel wire, and technology is convenient, simple.
5) save the silicon material.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
Fig. 1 is the silicon polished preparation flow figure of existing band heavily doped diffusion layer;
Fig. 2 is the silicon polished preparation flow figure that adopts line to cut in the patent of invention CN101186082 processing procedure;
Fig. 3 is the silicon polished preparation flow figure of band heavily doped diffusion layer of the present invention.
Embodiment
Embodiment 1, Fig. 3 have provided a kind of method for bonding and separating silicon wafers, carry out following steps successively:
1), select 2 monocrystalline silicon pieces for use, the crystal orientation is＜111 〉, the doping model is the N type, dopant is a phosphorus, resistivity is greater than 30 ohm. centimetre, the surface roughness 0.5nm in this monocrystalline silicon piece front, thickness are that 250um, diameter are 100mm.
2), adopt means of wet thermal oxidation, 1100 ℃ of thermal oxidations 300 minutes, oxygen flow 6.6l/min, hydrogen flowing quantity is 9l/min, thereby makes the surface (being positive and negative 2 faces) of every N type (111) monocrystalline silicon piece that oxide layer all is set, this thickness of oxide layer is 1.2um.
Owing to select means of wet thermal oxidation for use, therefore can guarantee the surface roughness≤0.8nm of the oxide layer (being silicon dioxide layer) of gained.
The front that makes above-mentioned 2 monocrystalline silicon pieces then is in twos over against back bonding on the bonding machine, and bonding method adopts conventional silicon chip room temperature Direct Bonding method, and bonding zone air cleaning grade is 10 grades, gets the bonding silicon chip group.
3), above-mentioned bonding silicon chip group is put in the annealing furnace handles, logical nitrogen in the annealing furnace, treatment temperature is 1150 ℃, the time is 1 hour; Get the reinforced silicon wafer group;
4), the reinforced silicon wafer group directly is immersed in mass concentration is to carry out corrosion treatment in 10% the HF solution, to remove the oxide layer of reinforced silicon wafer group outer surface; Can suitably rock HF solution, the processing time=corrosion rate of surface oxidation layer thickness/HF; Because the HF solution corrosion speed of this concentration is 50nm/ minute, so,
Processing time=1.2um/0.05=24 minute.
Adopt deionized water rinsing then, then adopt conventional rotation drying mode to carry out dried, get dry silicon chip group.
5), adopt conventional triple method of diffusion, heavily doped diffusion N+ is carried out on the two sides of above-mentioned dry silicon chip group.
6), the silicon chip group after the above-mentioned heavily doped diffusion is put into concentration is that 50%HF solution is handled, to erode the oxide layer of silicon chip group bonding face; Until obtaining 2 silicon chips that are separated from each other, the silicon chip that separates is transferred in the horse, rinse well with deionized water, and be rotated drying.
Test through conventional method: the thickness of 2 silicon chips is 249um, silicon chip surface non-oxidation layer.
Embodiment 2, a kind of method for bonding and separating silicon wafers, carry out following steps successively:
1), select 2 monocrystalline silicon pieces for use, the crystal orientation is＜111 〉, the doping model is the P type, dopant is a boron, resistivity is greater than 30 ohm. centimetre, the surface roughness 0.5nm in this monocrystalline silicon piece front, thickness are that 300um, diameter are 125mm.
2), wherein a slice silicon chip adopts means of wet thermal oxidation, 1150 ℃ of thermal oxidations 570 minutes, oxygen flow 6.6l/min, hydrogen flowing quantity were 9l/min, thereby make the positive and negative surface of this sheet P type (111) monocrystalline silicon piece that oxide layer all is set, this thickness of oxide layer is 2.5um.
Make the positive front with another polished silicon slice of the polished silicon slice that has oxide layer in twos over against back bonding on the bonding machine then, bonding method adopts conventional silicon chip room temperature Direct Bonding method, and bonding zone air cleaning grade is 10 grades, the bonding silicon chip group.
3), above-mentioned bonding silicon chip group is put in the annealing furnace handles, logical nitrogen and oxygen in the annealing furnace, treatment temperature is 1150 ℃, the time is 1 hour; Get the reinforced silicon wafer group;
4), the reinforced silicon wafer group directly is immersed in mass concentration is to carry out corrosion treatment in 10% the HF solution, to remove the oxide layer of reinforced silicon wafer group outer surface, can suitably rock HF solution; The processing time=corrosion rate of surface oxidation layer thickness/HF; Because the HF solution corrosion speed of this concentration is 50nm/ minute, so,
Processing time=2.5um/0.05=50 minute.
Adopt deionized water rinsing then, then adopt conventional drying to carry out dried, get dry silicon chip group.
5), adopt conventional triple method of diffusion, heavily doped diffusion N+ is carried out on the two sides of above-mentioned dry silicon chip group.
6), the silicon chip group after the above-mentioned heavily doped diffusion is put into concentration is that 50%HF solution is handled, to erode the oxide layer of silicon chip group bonding face; Until obtaining 2 silicon chips that are separated from each other, with regard to end process; Silicon chip is taken out from HF solution.
Test through conventional method: the thickness of 1 silicon chip is 299um, and the thickness of another sheet silicon chip is 300um; Silicon chip surface non-oxidation layer.
At last, it is also to be noted that what more than enumerate only is several specific embodiments of the present invention.Obviously, the invention is not restricted to above embodiment, many distortion can also be arranged.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention all should be thought protection scope of the present invention.
Claims (9)
1, a kind of method for bonding and separating silicon wafers, its characteristic is in turn include the following steps:
1), select 2 polished silicon slices for use, the front of described every polished silicon slice is burnishing surface;
2), arbitrarily the front of a slice polished silicon slice is provided with oxide layer therein, make then the positive front with another polished silicon slice of the above-mentioned polished silicon slice that has an oxide layer in twos over against after carry out the room temperature bonding;
Perhaps oxide layer all is set in the front of every polished silicon slice, make then the above-mentioned polished silicon slice front that has an oxide layer in twos over against after carry out the room temperature bonding;
Get the bonding silicon chip group;
3), above-mentioned bonding silicon chip group is put in the high temperature furnace reinforces, the reinforced silicon wafer group; Make then to judge:, then enter step 4) when the outer surface of reinforced silicon wafer group has oxide layer; When the outer surface of reinforced silicon wafer group does not have oxide layer, then directly enter step 5);
4), the reinforced silicon wafer group is handled with the HF solution corrosion, to remove the oxide layer of reinforced silicon wafer group outer surface; Wash successively then and drying;
5), adopt triple method of diffusion, heavily doped diffusion is carried out on the two sides of gained silicon chip group;
6), the silicon chip group after the above-mentioned heavily doped diffusion is put into HF solution handle, to erode the oxide layer of silicon chip group bonding face; Get 2 silicon chips that are separated from each other.
2, method for bonding and separating silicon wafers according to claim 1 is characterized in that: described polished silicon slice is lightly doped polished silicon slice.
3, method for bonding and separating silicon wafers according to claim 1 and 2 is characterized in that: the surface roughness≤0.8nm in described polished silicon slice front.
4, method for bonding and separating silicon wafers according to claim 3 is characterized in that: the described thickness of oxide layer that is positioned at the polished silicon slice front is 0.3um～3um, surface roughness≤0.8nm.
5, method for bonding and separating silicon wafers according to claim 4 is characterized in that: the method that oxide layer is set described step 2) is thermal oxidation method or chemical vapour deposition technique.
6, method for bonding and separating silicon wafers according to claim 5 is characterized in that: it is 1000～1200 ℃ that described step 3) is reinforced temperature, and the time is 10 minutes～10 hours; Under aerobic or oxygen free condition, reinforce.
7, method for bonding and separating silicon wafers according to claim 6, it is characterized in that: described step 4) is carried out corrosion treatment for the reinforced silicon wafer group directly is immersed in the HF solution, the processing time=corrosion rate of reinforced silicon wafer group outer surface oxidated layer thickness/HF solution; The mass concentration of HF solution is 5%～50%.
8, method for bonding and separating silicon wafers according to claim 7 is characterized in that: the mass concentration of HF solution is 〉=40% in the described step 6).
9, method for bonding and separating silicon wafers according to claim 8 is characterized in that: adopt deionized water rinsing in the described step 4).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109427581A (en) * | 2017-08-30 | 2019-03-05 | 株洲中车时代电气股份有限公司 | A kind of manufacturing method of power rectifier tube core |
| CN110660722A (en) * | 2019-10-15 | 2020-01-07 | 上海集成电路研发中心有限公司 | Temporary bonding structure and temporary bonding method |
| CN112259677A (en) * | 2020-10-19 | 2021-01-22 | 济南晶正电子科技有限公司 | Film bonding body with pattern, preparation method and electronic device |
-
2009
- 2009-05-19 CN CN2009100986753A patent/CN101556924B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109427581A (en) * | 2017-08-30 | 2019-03-05 | 株洲中车时代电气股份有限公司 | A kind of manufacturing method of power rectifier tube core |
| CN110660722A (en) * | 2019-10-15 | 2020-01-07 | 上海集成电路研发中心有限公司 | Temporary bonding structure and temporary bonding method |
| CN112259677A (en) * | 2020-10-19 | 2021-01-22 | 济南晶正电子科技有限公司 | Film bonding body with pattern, preparation method and electronic device |
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| CN101556924B (en) | 2010-09-08 |
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Address after: 201604 No. 88, Yangshi Road, Shihudang Town, Songjiang District, Shanghai Patentee after: Shanghai Chaosi Semiconductor Co.,Ltd. Address before: 201604 No. 88, Yangshi Road, Shihudang Town, Songjiang District, Shanghai Patentee before: SHANGHAI ADVANCED SILICON TECHNOLOGY Co.,Ltd. |
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Addressee: Wang Xiaoming Document name: Notification of Conformity |
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| DD01 | Delivery of document by public notice |