CN101661884B - Method for manufacturing transistor by using silicon single crystal slices - Google Patents
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- CN101661884B CN101661884B CN2009101524164A CN200910152416A CN101661884B CN 101661884 B CN101661884 B CN 101661884B CN 2009101524164 A CN2009101524164 A CN 2009101524164A CN 200910152416 A CN200910152416 A CN 200910152416A CN 101661884 B CN101661884 B CN 101661884B
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Abstract
The invention discloses a method for manufacturing a transistor by using silicon single crystal slices, which comprises the steps of: 1) selecting two light-doped polished silicon slices, wherein the front surfaces thereof are the polished surfaces; 2) conducting N+ or P+ pre-expansion on each silicon slice and then arranging an oxide layer on the front surface of the pre-expanded polished silicon slice; 3) causing the front surfaces of the two polished silicon slices with the oxide layers to face to each other for bonding at room temperature, and putting the obtained bonded silicon slice group into a high-temperature furnace for high-temperature processing; 4) conducting mechanical grinding and polishing on the two surfaces of the obtained silicon slice group; 5) manufacturing a transistor chip on the two surfaces of the silicon slice group respectively; 6) putting the silicon slice group obtained in the Step 5) into an HF solution to separate the silicon slices; and 7) metallizing the surfaces of the silicon slices without the transistor chip, and then removing optical resist, scribing and packaging, thus obtaining the transistor. The method for manufacturing the transistor by using silicon single crystal slices can guarantee the performance of the transistor.
Description
Technical field
The present invention relates to the thin monocrystalline silicon piece of a kind of usefulness and make transistorized method, mainly is the manufacture method of gently mixing structure silicon-based of (top layer of silicon chip)/heavily doped (bottom of silicon chip).
Background technology
Produce the silicon chip of N-/N+, P/N+, N/P+, P/P+ structure, two kinds of methods are arranged usually: method one is the method for gently mixing silicon at heavily doped silicon chip surface extension one deck; Method two is to carry out thermal diffusion with light doped silicon slice in diffusion furnace to form heavily dopedly on the surface, then the one side of silicon chip is carried out grinding and polishing and realizes said structure.Method one is that the silicon chip quality of the said structure made of epitaxy method is good, but processing cost is higher, and the equipment cost of the epitaxial furnace of its use is also very high, and along with the increase of epitaxial thickness, cost can be higher.In order to reduce cost to process some silicon chips not high, so method two has been arranged to the silicon chip quality requirements.Fig. 1 is that method two is the schematic diagram of example with processing N-/N+, earlier the N-silicon chip is put into diffusion furnace and carry out high temperature expansion phosphorus, two sides at silicon chip forms the N+ layer, then N+ layer simultaneously all being reached a part of N-layer grinds away, polish then and form N-/N+ layer structure, in this process, there is similar half silicon material to be lost by grinding.And triple method of diffusion need be about 1275 degree, handled in about 200 hours, for a long time high-temperature heat treatment can be introduced the regenerated heat defective in wafer bulk.These thermal defects can cause in the device technology dopant different with other regional diffusion velocities in the diffusion velocity of fault location, can cause the consistency of device parameters poor, and the leakage current of processing device is big, and breakdown potential is forced down etc., thereby makes device performance poor.
Patent of invention CN1064766A provides a kind of silicon material loss of can reducing, can also reduce simultaneously silicon chip high-temperature process time method (as shown in Figure 2) is earlier silicon chip to be carried out pre-expansion phosphorus, carry out the single face grinding and polishing then, a back side deposit skim, 2 silicon chip back are bondd with glass dust, carry out device technology then.But there are following several point defects in this method: 1, owing to bond with glass dust, must have a lot of bubbles at bonding interface, the existence of bubble can cause stress a large amount of between two silicon chips to exist, in subsequent device technology, stress at high temperature can induce crystal defect, thereby reduces device performance greatly.2 owing to carrying out glassy bond again under the situation of having made polished silicon wafer in the silicon chip front, guarantee that the silicon chip front is not damaged, and operation easier is big; And be easy to injure the polished silicon wafer surface.
Summary of the invention
The technical problem to be solved in the present invention provides a kind ofly with low cost makes transistorized method with the thin single crystal silicon chip, and adopting this method to make transistor, to have a technology cost low, and the silicon chip internal flaw is few in the course of processing, thereby guarantees the characteristics of transistor performance.
In order to solve the problems of the technologies described above, the invention provides a kind of method with making transistor with silicon single crystal thin section, in turn include the following steps:
1), select 2 lightly doped polished silicon slices for use, the front of every polished silicon slice is a burnishing surface;
2), above-mentioned every silicon chip all carries out N+ or P+ pre-expansion, the front of the polished silicon slice after pre-expansion is provided with oxide layer then;
3), make above-mentioned 2 polished silicon slice fronts that have an oxide layer in twos over against after carry out the room temperature bonding, the bonding silicon chip group; Above-mentioned bonding silicon chip group is put into carries out high-temperature process in the high temperature furnace, silicon chip group after the high-temperature process;
4), mechanical lapping and polishing are carried out in two surfaces of silicon chip group after the high-temperature process;
5), adopt conventional semiconductor planar technology to make transistor chip respectively on two surfaces of step 4) gained silicon chip group, the photoresist of anticorrosive usefulness is set respectively on above-mentioned silicon chip group two surfaces that have transistor chip respectively then;
6), the silicon chip group with the step 5) gained places HF solution that silicon chip is separated;
7), with the surface metalation of not establishing transistor chip of silicon chip, remove photoresist, scribing and encapsulation then; Get transistor.
In the present invention, resistivity is at 1 ohm. and more than centimetre is light dope, and resistivity is at 1 ohm. and below centimetre is heavy doping.
Improvement as the method with making transistor with silicon single crystal thin section of the present invention: the thickness of oxide layer that is positioned at the polished silicon slice front step 2) is 0.5um～3um, surface roughness≤0.8nm and was 0 (promptly not having the above particle of 0.5um) greater than the particle of 0.5um.The method that oxide layer is set is a thermal oxidation method.
Because after oxide layer is set, can worsen as the roughness on the burnishing surface surface in polished silicon slice front, when roughness during, need carry out chemico-mechanical polishing to the oxide layer in polished silicon slice front greater than 0.8nm, make its surface roughness≤0.8nm; Want the amount of skimming of strict control chemico-mechanical polishing, promptly satisfying under the prerequisite of above-mentioned surface roughness, the amount of skimming of chemico-mechanical polishing is the smaller the better; Must can not polish the whole oxide layer that is positioned at the polished silicon slice front, otherwise can cause subsequent step 6) silicon chip can not separate.
As the further improvements in methods with making transistor with silicon single crystal thin section of the present invention: step 3) high-temperature process temperature is 900～1290 ℃, and the time is 10 minutes～100 hours.
As the further improvements in methods with making transistor with silicon single crystal thin section of the present invention: step 4) to high-temperature process after two surfaces of silicon chip group carry out mechanical lapping and polishing, each surperficial removal amount is 30～100um, and each surface roughness≤1.2nm.
As the further improvements in methods with making transistor with silicon single crystal thin section of the present invention: the weight percent concentration of HF solution is 10%～50% in the step 6).
Method with making transistor with silicon single crystal thin section of the present invention, be that a kind of elder generation carries out the phosphorus pre-expansion with polished silicon slice, and then two silicon wafer polishing faces (front) are carried out bonding relatively reinforce, again the two sides of bonding silicon chip group is ground and polishing, carry out planar device technology then, carry out the transistorized method of manufacturing of the back side (promptly not establishing that surface of transistor chip) metallization and scribing encapsulation after afterwards silicon chip being separated.
In the present invention:
1, step 1): the original thickness of polished silicon slice is 150～350um, and diameter is 2～12 inches (inch); As bonding face, the reverse side of polished silicon slice can be abradant surface, erosional surface or burnishing surface with the front of polished silicon slice.
2, in step 2) in, because that oxidated layer thickness and the silicon chip of subsequent step separate is relevant, the thick more silicon chip that helps the back more of oxidated layer thickness separates; But the simultaneous oxidation layer thickness is thick more, and the cost of oxidation also can correspondingly increase.Therefore, the preferred 1um～6um of bonded layer place thickness of oxide layer (i.e. 2 oxidated layer thickness sums).
3, the bonding method of step 3) is conventional silicon chip room temperature Direct Bonding method, and bonding zone air cleaning grade is≤10 grades.
Two surfaces of silicon chip group are polished, and the form that can adopt two throwing machines to carry out twin polishing perhaps adopts single throwing machine that the two sides is polished separately, thereby makes two bites at a cherry this step of polishing.
The method of making transistor with silicon single crystal thin section of the present invention has the following advantages:
1) saves the silicon material;
2) the technology cost is low relatively, has reduced the long-time high-temperature process time;
3) greatly reduce because the defective that interfacial stress causes can improve device performance.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
Fig. 1 is the silicon polished preparation flow figure of existing band heavily doped diffusion layer;
Fig. 2 is the preparation flow figure of patent of invention CN1064766A;
Fig. 3 is a flow chart of the present invention.
Embodiment
Embodiment 1, Fig. 3 have provided a kind of method for bonding and separating silicon wafers, carry out following steps successively:
1), selects 2 monocrystalline polished silicon slices for use, the crystal orientation of this monocrystalline silicon piece is＜111 〉, the doping model is the N type, dopant is a phosphorus, resistivity is 33 ohm. centimetre～35 ohm. centimetre, the front of this monocrystalline polished silicon slice is the burnishing surface of surface roughness 0.5nm, and the thickness of this monocrystalline silicon piece is that 230um, diameter are 100mm.
2), every silicon chip all carries out following operation:
Silicon chip is placed high temperature dispersing furnace, adopt conventional phosphorus pre-expansion technology, 1140 ℃ of logical phosphorus source (POCL of temperature
3), to make impurity (N+) in silicon chip surface and carry out the pre-deposition diffusion, the time is 4 hours.
Adopt conventional thermal oxidation method then, process conditions are that temperature is 1140 degree, 6.6 liters/minute of oxygen flows, H
29 liters/minute of flows, the time is 3 hours; Thereby making the oxidated layer thickness that is positioned at the monocrystalline silicon piece front is 1.0um.
Because the employing thermal oxidation method, so the surface of N type (111) monocrystalline silicon piece of gained (being positive and negative 2 faces) all oxide layer can occur.The thickness of oxide layer that is positioned at the front of monocrystalline silicon piece is 1.0um, and surface roughness is 0.6nm, the surface exists 〉=and the particle of 0.5um.
Above-mentioned 2 monocrystalline silicon pieces are cleaned with SC1 and SC2 soup on cleaning machine successively, and with the particle test instrument oxide layer that is positioned at the monocrystalline silicon piece front is carried out surface particles and test, if have＞particle of 0.5um exists, then be judged to be nonconforming, that repeats cleans (after the perhaps slight polishing with SC1 and SC2 soup successively, Reduplicatedly clean with SC1 and SC2 soup successively), do not exist＞particle of 0.5um until the surface.
The prescription of SC1 soup is as follows: NH
4OH: H
2O
2: H
2O=1: 1: 6 (volume ratio),
The prescription of SC2 soup is as follows: H
2O
2: HCL: H2O=1: 1: 10 (volume ratio).
3), the room temperature bonding is carried out over against the back in twos in the above-mentioned satisfactory polished silicon slice front that has an oxide layer on the bonding machine, bonding method adopts conventional silicon chip room temperature Direct Bonding method, and bonding zone air cleaning grade is 10 grades, the bonding silicon chip group.
Then above-mentioned bonding silicon chip group is put into and carries out high-temperature process in the high-temperature annealing furnace, logical nitrogen in the high-temperature annealing furnace, treatment temperature is 1000 ℃, the time is 2 hours; Silicon chip group after the high-temperature process;
Bubble detection, no bubble are carried out in the interface of silicon chip group after infrared video camera is to the high-temperature process of this step 3) gained.
4), silicon chip group after the high-temperature process is carried out two-sided lapping equably on twin grinder, carry out twin polishing equably then on two throwing machines, making the silicon chip group gross thickness is 340um (being that single-sheet thickness is 170um); Wherein two-sided lapping removal amount 80um, twin polishing removal amount 40um, guarantee each surperficial roughness all≤1.2nm.
5), adopt conventional semiconductor planar technology, make transistor chip respectively on two surfaces of the silicon chip group of step 4) gained; The photoresist (for example selecting the high reverse side glue against corrosion of FSH-2 type for use) of anticorrosive usefulness is set respectively on above-mentioned silicon chip group two surfaces that have transistor chip respectively then, and the thickness of photoresist layer is 10um, and the purpose that this photoresist is set is for the protective transistor chip.
6), the silicon chip group of step 5) gained is placed the HF solution of mass concentration 40%, thus two silicon chips are separated;
7), according to common process, with that face metallization that silicon chip is not established transistor chip, remove photomask surface glue then, carry out scribing and encapsulation again; Get transistor.
The problem of bonding maximum is how to avoid the bubble at interface, and according to the conventional knowledge of the industry, bubble can cause a large amount of sliding lines of the inner generation of silicon chip in the follow-up hot procedure, thereby the device performance that causes processing reduces.And in the present embodiment, owing to not having bubble in the interface of silicon chip group after the high-temperature process that has guaranteed the step 3) gained; Therefore can guarantee device performance.
Contrast experiment 1,
With fully with the monocrystalline polished silicon slice of embodiment 1 as raw material, according to the preparation method that CN1064766A informs, the silicon chip group after bonding detects with infrared video camera, finds that there are a large amount of bubbles in the interface; Therefore can't guarantee the device performance of last gained.
Embodiment 2, a kind of method for bonding and separating silicon wafers, carry out following steps successively:
1), selects 2 monocrystalline polished silicon slices for use, the crystal orientation of this monocrystalline silicon piece is＜111 〉, the doping model is the N type, dopant is a phosphorus, resistivity is 33 ohm. centimetre～35 ohm. centimetre, the front of this monocrystalline silicon piece is the burnishing surface of surface roughness 0.5nm, and the thickness of this monocrystalline silicon piece is that 170um, diameter are 125mm.
2), with embodiment 1.
3), the room temperature bonding is carried out over against the back in twos in the front of the above-mentioned satisfactory polished silicon slice that has an oxide layer on the bonding machine, bonding method adopts conventional silicon chip room temperature Direct Bonding method, and bonding zone air cleaning grade is 10 grades, the bonding silicon chip group.
Then above-mentioned bonding silicon chip group is put in the high-temperature annealing furnace and handles, logical nitrogen in the annealing furnace, treatment temperature is 1280 ℃, the time is 20 minutes; Silicon chip group after the high-temperature process;
Bubble detection, no bubble are carried out in the interface of silicon chip group after infrared video camera is to the high-temperature process of this step 3) gained.
4), silicon chip group after the high-temperature process is ground with emery wheel on the single face grinder, every each 1 time, every removal amount is 35um; Carry out twin polishing then on two throwing machines, 40um is removed in twin polishing; The gross thickness that makes silicon chip group is 230um (being that single-sheet thickness is 115um), guarantee each surperficial roughness all≤1.2nm.
5), adopt conventional semiconductor planar technology on silicon chip group two surfaces of step 4) gained, to make transistor chip; The photoresist of anticorrosive usefulness is set on above-mentioned silicon chip group two surfaces (being positive and negative 2 outer surfaces) that have transistor chip respectively then; The thickness of photoresist layer is 10um.
6), the silicon chip group of step 5) gained is placed mass concentration 50%HF solution, thus silicon chip is separated;
7), according to common process, with that face metallization that silicon chip is not established transistor chip, remove photomask surface glue then, carry out scribing and encapsulation again; Get transistor.
The problem of bonding maximum is how to avoid the bubble at interface, and according to the conventional knowledge of the industry, bubble can cause a large amount of sliding lines of the inner generation of silicon chip in the follow-up hot procedure, thereby the device performance that causes processing reduces.And in the present embodiment, do not have bubble owing to guaranteed the interface of the reinforced silicon wafer group of step 3) gained; Therefore can guarantee device performance.
Contrast experiment 2,
With fully with the monocrystalline polished silicon slice of embodiment 2 as raw material, according to the preparation method that CN1064766A informs, the silicon chip group after bonding detects with ultrasonic wave, finds that there are a large amount of bubbles in the interface; Therefore can't guarantee the device performance of last gained.
At last, it is also to be noted that what more than enumerate only is several specific embodiments of the present invention.Obviously, the invention is not restricted to above embodiment, many distortion can also be arranged.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention all should be thought protection scope of the present invention.
Claims (7)
1. method with making transistor with silicon single crystal thin section, its characteristic is in turn include the following steps:
1), select 2 lightly doped polished silicon slices for use, the front of described every polished silicon slice is a burnishing surface;
2), above-mentioned every silicon chip all carries out N+ or P+ pre-expansion, the front of the polished silicon slice after pre-expansion is provided with oxide layer then; Silicon chip to gained cleans with SC1 and SC2 soup, does not exist＞particle of 0.5um until the surface;
3), make above-mentioned 2 polished silicon slice fronts that have an oxide layer in twos over against after carry out the room temperature bonding, the bonding silicon chip group; Above-mentioned bonding silicon chip group is put into carries out high-temperature process in the high temperature furnace, silicon chip group after the high-temperature process;
4), mechanical lapping and polishing are carried out in two surfaces of silicon chip group after the high-temperature process;
5), adopt conventional semiconductor planar technology to make transistor chip respectively on two surfaces of step 4) gained silicon chip group, the photoresist of anticorrosive usefulness is set respectively on above-mentioned silicon chip group two surfaces that have transistor chip respectively then;
6), the silicon chip group with the step 5) gained places HF solution that silicon chip is separated;
7), with the surface metalation of not establishing transistor chip of silicon chip, remove photoresist, scribing and encapsulation then; Get transistor.
2. the method with making transistor with silicon single crystal thin section according to claim 1 is characterized in that: the thickness of oxide layer that is positioned at the polished silicon slice front described step 2) is 0.5um～3um, surface roughness≤0.8nm and is 0 greater than the particle of 0.5um.
3. the method with making transistor with silicon single crystal thin section according to claim 2, it is characterized in that: the method that described step 2) oxide layer is set is a thermal oxidation method.
4. the method with making transistor with silicon single crystal thin section according to claim 3, it is characterized in that: described step 3) high-temperature process temperature is 900～1290 ℃, the time is 10 minutes～100 hours.
5. the method with making transistor with silicon single crystal thin section according to claim 4, it is characterized in that: described step 4) to high-temperature process after two surfaces of silicon chip group carry out mechanical lapping and polishing, each surperficial removal amount is 30～100um, and each surface roughness≤1.2nm.
6. the method with making transistor with silicon single crystal thin section according to claim 5, it is characterized in that: the mass concentration of HF solution is 10% to 50% in the described step 6).
7. the method with making transistor with silicon single crystal thin section according to claim 6, it is characterized in that: the original thickness of polished silicon slice is 150～350um in the described step 1).
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| CN102623875B (en) * | 2012-04-11 | 2014-04-09 | 青岛镭视光电科技有限公司 | Fusion bonding assembling method of crystal device |
| CN102945897B (en) * | 2012-11-10 | 2016-09-07 | 长治虹源科技晶片技术有限公司 | Processing method for the sapphire substrate of patterned substrate |
| CN103730358A (en) * | 2014-01-17 | 2014-04-16 | 上海超硅半导体有限公司 | Method for producing transistor through silicon single crystal sheets |
| CN109103079B (en) * | 2018-08-06 | 2021-06-01 | 济南晶正电子科技有限公司 | Nanoscale single crystal film and preparation method thereof |
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