CN102315096A - Preparation method of multilayer semiconductor substrate - Google Patents
Preparation method of multilayer semiconductor substrate Download PDFInfo
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- CN102315096A CN102315096A CN201110238030A CN201110238030A CN102315096A CN 102315096 A CN102315096 A CN 102315096A CN 201110238030 A CN201110238030 A CN 201110238030A CN 201110238030 A CN201110238030 A CN 201110238030A CN 102315096 A CN102315096 A CN 102315096A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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Abstract
The invention provides a preparation method of a multilayer semiconductor substrate, which comprises the following steps of: providing a first semiconductor substrate and a second semiconductor substrate; immerging at least one of the first semiconductor substrate and the second semiconductor substrate into an oxidizing solution or oxidizing gas to form an oxidized bonding-medium layer on a surface; and by using the bonding-medium layer as an intermediate layer, bonding the first semiconductor substrate and the second semiconductor substrate together.
Description
Technical field
The invention relates to the preparation method of multi-lager semiconductor substrate, particularly the preparation method of the multi-lager semiconductor substrate of low cost, high efficiency and process stabilizing.
Background technology
Circuit such as the power supply control thick film epitaxial wafer that is widely used in the integrated circuit, so-called thick film epitaxial wafer is meant the epitaxial loayer that has different resistivity at semiconductor substrate surface extension one deck, changes epitaxy layer thickness usually greater than 100um.Main extension technology of preparing adopts flat such substrate of epitaxial furnace preparation at present, through the epitaxial loayer that on semi-conductive substrate, has different resistivity through the epitaxy technique preparation.The shortcoming of epitaxy technique is that the time is long, and single furnaceman's skill time surpasses 2.5 hours, and production efficiency is low, and preparation cost is high, and thickness evenness only can be controlled at about 5% in the sheet.
Summary of the invention
Technical problem to be solved by this invention is that the preparation method of the multi-lager semiconductor substrate of a kind of low cost, high efficiency and process stabilizing is provided.
In order to address the above problem, the invention provides a kind of preparation method of multi-lager semiconductor substrate, comprise the steps: to provide first Semiconductor substrate and second Semiconductor substrate; In at least one immersion oxidizing solution or oxidizing gas in first Semiconductor substrate and second Semiconductor substrate, to form the bonding medium layer of oxidation on the surface; With the bonding medium layer is the intermediate layer, and first Semiconductor substrate and second Semiconductor substrate are bonded together.
As optional technical scheme, said first Semiconductor substrate and second Semiconductor substrate are made up of identical materials, and have different resistivity, perhaps have different conduction types; The material of said first Semiconductor substrate and second Semiconductor substrate is a monocrystalline silicon.
As optional technical scheme, said first Semiconductor substrate and second Semiconductor substrate are made up of material different, and the concrete technological parameter of said cleaning is to adopt hydrofluoric acid solution to clean more than 1 minute, adopts washed with de-ionized water to be no more than 10 minutes again.
As optional technical scheme, after the bonding step is implemented to finish, further comprise the step of a pair of bonded interface enforcement annealing.
As optional technical scheme, after the bonding step is implemented to finish, further comprise the step of attenuate first Semiconductor substrate or second Semiconductor substrate.
The invention has the advantages that the preparation method who has proposed a kind of multi-lager semiconductor substrate; With forming natural oxidizing layer in first Semiconductor substrate and/or second Semiconductor substrate immersion oxidizing solution or the oxidizing gas; And enforcement bonding; This substrate promptly has sandwich construction, and bilevel electricity and crystallographic properties by before first Semiconductor substrate and the decision of second Semiconductor substrate, the method that is provided has the advantage of low cost, high efficiency and process stabilizing.
The present invention has further proposed after bonding, to implement the step of annealing; Can further promote in the multi-lager semiconductor substrate two-layer between fusion on the lattice yardstick; Can see obviously that from the TEM photo that is obtained bonded interface oxygen has melted, lattice is continuous.
Description of drawings
Accompanying drawing 1 is the implementation step sketch map of embodiment according to the invention.
Accompanying drawing 2A is the process schematic representation of embodiment according to the invention to accompanying drawing 2E.
Accompanying drawing 3 be in the embodiment according to the invention the multi-lager semiconductor substrate at multilayer projection electron microscope (TEM) photo at the interface.
Embodiment
Next combine accompanying drawing to introduce the preparation method's of a kind of multi-lager semiconductor substrate according to the invention embodiment in detail.
Be the implementation step sketch map of embodiment according to the invention shown in the accompanying drawing 1, comprise: step S10 provides first Semiconductor substrate and second Semiconductor substrate; Step S11 adopts hydrofluoric acid solution and deionized water rinsing with first Semiconductor substrate and second Semiconductor substrate, to form the bonding medium layer of oxidation on the surface that is cleaned; Step S12 is the intermediate layer with the bonding medium layer, and first Semiconductor substrate and second Semiconductor substrate are bonded together; Step S13, annealing is implemented at the para-linkage interface; Step S14, attenuate first Semiconductor substrate or second Semiconductor substrate.
Accompanying drawing 2A is to shown in the accompanying drawing 2E being the process schematic representation of this embodiment.
Shown in the accompanying drawing 2A, refer step S10 provides first Semiconductor substrate 100 and second Semiconductor substrate 200.Above-mentioned two Semiconductor substrate are intended to constitute respectively two different semiconductor layers of multi-lager semiconductor substrate; So first Semiconductor substrate 100 can be made up of identical or material different with second Semiconductor substrate 200; At both is under the situation of same material formation; Should have different resistivity separately, perhaps have different conduction types, perhaps on other crystallography or electricity index, there are differences.Under first Semiconductor substrate 100 situation identical with the material of second Semiconductor substrate 200, both materials for example can be monocrystalline silicon.
Shown in the accompanying drawing 2B, refer step S11 adopts hydrofluoric acid solution and deionized water rinsing with first Semiconductor substrate 100 and second Semiconductor substrate 200, to form the bonding medium layer 101 of oxidation on the surface.With the monocrystalline substrate is example, and the concrete technological parameter of cleaning is that HF cleaned more than 1 minute, adopts washed with de-ionized water to be no more than 10 minutes again, and the thickness of the bonding medium layer that is obtained is normally less than 0.5nm's.Oxygen content, temperature and backing material in above scavenging period and hydrofluoric acid solution concentration, the deionized water all have substantial connection, need those skilled in that art to adjust according to the oxidated layer thickness that reality obtained.In general, HF is for cleaning action is played on the surface, increase the hydrofluoric acid time to help obtaining clean Surface, and the time that increases washed with de-ionized water helps increasing the thickness of the bonding medium layer 101 of surface oxidation.Between above-mentioned HF cleaning and deionized water rinsing; Can further include the step of Ammonia flushing and the step of monochlor(in)ate hydrogen solution flushing; The purpose that above-mentioned two kinds of solution clean is to improve the cleannes on surface; The concentration of two kinds of cleaning fluids and scavenging period can be confirmed through experiment, be advisable with the not obvious bonding medium layer that thickens.This embodiment is that example is described with first Semiconductor substrate 100; In other execution mode; Also can be to form the bonding medium layer, perhaps all form the bonding medium layer on the surface of first Semiconductor substrate 100 and second Semiconductor substrate 200 on second Semiconductor substrate, 200 surfaces.In that first Semiconductor substrate 100 is immersed in the oxidizing solutions, should all form the bonding medium layer on its two surfaces, the narration of subsequent step for ease among the accompanying drawing 2B only shows the bonding medium layer 101 on a surface.Because the bonding medium layer forms in oxidizing solution or oxidizing gas naturally; So thickness is normally less than 0.5nm's; Drawn a thicker bonding medium layer 101 among the accompanying drawing 2B for clarity; This and do not mean that bonding medium layer 101 and first Semiconductor substrate 100 between thickness have so proportionate relationship, and just explain for ease and the signal made.
Shown in the accompanying drawing 2C, refer step S12 is the intermediate layer with bonding medium layer 101, and first Semiconductor substrate 100 and second Semiconductor substrate 120 are bonded together.For the situation that two surfaces all have the bonding medium layer, should whether be that polished surface is selected bonding face for example according to other character on surface, for the twin polishing substrate, can choose any one surface certainly as bonding surface.Owing in the last step first Semiconductor substrate 100 is immersed in oxidizing solution or the oxidizing gas; Substrate surface is not brought any extra contamination; This bonding step immerse in the oxidizing solution it even the effect of in addition surface being cleaned, so can be implemented immediately after step S11 implements to finish and needn't implement extra cleaning step again.First Semiconductor substrate 100 after bonding finishes and second Semiconductor substrate 200 have promptly formed the Semiconductor substrate of multilayer; After follow-up attenuate and polishing; This substrate promptly has sandwich construction, and bilevel electricity and crystallographic properties by before first Semiconductor substrate 100 determine with second Semiconductor substrate 200.If first Semiconductor substrate 100 before and second Semiconductor substrate 200 have different electrical conductivity, the multi-lager semiconductor substrate that is then obtained also has the conductivity of multilayer.
Before step S11 implements, can also further select to be mixed in the surface of first Semiconductor substrate 100 or second Semiconductor substrate 120, the method that can select to inject or spread is implemented.First Semiconductor substrate 100 after the doping or second Semiconductor substrate 120 itself promptly have the double-decker of different electric conductance; Again both are bonded together; Promptly formed and have three layers the Semiconductor substrate of (selecting one of which to mix) even four layers (both all mix), the three-layer semiconductor structure that has the heavy doping interlayer for the centre especially has important use for IGBT constant power device and is worth.
Shown in the accompanying drawing 2D, refer step S13, annealing is implemented at the para-linkage interface.Annealing temperature is preferably greater than 1000 ℃, so that the bonding medium layer 101 that bonded interface is reinforced the oxidation formation of annealing rear interface place at high temperature melts latticeization, does not influence the subsequent device performance.Because bonding medium layer 101 at the interface forms through autoxidation; Thinner thickness; So the oxygen atom that is wherein contained can be diffused in annealing process and go in the lattice; By the lattice atoms dilution, and then make the lattice of first Semiconductor substrate 100 and second Semiconductor substrate 200 can keep continuous at the interface.Accompanying drawing 3 is projection electron microscope at the interface (TEM) photos after the annealing, can see obviously that therefrom bonded interface oxygen melts, and lattice is continuous.So the step of annealing can further promote in the multi-lager semiconductor substrate two-layer between fusion on the lattice yardstick.
Shown in the accompanying drawing 2E, refer step S14, attenuate first Semiconductor substrate 100 and second Semiconductor substrate 200.The thickness of attenuate confirms that according to the needs of practical application in the process of wafer processing, this thickness all is given by the client of this wafer of needs usually, and attenuate can at first adopt mechanical reduction, implements chemico-mechanical polishing again and carries out Surface Finishing.Before attenuate, can also further implement chamfer angle technique as required.
After the attenuate, can also introduce semi-conductive substrate again and repeat to implement above-mentioned autoxidation technology, bonding technology and doping process, further formation has the Semiconductor substrate of more laminations.
In sum; Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention, to have common knowledge the knowledgeable in the technical field under the present invention, not break away from the spirit and scope of the present invention; When can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining that claims apply for.
Claims (9)
1. the preparation method of a multi-lager semiconductor substrate is characterized in that, comprises the steps: to provide first Semiconductor substrate and second Semiconductor substrate; In first Semiconductor substrate and second Semiconductor substrate at least one washed, and said flushing comprises the step of hydrofluoric acid solution flushing and the step of a deionized water rinsing successively, to form the bonding medium layer of oxidation on the surface that is cleaned; With the bonding medium layer is the intermediate layer, and first Semiconductor substrate and second Semiconductor substrate are bonded together.
2. the preparation method of multi-lager semiconductor substrate according to claim 1 is characterized in that, said first Semiconductor substrate and second Semiconductor substrate are made up of identical materials, and has different resistivity.
3. the preparation method of multi-lager semiconductor substrate according to claim 1 is characterized in that, said first Semiconductor substrate and second Semiconductor substrate are made up of identical materials, and has different conduction types.
4. according to the preparation method of claim 2 or 3 described multi-lager semiconductor substrates, it is characterized in that the material of said first Semiconductor substrate and second Semiconductor substrate is a monocrystalline silicon.
5. the preparation method of multi-lager semiconductor substrate according to claim 4 is characterized in that, the scavenging period of said hydrofluoric acid solution rinsing step is more than 1 minute, and the scavenging period of said deionized water rinsing step is no more than 10 minutes.
6. the preparation method of multi-lager semiconductor substrate according to claim 1 is characterized in that, said first Semiconductor substrate and second Semiconductor substrate are made up of material different.
7. the preparation method of multi-lager semiconductor substrate according to claim 1 is characterized in that, after the bonding step is implemented to finish, further comprises the step of a pair of bonded interface enforcement annealing.
8. the preparation method of multi-lager semiconductor substrate according to claim 1 is characterized in that, after the bonding step is implemented to finish, further comprises the step of attenuate first Semiconductor substrate or second Semiconductor substrate.
9. the preparation method of multi-lager semiconductor substrate according to claim 1; It is characterized in that; Said with at least one step of washing in first Semiconductor substrate and second Semiconductor substrate; Between the step of the step of said hydrofluoric acid solution flushing and deionized water rinsing, the step that the step that further comprises Ammonia flushing and monochlor(in)ate hydrogen solution wash.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110238030A CN102315096A (en) | 2011-08-19 | 2011-08-19 | Preparation method of multilayer semiconductor substrate |
| PCT/CN2012/073866 WO2013026277A1 (en) | 2011-08-19 | 2012-04-12 | Preparation method of multilayer semiconductor substrate |
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| CN201110238030A CN102315096A (en) | 2011-08-19 | 2011-08-19 | Preparation method of multilayer semiconductor substrate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013026277A1 (en) * | 2011-08-19 | 2013-02-28 | 上海新傲科技股份有限公司 | Preparation method of multilayer semiconductor substrate |
| CN103208737A (en) * | 2012-12-20 | 2013-07-17 | 上海显恒光电科技股份有限公司 | Manufacturing method for ultraviolet light output screen and manufactured ultraviolet light output screen and application |
| CN104637813A (en) * | 2013-11-13 | 2015-05-20 | 江苏物联网研究发展中心 | IGBT (insulated gate bipolar translator) manufacturing method |
| CN105374862A (en) * | 2014-09-01 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic apparatus |
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| CN1086926A (en) * | 1992-11-10 | 1994-05-18 | 东南大学 | Silicon chip directive bonding method |
| US20050042841A1 (en) * | 2002-07-24 | 2005-02-24 | International Business Machines Corporation | SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer |
| US20100072580A1 (en) * | 2006-06-14 | 2010-03-25 | Intel Corporation | Ultra-thin oxide bonding for si to si dual orientation bonding |
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| JP2002184960A (en) * | 2000-12-18 | 2002-06-28 | Shin Etsu Handotai Co Ltd | Manufacturing method of soi wafer and soi wafer |
| JP2011103409A (en) * | 2009-11-11 | 2011-05-26 | Sumco Corp | Wafer laminating method |
| CN101799381B (en) * | 2010-03-02 | 2012-03-14 | 上海新傲科技股份有限公司 | Method for forming oxide layer on surface of silicon wafer |
| CN102130037B (en) * | 2010-12-27 | 2013-03-13 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process |
| CN102315096A (en) * | 2011-08-19 | 2012-01-11 | 上海新傲科技股份有限公司 | Preparation method of multilayer semiconductor substrate |
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2011
- 2011-08-19 CN CN201110238030A patent/CN102315096A/en active Pending
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2012
- 2012-04-12 WO PCT/CN2012/073866 patent/WO2013026277A1/en active Application Filing
Patent Citations (3)
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| CN1086926A (en) * | 1992-11-10 | 1994-05-18 | 东南大学 | Silicon chip directive bonding method |
| US20050042841A1 (en) * | 2002-07-24 | 2005-02-24 | International Business Machines Corporation | SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer |
| US20100072580A1 (en) * | 2006-06-14 | 2010-03-25 | Intel Corporation | Ultra-thin oxide bonding for si to si dual orientation bonding |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013026277A1 (en) * | 2011-08-19 | 2013-02-28 | 上海新傲科技股份有限公司 | Preparation method of multilayer semiconductor substrate |
| CN103208737A (en) * | 2012-12-20 | 2013-07-17 | 上海显恒光电科技股份有限公司 | Manufacturing method for ultraviolet light output screen and manufactured ultraviolet light output screen and application |
| CN104637813A (en) * | 2013-11-13 | 2015-05-20 | 江苏物联网研究发展中心 | IGBT (insulated gate bipolar translator) manufacturing method |
| CN104637813B (en) * | 2013-11-13 | 2019-10-01 | 江苏物联网研究发展中心 | The production method of IGBT |
| CN105374862A (en) * | 2014-09-01 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic apparatus |
| CN105374862B (en) * | 2014-09-01 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic device |
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| WO2013026277A1 (en) | 2013-02-28 |
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Application publication date: 20120111 |