CN101496166B - 具有用于键合的相邻贮存器的半导体互连及形成方法 - Google Patents

具有用于键合的相邻贮存器的半导体互连及形成方法 Download PDF

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CN101496166B
CN101496166B CN2006800518156A CN200680051815A CN101496166B CN 101496166 B CN101496166 B CN 101496166B CN 2006800518156 A CN2006800518156 A CN 2006800518156A CN 200680051815 A CN200680051815 A CN 200680051815A CN 101496166 B CN101496166 B CN 101496166B
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layer
dielectric layer
dielectric
mask layer
opening
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CN101496166A (zh
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R·查特杰
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
CN2006800518156A 2006-01-25 2006-12-07 具有用于键合的相邻贮存器的半导体互连及形成方法 Active CN101496166B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/339,132 2006-01-25
US11/339,132 US7579258B2 (en) 2006-01-25 2006-01-25 Semiconductor interconnect having adjacent reservoir for bonding and method for formation
PCT/US2006/061737 WO2007100404A2 (en) 2006-01-25 2006-12-07 Semiconductor interconnect having adjacent reservoir for bonding and method for formation

Publications (2)

Publication Number Publication Date
CN101496166A CN101496166A (zh) 2009-07-29
CN101496166B true CN101496166B (zh) 2010-11-03

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US (2) US7579258B2 (OSRAM)
JP (1) JP5138611B2 (OSRAM)
CN (1) CN101496166B (OSRAM)
TW (1) TWI415216B (OSRAM)
WO (1) WO2007100404A2 (OSRAM)

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Publication number Priority date Publication date Assignee Title
US8134235B2 (en) * 2007-04-23 2012-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional semiconductor device
US8053900B2 (en) * 2008-10-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect
US8796822B2 (en) * 2011-10-07 2014-08-05 Freescale Semiconductor, Inc. Stacked semiconductor devices
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
US10636767B2 (en) * 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
KR102724620B1 (ko) * 2019-11-19 2024-11-01 에스케이하이닉스 주식회사 반도체 메모리 장치
GB2589329B (en) * 2019-11-26 2022-02-09 Plessey Semiconductors Ltd Substrate bonding

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US5817572A (en) * 1992-06-29 1998-10-06 Intel Corporation Method for forming multileves interconnections for semiconductor fabrication
US6232219B1 (en) * 1998-05-20 2001-05-15 Micron Technology, Inc. Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

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JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JPH04258125A (ja) * 1991-02-13 1992-09-14 Nec Corp 半導体装置
US6097096A (en) * 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JP2002026056A (ja) * 2000-07-12 2002-01-25 Sony Corp 半田バンプの形成方法及び半導体装置の製造方法
DE10118422B4 (de) * 2001-04-12 2007-07-12 Infineon Technologies Ag Verfahren zur Herstellung einer strukturierten metallhaltigen Schicht auf einem Halbleiterwafer
JP3735547B2 (ja) * 2001-08-29 2006-01-18 株式会社東芝 半導体装置及びその製造方法
US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7307005B2 (en) * 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
EP1732116B1 (en) * 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817572A (en) * 1992-06-29 1998-10-06 Intel Corporation Method for forming multileves interconnections for semiconductor fabrication
US6232219B1 (en) * 1998-05-20 2001-05-15 Micron Technology, Inc. Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

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US20070170585A1 (en) 2007-07-26
US20070170584A1 (en) 2007-07-26
US7579258B2 (en) 2009-08-25
CN101496166A (zh) 2009-07-29
JP5138611B2 (ja) 2013-02-06
WO2007100404A2 (en) 2007-09-07
JP2009524932A (ja) 2009-07-02
US7514340B2 (en) 2009-04-07
TWI415216B (zh) 2013-11-11
TW200746358A (en) 2007-12-16
WO2007100404A3 (en) 2008-10-09

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