CN101477505B - 一种主、从设备之间通过总线传输数据的方法 - Google Patents
一种主、从设备之间通过总线传输数据的方法 Download PDFInfo
- Publication number
- CN101477505B CN101477505B CN2008102405558A CN200810240555A CN101477505B CN 101477505 B CN101477505 B CN 101477505B CN 2008102405558 A CN2008102405558 A CN 2008102405558A CN 200810240555 A CN200810240555 A CN 200810240555A CN 101477505 B CN101477505 B CN 101477505B
- Authority
- CN
- China
- Prior art keywords
- data
- slave unit
- main equipment
- transmission
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 259
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000012546 transfer Methods 0.000 claims description 28
- 238000007689 inspection Methods 0.000 claims description 22
- 230000015654 memory Effects 0.000 claims description 21
- 238000005070 sampling Methods 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 8
- 230000000977 initiatory effect Effects 0.000 claims description 7
- 238000012163 sequencing technique Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 description 10
- 241001269238 Data Species 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 230000001976 improved effect Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
Images
Landscapes
- Bus Control (AREA)
Abstract
Description
信号 | 信号源 | 总线宽度 | 说明 |
avalid | 主设备 | 1 | the master request data access to slave |
addr | 主设备 | 32 | the access start address |
len | 主设备 | 4 | the number of beat transfers that occur withineach burstb0000:1b0001:2b0010:3 … …b1101:14b1110:15b1111:16 |
write | 主设备 | 1 | write enable,1:write;0:read |
aready | 从设备 | 1 | the address information is captured by MARB |
信号名称 | 信号源 | 总线宽度 | 含义 |
wvalid | 主设备 | 1 | the write data from master is ready |
wstrb | 主设备 | 4 | the write strobe,indicates which byte lanes toupdate in memory.wstrb[n](n=0,1,2,3)1:the byte write is masked,can not update inmemory0:the byte write is enable,update into memory |
wdata | 主设备 | 32 | the write data |
wready | 从设备 | 1 | the write data has been captured by slave |
信号名称 | 信号源 | 总线位宽 | 说明 |
rvalid | 从设备 | 1 | read data from slave is ready for master to get |
rdata | 从设备 | 32 | the read data |
rready | 主设备 | 1 | the read data has been captured by master |
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008102405558A CN101477505B (zh) | 2008-12-23 | 2008-12-23 | 一种主、从设备之间通过总线传输数据的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008102405558A CN101477505B (zh) | 2008-12-23 | 2008-12-23 | 一种主、从设备之间通过总线传输数据的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101477505A CN101477505A (zh) | 2009-07-08 |
CN101477505B true CN101477505B (zh) | 2012-11-21 |
Family
ID=40838224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008102405558A Expired - Fee Related CN101477505B (zh) | 2008-12-23 | 2008-12-23 | 一种主、从设备之间通过总线传输数据的方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101477505B (zh) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103106113A (zh) * | 2013-02-25 | 2013-05-15 | 广东威创视讯科技股份有限公司 | 一种中断事件处理方法和处理设备 |
CN103729319A (zh) * | 2013-12-04 | 2014-04-16 | 上海斐讯数据通信技术有限公司 | 基于串行总线的设备系统及数据传输方法 |
US9697141B2 (en) * | 2014-10-17 | 2017-07-04 | Sk Hynix Memory Solutions Inc. | LBA blocking table for SSD controller |
CN104836710B (zh) * | 2015-02-10 | 2018-06-05 | 数据通信科学技术研究所 | 一种基于分布式系统一主多从通信的方法与装置 |
CN108920982B (zh) * | 2015-10-30 | 2021-08-17 | 深圳国微技术有限公司 | 一种用于安全芯片的防篡改屏蔽层 |
CN105608027B (zh) * | 2015-12-18 | 2018-10-19 | 华为技术有限公司 | 非易失存储设备和访问非易失存储设备的方法 |
CN106569974A (zh) * | 2016-11-02 | 2017-04-19 | 深圳市博巨兴实业发展有限公司 | 一种软硬件接口协议 |
CN108228492B (zh) * | 2016-12-21 | 2020-11-17 | 深圳市中兴微电子技术有限公司 | 一种多通道ddr交织控制方法及装置 |
CN108363670B (zh) * | 2017-01-26 | 2020-07-14 | 华为技术有限公司 | 一种数据传输的方法、装置、设备和系统 |
CN107301143B (zh) * | 2017-05-08 | 2020-09-04 | 浙江大学 | 一种基于双轨编码四相握手协议的异步仲裁器 |
US10372663B2 (en) * | 2017-07-25 | 2019-08-06 | Qualcomm Incorporated | Short address mode for communicating waveform |
CN108595350B (zh) * | 2018-01-04 | 2022-04-05 | 深圳开阳电子股份有限公司 | 一种基于axi的数据传输方法和装置 |
CN108319430B (zh) * | 2018-01-17 | 2021-03-23 | 杭州宏杉科技股份有限公司 | 处理io请求的方法及装置 |
CN108763140B (zh) * | 2018-04-23 | 2021-02-12 | 深圳市文鼎创数据科技有限公司 | 一种双向通信的方法、系统及终端设备 |
CN109344093B (zh) * | 2018-09-13 | 2022-03-04 | 苏州盛科通信股份有限公司 | 缓存结构、读写数据的方法和装置 |
CN109471824B (zh) * | 2018-11-22 | 2021-02-05 | 青岛方寸微电子科技有限公司 | 基于axi总线的数据传输系统及方法 |
CN110737622B (zh) * | 2019-10-15 | 2021-05-07 | 上海智汇电器有限公司 | 一种单线双向通讯充电方法 |
CN111752875A (zh) * | 2020-06-22 | 2020-10-09 | 深圳鲲云信息科技有限公司 | 一种模块间通信方法及系统 |
CN111913902B (zh) * | 2020-08-05 | 2021-11-12 | 青岛信芯微电子科技股份有限公司 | 应用于SoC芯片的控制总线时序的装置 |
CN111984562B (zh) * | 2020-09-07 | 2022-05-10 | 苏州盛科通信股份有限公司 | 寄存器突发访问控制的方法、电子设备及存储介质 |
CN112256426A (zh) * | 2020-10-21 | 2021-01-22 | 广东高云半导体科技股份有限公司 | 具有总线仲裁器的主从通信系统及通信方法 |
CN112948294B (zh) * | 2021-03-19 | 2024-02-09 | 北京控制工程研究所 | 面向SOC的全域并行收发数据的双通道SpaceWire控制器及控制方法 |
CN114840458B (zh) * | 2022-07-06 | 2022-09-20 | 北京象帝先计算技术有限公司 | 读写模块、片上系统和电子设备 |
CN115617718B (zh) * | 2022-12-19 | 2023-03-21 | 芯动微电子科技(珠海)有限公司 | 一种基于AXI总线的读写保序方法及SoC系统 |
CN117435518B (zh) * | 2023-12-21 | 2024-03-22 | 沐曦集成电路(上海)有限公司 | 一种用于主从读写数据的保护方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1947109A (zh) * | 2004-04-28 | 2007-04-11 | 皇家飞利浦电子股份有限公司 | 具有异步/同步接口的电路 |
CN101135993A (zh) * | 2007-09-20 | 2008-03-05 | 华为技术有限公司 | 一种嵌入式系统芯片及数据读写处理方法 |
-
2008
- 2008-12-23 CN CN2008102405558A patent/CN101477505B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1947109A (zh) * | 2004-04-28 | 2007-04-11 | 皇家飞利浦电子股份有限公司 | 具有异步/同步接口的电路 |
CN101135993A (zh) * | 2007-09-20 | 2008-03-05 | 华为技术有限公司 | 一种嵌入式系统芯片及数据读写处理方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101477505A (zh) | 2009-07-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101477505B (zh) | 一种主、从设备之间通过总线传输数据的方法 | |
US20070005922A1 (en) | Fully buffered DIMM variable read latency | |
KR937000918A (ko) | 고성능 버스 인터페이스를 사용하는 집적회로 입출력 | |
US20050177664A1 (en) | Bus system and method thereof | |
CN105224488B (zh) | 一种pci总线控制器及其控制方法 | |
JP4685800B2 (ja) | スケーラブルなバス構造 | |
US5925118A (en) | Methods and architectures for overlapped read and write operations | |
CN105573951B (zh) | 一种针对数据流传输的ahb总线接口系统 | |
US20040205267A1 (en) | Bridge for removing master-induced stalls on a data bus | |
US20130326090A1 (en) | Ring topology status indication | |
CN101446931B (zh) | 一种实现输入输出数据一致性的系统及方法 | |
CN109656851B (zh) | 一种时间确定的包括多路高速总线通道及共享接口的系统 | |
CN104599227A (zh) | 用于高速ccd数据存储的ddr3仲裁控制器及方法 | |
US20020019911A1 (en) | Distributed high-speed memory controller | |
US20060224804A1 (en) | Direct memory access for advanced high speed bus | |
CN114416632A (zh) | 一种基于多总线协议灵活转换的两级缓存互联结构 | |
US20030191884A1 (en) | Bus system and information processing system including bus system | |
US20070101032A1 (en) | Bus arbitration circuit and bus arbitration method | |
US20090265483A1 (en) | Direct memory access for advanced high speed bus | |
KR100438736B1 (ko) | 어드레스 라인을 이용해 데이터 쓰기를 수행하는 메모리제어 장치 | |
US6845418B2 (en) | Bus system for master-slave device accesses, has multiple pseudo-delayer connected to controllers which delay and output access commands to slave devices for having longer latency periods | |
US8127108B2 (en) | Apparatus, system and method for prefetching data in bus system | |
US20050144331A1 (en) | On-chip serialized peripheral bus system and operating method thereof | |
JP4603054B2 (ja) | スケーラブルバス構造 | |
JPS6367042A (ja) | コンピユ−タシステムのデ−タ転送方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: WUXI VIMICRO CO., LTD. Free format text: FORMER OWNER: BEIJING ZHONGXING MICROELECTRONICS CO., LTD. Effective date: 20110406 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100083 16/F, SHINING BUILDING, NO. 35, XUEYUAN ROAD, HAIDIAN DISTRICT, BEIJING TO: 214028 610, NATIONAL INTEGRATED CIRCUIT DESIGN PARK (CHUANGYUAN BUILDING), NO. 21-1, CHANGJIANG ROAD, WUXI NEW DISTRICT, JIANGSU PROVINCE |
|
TA01 | Transfer of patent application right |
Effective date of registration: 20110406 Address after: 214028 national integrated circuit design (21-1), Changjiang Road, New District, Jiangsu, Wuxi, China, China (610) Applicant after: Wuxi Vimicro Co., Ltd. Address before: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Applicant before: Beijing Vimicro Corporation |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address |
Address after: 214135 Taihu International Science Park Sensor Network University Science Park 530 Building A1001, 18 Qingyuan Road, Wuxi, Jiangsu Province Patentee after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: 214028 National Integrated Circuit Design Park (Chuangyuan Building) 610, 21-1 Changjiang Road, New District, Wuxi City, Jiangsu Province Patentee before: Wuxi Vimicro Co., Ltd. |
|
CP03 | Change of name, title or address | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121121 Termination date: 20191223 |