CN101465377A - 半导体器件及其制造方法 - Google Patents
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Abstract
本发明公开了一种半导体器件及其制造方法。该半导体器件包括：半导体衬底；栅电极，包括设置在所述半导体衬底上的主体部和自主体部向下凸出的凸出部；以及源极/漏极区，位于所述栅电极的相对侧。本发明可以减小半导体器件的尺寸。
Description
技术领域
本发明实施例涉及一种半导体器件及其制造方法。
背景技术
最近，用于无线通信设备等的半导体器件等可以在3V到5V电压下工作。而且，还需要一种小且高度集成的半导体器件。
发明内容
本发明的实施例提供一种半导体器件，该半导体器件可在高电压下工作并且可以被高度集成。
本发明提供的半导体器件大体包括：半导体衬底；栅电极，包括位于所述半导体衬底上的主体部和自所述主体部向下凸出的凸出部；以及源极/漏极区，位于所述栅电极的相对侧处的所述半导体衬底中。
本发明又提供一种制造半导体器件的方法，包括以下步骤：在半导体衬底上或在半导体衬底中形成凹槽；形成栅电极，所述栅电极包括位于所述半导体衬底上的主体部和自所述主体部向下凸出的凸出部；以及在所述栅电极的相对侧形成源极/漏极区。
根据本发明的实施例，该半导体器件也可具有一沟道长度，该沟道位于该栅电极的下部或位于栅电极的下部(例如，最下表面)以下。相对于栅极具有平坦的最下表面的传统CMOS晶体管，本发明通常通过该栅电极的凸出部增加了沟道长度。由于增加了沟道长度，因此该半导体器件可在较高电压下工作。
而且，在根据本发明实施例的半导体器件中，即使减小了源极/漏极区之间的长度，沟道的长度也通过栅电极的凸出部变长，从而可以减小半导体器件的尺寸。
附图说明
图1为根据本发明实施例的示例性MOS晶体管的剖面图。
图2a至图2e示出根据本发明实施例的制造NMOS晶体管的示例性方法的剖面图。
具体实施方式
下面将参照附图详细地描述根据本发明实施例的半导体器件及其制造方法。
在各种实施例的描述中，应当理解，当一层(或膜)被指为在另一层或衬底上时，该层(或膜)可以直接位于另一层或衬底上，或者也可以存在一个或多个中间层。
图1为根据本发明实施例的示例性MOS晶体管的剖面图。
参见图1，该MOS晶体管通常包括半导体衬底100、栅电极200、栅极绝缘层230、间隔件240、轻掺杂漏极(LDD)区300、源极/漏极区400以及硅化物层500。
该半导体衬底100可包括单晶硅衬底(例如，晶片)，其上可具有一个或多个Si层、应变Si层或Si-Ge层(例如，外延Si和/或SiGe)。另外，该半导体衬底100可包括包含有轻掺杂n-型区110、器件隔离层130以及p-型阱120的区域100。
可通过LOCOS工艺和/或STI工艺等等形成该器件隔离层130，以隔离该半导体器件。该半导体衬底100还包括有源区(AR)(参见图2a)，其可通过该器件隔离层130来限定。
通常，可通过注入低浓度的p-型杂质(例如B、Ga、In、T1等等)在该有源区(AR)中形成该p-型阱120。
此外，该半导体衬底100包括凹槽170。该凹槽170形成在该p-型阱120上或该p-型阱120中，并且该凹槽170的内侧171的至少一部分具有弯曲的表面(curved surface)。更具体地说，该凹槽170在该半导体衬底100的一个方向上具有更长的长度。此外或可替代地，该凹槽170的整个内侧171可具有弯曲的表面。
栅电极200形成在该半导体衬底100的该有源区(AR)上。优选地，该栅电极200可形成在该凹槽170上或该凹槽170中。该栅电极200可包括多晶硅和/或金属，例如钨、钼、钴、钛、上述金属的硅化物、或者铝或铝合金(例如，铝最多占4％的重量百分比，铜最多占4％的重量百分比，钛最多占2％的重量百分比和/或硅最多1％的占重量百分比)。该金属可位于传统的粘合层和/或阻挡层上(例如Ti和/或TiN，如TiN-Ti双分子层)，和/或被传统的粘合层、阻挡层、小丘抑制(hillock suppression)层和/或抗反射层(例如Ti、TiN、WN、TiW合金、或其任意组合，例如Ti上TiN(TiN-on-Ti)双分子层或Ti上TiW(TiW-on-Ti)双分子层)所覆盖。在示例性的实施中，该栅电极200包括主体部210和凸出部220。
该栅电极200的主体部210位于该半导体衬底100上/该半导体衬底100中，且通常为矩形形状。例如，该主体部210在一个方向上的长度可大于其在正交方向上的宽度，并且该主体部210覆盖该凹槽170。
该栅电极200的该凸出部220与该主体部210一体地形成，并且通常向下凸出。在优选实施例中，该凸出部具有弯曲的表面，并与该凹槽170互补。该凸出部220在与该主体部210相同方向上具有一长度，该长度大于宽度或厚度，且该凸出部220可对应于凹槽170。例如，该凸出部220可位于该凹槽170中并具有与该凹槽170互补的弯曲的表面。
该栅极绝缘层/膜230位于该栅电极200和该半导体衬底100之间。在各种实施中，该栅极绝缘膜230可包括本领域公知的任何适合的材料，例如氧化物(例如，热SiO2)。一部分该栅极绝缘膜230位于该凹槽170内部以及位于该凸出部220的下部。通常，该栅极绝缘层230使该栅电极200和该半导体衬底100彼此绝缘。
间隔件240可设置在该栅电极200的一侧或多侧上。该间隔件240可包括这样的材料：例如正硅酸乙酯(TEOS)、氮化物、其组合、或任意其它适合的材料，用于使栅电极200的一侧或多侧绝缘并在源极/漏极端注入期间充当掩模。
LDD区300形成在阱120中并邻近该栅电极200的下部。LDD区300包括低浓度的n-型杂质(例如磷、砷、锑等等)。在示例性实施例中，晶体管/半导体器件包括一对LDD区，并且LDD区通过该栅极200和器件隔离区130彼此隔开。
在一些实施例中，沟道区(CH)形成在该LDD区300之间并位于该栅电极200的下部以下。
源极/漏极区400形成在该栅电极200的相对侧。此外，该源极/漏极区400可包括高浓度的n-型杂质。而且，该源极/漏极区400邻近该LDD区300。
硅化物层500可形成在栅电极200和/或源极/漏极区400上。该硅化物层500可包括镍(Ni)的硅化物或钛(Ti)的硅化物。该硅化物层500改善了电连接到各个源极/漏极区400和栅电极200的接触电极的电连接。
有利地是，由于沟槽170和凸出部220，根据本发明实施例的NMOS晶体管/半导体器件具有相对长的沟道长度。因此，即使将高电压应用施加到该源极/漏极区400上，根据本发明的NMOS晶体管也可防止对沟道区(CH)的击穿现象(punch through phenomenon)。
本发明的NMOS晶体管可在高电压下工作。
此外，由于该凹槽170和该凸出部220包括弯曲的表面，所以可以减少在该栅电极200中流动的电子数量。换句话说，由于位于该凹槽170内部的该栅极绝缘层230具有与该凹槽170互补的弯曲的表面，所以通过该沟道区(CH)的电子可能在绝缘层上碰撞，但不会通过该栅极绝缘层230。因此，不会降低本发明的NMOS晶体管的性能。
另外，可通过该凹槽170和该凸出部220增加沟道长度，从而可以减小该栅电极200的宽度。换句话说，相比不具有该凹槽170和该凸出部220的传统NMOS晶体管，本发明的NMOS晶体管的栅电极的宽度可减小。因此，本发明的NMOS晶体管的尺寸可相对较小并且被高度集成。
图2a至图2e示出制造NMOS晶体管/半导体器件的示例性方法的剖面图。
参见图2a，将低浓度的p-型杂质选择性地注入到包括低浓度的n-型杂质的衬底中，从而在衬底100中形成包括n-型杂质的区域110和p-型阱120。
之后，在p-型阱120和包括n-型杂质110的区域110之间的衬底中，图案化并蚀刻一沟槽。在该沟槽中沉积绝缘材料(例如二氧化硅)，以形成一个或多个器件隔离层130。可通过该一个或多个器件隔离层130限定该有源区(AR)。从而形成了具有该包括n-型杂质的区域110、该p-型阱120以及该器件隔离层130的衬底100。
之后，可在该半导体衬底100上沉积至少一个绝缘层(例如，第一氧化物层140和/或氮化物层150)。然后，选择性地蚀刻该绝缘层(例如，图2a中的该第一氧化物层/膜140和该氮化物层150)，以暴露一部分p-型阱120。通常，该p-型阱120暴露的部分在一个方向上的长度大于其在正交方向上的宽度(示出)。
之后，将暴露的p-型阱120的一部分氧化，并且可通过热氧化工艺形成第二氧化物层160。具体而言，暴露的p-型阱120的一部分与氧反应，以形成第二氧化物层160。在氧化之前，可将小凹陷蚀刻至p-型阱120中。
参见图2b，去除该第一氧化物层140、该氮化物层150以及该第二氧化物层160，以在该半导体衬底100上/中形成该凹槽170。该凹槽170的深度约为100
至1000，优选为150-500。
在一个方案中，该凹槽170具有弯曲的表面。换句话说，凹槽170的中心部分比该凹槽170的一个或多个边缘深。此外，该凹槽170的整个内侧171可具有弯曲的表面，并且该凹槽170的长度大于宽度。
参见图2c，在形成该凹槽170之后，可在该半导体衬底100上形成第三氧化物层。该第三氧化物层形成在该凹槽170内部，并与该凹槽170的内侧171互补。
之后，在第三氧化物层上形成多晶硅层。该多晶硅层填充该凹槽170的内部。该多晶硅层的主体部可为1500到8000。然后，通过掩模工艺，图案化该第三氧化物层和该多晶硅层，以形成栅极绝缘层230和栅电极200。该栅电极200包括主体部210和自主体部210向下凸出的凸出部220。该栅极绝缘层230位于该栅电极200和该半导体衬底100之间。
该栅电极的该凸出部220可与该凹槽170互补，并且在与该凹槽170相对应的方向上具有更长的长度。此外，该栅电极的该凸出部220具有弯曲的表面221。
之后，使用该栅电极200作为掩模，将低浓度的n-型杂质注入到该有源区(AR)中。然后，通过热处理(或退火)工艺使注入的该n-型杂质扩散，以形成LDD区300。
参见图2d，可通过在该衬底上沉积一层或多层膜(例如TEOS膜和/或氮化物膜)，在该栅电极200的一侧或多侧形成间隔件240。可在该衬底的该有源区(AR)上顺序堆叠这些膜，并通过各向异性蚀刻工艺蚀刻该TEOS膜和该氮化物膜。
之后，使用该间隔件240作为离子注入掩模，将高浓度的n-型杂质注入到该有源区(AR)。然后，通过热处理工艺或本领域公知的任何其它工艺，使注入的高浓度n-型杂质扩散到有源区(AR)的一侧或两侧，从而在该栅电极200的相对侧形成源极/漏极区400。
参见图2e，通过快速热处理(RTP)等等，在该有源区(AR)上形成非反应金属层，并在该栅电极200和该源极/漏极区400形成硅化物层500。
之后，通过清洗工艺去除该非反应金属层。
说明书中所涉及的“一实施例”、“实施例”、“示例性实施例”等，其含义是结合实施例描述的特定特征、结构、或特性均包括在本发明的至少一个实施例中。说明书中出现于各处的这些短语并不一定都涉及同一个实施例。此外，当结合任何实施例描述特定特征、结构或特性时，都认为其落在本领域技术人员结合其它实施例就可以实现这些特征、结构或特性的范围内。
尽管对实施例的描述中结合了其中多个示例性实施例，但可以理解的是本领域技术人员完全可以推导出许多其它变化和实施例，并落入本公开内容的原理的精神和范围之内。尤其是，可以在该公开、附图和所附权利要求的范围内对组件和/或附件组合设置中的设置进行多种变化和改进。除组件和/或设置的变化和改进之外，其他可选择的应用对于本领域技术人员而言也是显而易见的。
Claims (20)
1.一种半导体器件，包括：
半导体衬底；
栅电极，所述栅电极包括位于所述半导体衬底上的主体部和自所述主体部向下凸出的凸出部；以及
源极/漏极区，位于所述栅电极的相对侧处的所述半导体衬底中。
2.如权利要求1所述的半导体器件，其中所述凸出部具有弯曲的表面。
3.如权利要求1所述的半导体器件，其中所述半导体衬底包括凹槽，所述凹槽的内侧具有弯曲的表面。
4.如权利要求3所述的半导体器件，其中所述凸出部与所述凹槽互补。
5.如权利要求3所述的半导体器件，其中所述主体部为矩形形状并覆盖所述凹槽。
6.如权利要求3所述的半导体器件，还包括：栅极绝缘层，位于所述半导体衬底和所述栅电极之间。
7.如权利要求6所述的半导体器件，其中一部分所述栅极绝缘层位于所述凹槽内部。
8.如权利要求1所述的半导体器件，其中所述半导体衬底包括n-型杂质区、器件隔离层以及p-型阱。
9.如权利要求8所述的半导体器件，其中所述器件隔离层用于限定有源区。
10.如权利要求1所述的半导体器件，还包括：间隔件，位于所述栅电极的相对侧上。
11.如权利要求10所述的半导体器件，还包括：轻掺杂漏极区，位于所述间隔件下方的所述衬底中。
12.如权利要求1所述的半导体器件，还包括：硅化物层，位于所述栅电极和/或所述源极/漏极区上。
13.一种半导体器件的制造方法，包括以下步骤：
在半导体衬底上形成凹槽；
在所述半导体衬底上形成栅电极，所述栅电极包括位于所述半导体衬底上的主体部和自所述主体部向下凸出至所述凹槽的凸出部；以及
在所述栅电极的相对侧处的所述半导体衬底中形成源极/漏极区。
14.如权利要求13所述的半导体器件的制造方法，其中形成所述凹槽的步骤包括：
通过热氧化工艺，在所述半导体衬底上选择性地形成至少一个绝缘层；以及
去除所述绝缘层。
15.如权利要求13所述的半导体器件的制造方法，其中所述凹槽的内侧具有弯曲的表面。
16.如权利要求13所述的半导体器件的制造方法，其中所述栅电极的所述凸出部填充所述凹槽。
17.如权利要求13所述的半导体器件的制造方法，还包括在所述半导体衬底上和所述凹槽的内部形成栅极绝缘层。
18.如权利要求13所述的半导体器件的制造方法，还包括在所述半导体衬底中形成n-型杂质区、器件隔离层以及p-型阱。
19.如权利要求13所述的半导体器件的制造方法，还包括在所述栅电极的相对侧上形成间隔件。
20.如权利要求19所述的半导体器件的制造方法，还包括在与所述栅电极相邻的所述衬底中形成轻掺杂漏极区。
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| KR1020070131938A KR20090064658A (ko) | 2007-12-17 | 2007-12-17 | 반도체 소자 및 이의 제조방법 |
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| US (1) | US20090152648A1 (zh) |
| KR (1) | KR20090064658A (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112909088A (zh) * | 2021-01-25 | 2021-06-04 | 深圳大学 | 静电感应晶体管及其制备方法 |
| CN114270544A (zh) * | 2019-08-09 | 2022-04-01 | 欧司朗光电半导体有限公司 | 具有减少的吸收的器件和用于制造器件的方法 |
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| JP5434365B2 (ja) * | 2009-08-24 | 2014-03-05 | ソニー株式会社 | 半導体装置及びその製造方法 |
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| US5552329A (en) * | 1994-01-05 | 1996-09-03 | Lg Semicon Co., Ltd. | Method of making metal oxide semiconductor transistors |
| KR100521369B1 (ko) * | 2002-12-18 | 2005-10-12 | 삼성전자주식회사 | 고속도 및 저전력 소모 반도체 소자 및 그 제조 방법 |
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| CN114270544A (zh) * | 2019-08-09 | 2022-04-01 | 欧司朗光电半导体有限公司 | 具有减少的吸收的器件和用于制造器件的方法 |
| CN112909088A (zh) * | 2021-01-25 | 2021-06-04 | 深圳大学 | 静电感应晶体管及其制备方法 |
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| US20090152648A1 (en) | 2009-06-18 |
| TW200929382A (en) | 2009-07-01 |
| KR20090064658A (ko) | 2009-06-22 |
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