CN114078772A - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

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CN114078772A
CN114078772A CN202110935630.8A CN202110935630A CN114078772A CN 114078772 A CN114078772 A CN 114078772A CN 202110935630 A CN202110935630 A CN 202110935630A CN 114078772 A CN114078772 A CN 114078772A
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王宝明
邱哲夫
聂俊峰
张惠政
杨育佳
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置的形成方法，包括：布植第一导电类型的多个掺质到半导体基底中，以形成第一井，外延成长通道层于上述半导体基底上，以及形成栅极结构于上述鳍片的通道区域之上。上述半导体基底包括第一半导体材料。布植上述掺质的步骤是在150℃至500℃的范围内的温度下进行。上述通道层包括第二半导体材料。上述通道层受到上述第一导电类型的上述掺质所掺杂。

Description

半导体装置的形成方法
技术领域
本发明实施例是有关于一种半导体装置及其形成方法，特别是有关于可控制触发电压的鳍式场效晶体管及其形成方法。
背景技术
半导体装置使用于各种电子应用中，例如，个人电脑、移动电话、数码相机及其他电子设备。半导体装置通常通过以下方式而制造，包括在半导体基底上依序沉积绝缘或介电层、导电层及半导体层，并且使用微影制程将上述各材料层图案化，借以在此半导体基底上形成电路组件及元件。
半导体产业通过不断降低最小部件尺寸以持续提高各种电子组件(例如，晶体管、二极管、电阻、电容等)的集成密度，这允许将更多的部件集积到特定区域中。
发明内容
在本发明实施例的一实施形态中，提供一种半导体装置的形成方法。此半导体装置的形成方法包括：布植第一导电类型的多个掺质到半导体基底中，以形成第一井，其中上述半导体基底包括第一半导体材料，布植上述第一导电类型的上述掺质的步骤是在150℃至500℃的范围内的温度下进行；外延成长通道层于上述半导体基底上，其中上述通道层包括第二半导体材料，上述通道层受到上述第一导电类型的上述掺质所掺杂；从上述第二半导体材料形成鳍片；以及形成栅极结构于上述鳍片的通道区域之上，并且形成多个源极/漏极区域于上述该通道区域的相对两侧上的上述鳍片之上，其中上述源极/漏极区域受到第二导电类型的多个掺质所掺杂。
在本发明实施例的另一实施形态中，提供一种半导体装置的形成方法。此半导体装置的形成方法包括：形成第一掩膜于基底的第一区域及第二区域之上；形成第二掩膜于上述基底的上述第一区域中的上述第一掩膜之上；在上述第二区域中以1.5×1014cm-2至3.0×1014cm-2的剂量布植第一掺质，以形成第一井，上述布植是在170℃至500℃的范围内的温度下进行，其中上述布植是通过驱动上述第一掺质穿过上述第一掩膜而进行；移除上述第二掩膜；移除上述第一掩膜；以及形成第一鳍片于上述第一区域中，且形成第二鳍片于上述第二区域中。
在本发明实施例的又一实施形态中，提供一种半导体装置。此半导体装置包括：半导体基底，上述半导体基底包括第一井，其中上述第一井包括第一掺质，其中上述第一掺质具有浓度在1017原子/cm3至1019原子/cm3范围内，上述第一井具有多个基底缺陷，其中上述基底缺陷具有面积密度在1.0×107cm-2至5.0×107cm-2的范围内；第一鳍片，从上述第一井延伸，其中上述第一掺质的上述浓度以每纳米8×1017原子/cm3至每纳米2×1018原子/cm3的范围内的速率改变而跨越上述第一井与上述第一鳍片之间的一边界；第一源极/漏极区及第二源极/漏极区，其中上述第一源极/漏极区及上述第二源极/漏极区从上述第一鳍片延伸；以及第一栅极电极，位于上述第一鳍片之上。
附图说明
通过以下的详述配合所附图式可更加理解本发明实施例的内容。需注意的是，依据工业上的标准做法，各个部件(feature)并未按照比例绘制。事实上，为了能清楚地讨论，可能任意地放大或缩小各个部件的尺寸。
图1是依据一些实施例的鳍式场效晶体管的示范例的三维立体示意图。
图2、图3、图4、图5、图6、图7及图8是依据一些实施例的制造鳍式场效晶体管的中间阶段的剖面示意图。
图9是依据一些实施例而绘示在鳍式场效晶体管的部分之中的掺质浓度。
图10、图11、图12A、图12B、图13、图14A、图14B、图15A、图15B、图16A、图16B、图16C、图16D、图17A、图17B、图18A、图18B、图19A、图19B、图20A、图20B、图20C、图21A、图21B、图22A及图22B是依据一些实施例的制造鳍式场效晶体管的其他中间阶段的剖面示意图。
其中，附图标记说明如下：
50：基底
50N：N型区域
50P：P型区域
51：分隔线
52：鳍片
54：绝缘材料
56：浅沟槽隔离区域
58：通道区域
60：虚置介电层
62：虚置栅极层
64：掩膜层
72：虚置栅极
74：掩膜
80：栅极密封间隔物
82：源极/漏极区域(外延源极/漏极区域)
86：栅极间隔物
87：接触蚀刻停止层
88：第一层间介电层
89：区域
90：凹口
92：栅极介电层
94：栅极电极
94A：衬层
94B：功函数调整层
94C：填充材料
96：栅极掩膜
108：第二层间介电层
110：栅极接触件
112：源极/漏极接触件
150：第一掩膜(掩膜层)
152：第三掩膜
154：第二掩膜
158：半导体层
200：N型杂质热布植
300：P型杂质布植
602：P型井
604：N型井
具体实施方式
以下公开提供了许多不同的实施例或范例，用于实施本发明实施例中的不同部件。组件与配置的具体范例描述如下，以简化本发明实施例的说明。当然，这些仅仅是范例，并非用以限定本发明实施例。举例而言，当以下叙述中提及第一部件形成于第二部件之上或上方，可能包含上述第一部件与上述第二部件直接接触的实施例，也可能包含有额外的部件形成于上述第一部件与上述第二部件之间，使得上述第一部件与上述第二部件不直接接触的实施例。此外，本发明实施例可能在各种示范例中重复参考标号以及/或字母。如此重复是为了简明和清楚的目的，而非用以表示所讨论的不同实施例及/或配置之间的关系。
再者，在此可使用空间相对用词，例如「在……下方」、「在……下」、「下方的」、「在……上」、「上方的」及类似的用词以助于描述图中所示的其中一个元件或部件相对于另一(些)元件或部件之间的关系。除了在图式中绘示的方位外，这些空间相对用词意欲包含使用中或操作中的装置的不同方位。装置能够以其他方式定向(旋转90度或其他方向)，并且可与其相应地解释在此使用的空间相对的描述。
在本文所公开的实施例提供在升高的温度下进行的井布植，因而减少间隙缺陷(interstitial defect)。可以在较高的剂量条件下进行杂质的布植而形成井区域，以减小井电阻(well resistance)及隔离漏电流(isolation leakage current)，例如，从高掺杂源极/漏极区域到井区域的漏电流，借此实现后续形成的晶体管(例如，金属氧化物半导体场效晶体管(MOSFET))的大于约1.7V的触发电压(trigger voltage；Vtrigger)。在高温(例如，高于约150℃)下进行诸如此类的杂质布植，如此可有利于降低半导体基底内产生的点缺陷(point defect)的密度，其中这些点缺陷是因为布植掺质的重型物种(heavyspecies，例如，砷及磷)而产生的。通过在高于约150℃的高温下进行杂质布植，可以产生更少的基底间隙，如此可以减少基底广延缺陷(extended defect)，例如，在后续热处理制程期间的迭差(stacking fault)及差排(dislocation)，因而提高装置性能。
依据一些实施例，图1以三维立体示意图绘示鳍式场效晶体管(FinFET)的示范例。鳍式场效晶体管包括位于基底50(例如，半导体基底)上的鳍片52。隔离区域56设置于基底50之中，并且鳍片52在相邻的隔离区域56之间朝向上方突出。虽然将隔离区域56描述/绘示为与基底50分离，但是，如本文所使用，技术用语「基底」可用于仅指称半导体基底，或是用于指称包括隔离区域的半导体基底。此外，虽然鳍片52被绘示为与基底50相同的单一连续材料，但是，鳍片52及/或基底50可包括单一材料或多种材料。在此上下文中，鳍片52是指在相邻的隔离区域56之间延伸的部分。
栅极介电层92沿着侧壁并且位在鳍片52的顶表面上方，且栅极电极94位在栅极介电层92之上。源极/漏极区域82设置在相对于栅极介电层92和栅极电极94的鳍片52的两侧。图1进一步绘示在后续的图式中所使用的参考剖面。剖面A-A沿着栅极电极94的纵轴，并且在，例如，垂直于鳍式场效晶体管的源极/漏极区域82之间的电流流动方向的方向上。剖面B-B垂直于剖面A-A，且沿着鳍片52的纵轴，并且在，例如，鳍式场效晶体管的源极/漏极区域82之间的电流流动的方向上。剖面C-C平行于剖面A-A，并且延伸穿过鳍式场效晶体管的源极/漏极区域。为了清楚起见，后续的图式将参考这些参考剖面。
本文所讨论的一些实施例是在使用栅极后制制程(gate-last process)形成的鳍式场效晶体管的背景下讨论的。在其他实施例中，可以使用栅极先制制程(gate-firstprocess)。而且，一些实施例考虑了使用在平面装置中的方面，例如，平面场效晶体管(planar FET)、纳米结构(例如，纳米片、纳米线、全绕式栅极(gate-all-around)等)场效晶体管(nanostructure field effect transistor；NSFET)或其他类似物。
图2到图8及图10到图22B是依据一些实施例的制造鳍式场效晶体管的中间阶段的剖面示意图。图2到图8及图10到图13绘示了图1所绘示的参考剖面A-A，除了多个鳍片/鳍式场效晶体管之外。图14A、图15A、图16A、图17A、图18A、图19A、图20A、图21A及图22A是沿着图1所绘示的参考剖面A-A所绘示。图14B、图15B、图16B、图17B、图18B、图19B、图20B、图20C、图21B及图22B是沿着图1所绘示的参考剖面B-B所绘示，除了多个鳍片/鳍式场效晶体管之外。图16C及图16D是沿着图1所绘示的参考剖面C-C所绘示，除了多个鳍片/鳍式场效晶体管之外。
在图2中，提供基底50。基底50可以是半导体基底，例如，块材(bulk)半导体、绝缘体上覆半导体(semiconductor-on-insulator；SOI)基底或其他类似物，其可以被掺杂(例如，使用P型掺质或N型掺质)或是未经掺杂。基底50可以是晶圆，例如，硅晶圆。通常，绝缘体上覆半导体基底是形成在绝缘体层上的一层半导体材料。绝缘体层可以是，例如，埋藏氧化物(buried oxide；BOX)层、氧化硅层或其他类似物。绝缘层设置在通常为硅或玻璃基底的基底上。也可使用其他基底，例如，多层(multi-layered)基底或渐变(gradient)基底。在一些实施例中，基底50的半导体材料可包括硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟(indium antimonide)；合金半导体，包括硅锗(silicon-germanium)、磷砷化镓(gallium arsenide phosphide)、砷化铟铝(aluminum indiumarsenide)、砷化镓铝(aluminum gallium arsenide)、砷化铟镓(gallium indiumarsenide)、磷化铟镓(gallium indium phosphide)及/或磷砷化铟镓(gallium indiumarsenide phosphide)；或上述的组合。
基底50具有N型区域50N和P型区域50P。N型区域50N可用于形成N型装置，例如，N型金属氧化物半导体(NMOS)晶体管，例如，N型鳍式场效晶体管。P型区域50P可用于形成P型装置，例如，P型金属氧化物半导体(PMOS)晶体管，例如，P型鳍式场效晶体管。N型区域50N可与P型区域50P物理性地分开(如分隔线51所示)，并且可在N型区域50N及P型区域50P与半导体装置之间设置任何数量的装置部件(例如，其他主动装置、掺杂区域、隔离结构等)。
在图3至图5中，可以在鳍片52及/或基底50中形成适当的井区域。在一些实施例中，可形成P型井于N型区域50N中，并且可形成N型井于P型区域50P中。在一些实施例中，形成P型井或N型井于N型区域50N及P型区域50P的两者中。依据一些实施例，图3至图5绘示出先在P型区域50P中形成的N型井，以及后续在N型区域50N中形成的P型井。在其他实施例中，可以先在N型区域50N中形成P型井，后续在P型区域50P中形成N型井。如将在下文更详细地讨论，P型区域50P中的N型井将形成一个井区域，且在其上形成用于P型装置的通道层，并且N型区域50N中的P型井将形成一个井区域，且在其上形成用于N型装置的通道层。
首先请参照图3，可以形成第一掩膜150(也称为掩膜层150)于基底50之上。第一掩膜150是视需要而选用的掩膜，其可用于减少基底中或基底上的残留物，其中这些残留物是来自后续形成的光阻，例如，第二掩膜154及第三掩膜152(请参照以下图4及图5)的脱气(outgassing)及/或移除制程。在一些实施例中，第一掩膜150包括垫氧化物(pad oxide)层、垫氮化物(pad nitride)层、其他类似物或上述的组合。垫氧化物层可以是包含氧化硅及/或二氧化硅(SiO2)的薄膜，其可通过，例如，使用热氧化制程或沉积制程而形成，其中沉积制程包括，例如，化学气相沉积(chemical vapor deposition；CVD)、低压化学气相沉积(low pressure chemical vapor deposition；LPCVD)或等离子体辅助化学气相沉积(plasma enhanced chemical vapor deposition；PECVD)。然而，可以使用任何合适的方法而形成垫氧化物层。垫氮化物层可以由氮化硅(SiN)所形成，例如，使用化学气相沉积、低压化学气相沉积或等离子体辅助化学气相沉积。但是，可以使用任何合适的方法而形成垫氮化物层。在一些实施例中，例如，在低于约170℃的温度下进行后续离子布植(请参照以下图4及图5)的实施例中，可以省略第一掩膜150。
在图4中，利用N型杂质热布植200在P型区域50P中形成N型井604，如此可有利于减少基底缺陷。第二掩膜154(例如，光阻)形成于基底50之上并且被图案化，以暴露基底50的P型区域50P，或者，如果存在的话，暴露位于基底的P型区域50P之上的第一掩膜150。可以通过使用旋转涂布(spin-on)技术而形成第二掩膜154，并且可以使用可接受的光学微影(photolithography)技术而将第二掩膜154图案化。一旦第二掩膜154被图案化及显影，就可以在P型区域50P中进行N型杂质热布植200。第二掩膜154可以作为掩膜，以实质上防止N型杂质被布植到N型区域50N中。在其中存在第一掩膜150的一些实施例中，N型杂质热布植200驱动N型杂质穿过第一掩膜150进入基底50的P型区域50P中。N型杂质可以是磷、砷、锑或其他类似物。
N型杂质热布植200可以是合适的制程，例如，离子布植，并且可以以大约1.5×1014cm-2至大约3.0×1014cm-2的范围内的剂量或掺杂浓度而进行，如此可有利于通过减小井电阻及隔离漏电流，例如，从N+高掺杂源极/漏极区域到N型井604的漏电流(N+NW漏电流)，而实现后续形成的晶体管(例如，金属氧化物半导体场效晶体管)的大于约1.7V的触发电压。以小于约1.5×1014cm-2的剂量进行N型杂质热布植200可能是不利的，因为会造成较高的井电阻及N+NW漏电流，如此将导致小于约1.7V的触发电压。以大于约3.0×1014cm-2的剂量进行N型杂质热布植200可能是不利的，因为如此会产生很多的点缺陷，这些点缺陷会在后续的退火制程中形成广延缺陷(extended defect)。可以以大约5keV至大约150keV的范围内的能量进行离子布植，持续时间可以在大约2秒至大约10秒的范围内。在N型杂质热布植200期间的腔室压力可以在大约1×10-5torr至大约6×10-5torr的范围内。可以将N型掺质布植到N型井604中大约20nm至大约600nm的深度。在进行N型杂质热布植200之后，N型井604的N型掺质的体积浓度可以在大约1×1017原子/cm3至大约1×1019原子/cm3的范围内。
在大约150℃至大约500℃的温度范围内，例如，大约170℃至大约300℃，进行N型杂质热布植200，如此可有利于防止/减少点缺陷的形成，其中这些点缺陷是因为布植掺质的重型物种，例如，砷及磷，而在基底50内所产生的。举例而言，在约150℃至约500℃的范围内的温度下进行N型杂质热布植200可导致基底缺陷区域密度小于约5×107cm-2，例如，在约1×107cm-2至约5×107cm-2的范围内。如此可以减少在后续热处理期间的基底广延缺陷，因而提高装置性能。在小于约150℃的温度下以约1.5×1014cm-2至约3.0×1014cm-2的剂量布植掺质的重型物种，可能会在基底50(例如，硅基底)中引起间隙缺陷，并且可能会导致基底缺陷密度大于约5×107cm-2。如此可能会导致广延缺陷的形成，例如，在后续热处理制程期间的迭差及差排。这些广延缺陷可能会导致后续形成的外延通道区域(请参照以下图7)的迁移率下降。在大于约500℃的温度下进行N型杂质热布植200可能是不利的，因为如此可能会导致不匹配的掺质分布以较差的粒子性能。
举例而言，在一些实施例中，在约150℃下使用掺质的重型物种进行N型杂质热布植200，可以将所形成的基底缺陷的数量减少到比通过在室温下使用掺质的重型物种进行N型杂质布植所形成的基底缺陷的数量少约10倍，例如，基底缺陷区域的密度在约5×108cm-2至约1×1010cm-2的范围内。作为另一示范例，在约300℃下使用掺质的重型物种进行N型杂质热布植200可以将所形成的基底缺陷的数量减少到比通过在室温下使用掺质的重型物种进行N型杂质布植所形成的基底缺陷的数量少约12倍。
在一些实施例中，在约150℃至约170℃的温度范围内进行N型杂质热布植200。对于在约150℃至约170℃范围内的温度，可以省略如以上关于图3所描述的第一掩膜150的形成，这是因为较低的温度会导致来自光阻(例如，第二掩膜154)的脱气较少，以及来自第二掩膜154的移除所留下的残留物较少。如此可有利于有效地避免流量积分(flowintegration)的问题。在N型杂质热布植200是在大于约170℃的温度下进行的一些实施例中，为了减少基底50之中或基底50之上的残留物，第一掩膜150的形成可能是有需要的，其中残留物是来自光阻(例如，第二掩膜154)的脱气及/或移除制程。
在图5中，利用P型杂质布植300在N型区域50N中形成P型井602。第三掩膜152(例如，光阻)形成于基底50之上。将第三掩膜152图案化，以在基底的N型区域50N上方暴露基底50的N型区域50N或者，如果存在的话，暴露位于基底的N型区域50N之上的第一掩膜150。可以通过使用旋转涂布技术而形成第三掩膜152，并且可以使用可接受的光学微影技术而将第三掩膜152图案化。一旦第三掩膜152被图案化及显影，就可以在N型区域50N中进行P型杂质布植300，并且第三掩膜152可以作为掩膜，以实质上防止P型杂质被布植到P型区域50P中。在其中存在第一掩膜150的一些实施例中，P型杂质布植300驱动P型杂质穿过第一掩膜150进入基底50的N型区域50N中。P型杂质可以是硼、硼氟化物(例如，二氟化硼(BF2))、铟或其他类似物。
P型杂质布植300可以是合适的制程，例如，离子布植，并且可以以大约1.5×1014cm-2至大约3.0×1014cm-2的范围内的剂量或掺杂浓度而进行，如此可有利于通过减小井电阻及隔离漏电流，例如，从P+高掺杂源极/漏极区域到P型井602的漏电流(P+PW漏电流)，而实现后续形成的晶体管(例如，金属氧化物半导体场效晶体管)的大于约1.7V的触发电压。触发电压可以约略相等于晶体管的P-N接面(P-N junction)的崩溃电压(breakdownvoltage)。当两个双极接面晶体管(bipolar junction transistor；BJT，例如，金属氧化物半导体场效晶体管)并联时，连接到漏极端点VDD的直流电源大于触发电压可能会触发两个并联的双极接面晶体管的正回馈(positive feedback)，如此可能会导致漏电流耗尽。以小于约1.5×1014cm-2的剂量进行P型杂质布植300可能是不利的，因为会造成较高的井电阻及P+PW漏电流，如此将导致小于约1.7V的触发电压。以大于约3.0×1014cm-2的剂量进行P型杂质布植300可能是不利的，因为如此会产生很多的点缺陷，这些点缺陷会在后续的退火制程中形成广延缺陷。
P型杂质布植300可以是在大约5keV至大约60keV的范围内的离子布植能量下，在大约3秒至大约10秒的范围内并且在室温下进行的离子布植制程。在P型杂质布植300期间的腔室压力可以在大约1×10-5torr至大约6×10-5torr的范围内。可以将P型掺质布植到P型井602中大约20nm至大约600nm的深度。在一些实施例中，可以以例如约1016cm-3至约1019cm-3的范围内的浓度，将P型杂质布植到此区域中。在布植之后，例如，可以通过可接受的灰化(ashing)制程而移除第三掩膜152。
在一些实施例中，也可以使用与如以上关于图4所描述的N型杂质热布植200相似的方法，在大约150℃至大约500℃的范围内(例如，大约170℃至大约300℃)的温度下进行如以上关于图5所描述的P型杂质布植300而作为热布植。当所布植的P型杂质是例如二氟化硼(BF2)等相对较重的物种时，如此可有利于减少在形成P型井602期间基底缺陷的形成。
在图6中，例如，可以通过可接受的灰化制程而移除第三掩膜152。在其中存在第一掩膜150的实施例中，例如，可以通过可接受的蚀刻制程例如，干式蚀刻或湿式蚀刻，而移除第一掩膜150。在N型区域50N及P型区域50P的布植之后，可以进行退火，以修复布植损伤并且活化所布植的P型杂质及/或N型杂质。
在图7中，通过合适的制程，例如，外延成长，形成半导体层158于基底50之上。半导体层158可以被使用于在后续形成的鳍片52的顶部分中形成通道区域58(请参照下文，图8)。在各种实施例中，半导体层158可以由硅或由其他材料所形成，例如，硅锗(SixGe1-x，其中x可以在0-1的范围内)、碳化硅、纯的或实质上纯的锗、III-V族化合物半导体、II-VI族化合物半导体或其他类似物。举例而言，用于形成III-V化合物半导体的可用材料包括但不限于：砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化镓铟、砷化铝铟、锑化镓(galliumantimonide)、锑化铝(aluminum antimonide)、磷化铝、磷化镓及其他类似物。这些实施例的有利特征是后续形成的通道区域58可以由低能隙(low-bandgap)材料所形成，如此可以改善载子迁移率。此外，半导体层158的厚度仍可以相对较小，因而减小应力松弛(stress-relaxation)。在一些实施例中，在N型区域50N(例如，N型金属氧化物半导体区域)中外延成长与在P型区域50P(例如，P型金属氧化物半导体区域)中的材料不同的材料，如此可能是有优点的。举例而言，N型区域50N中的半导体层158的部分可以由与P型区域50P中的半导体层158的部分不同的材料所形成。
相似于如以上分别关于图4及图5所讨论的形成N型井604及P型井602的制程，可以使用掺质布植半导体层158，然后进行退火。在一些实施例中，半导体层158可以在成长期间被原位(in-situ)掺杂。半导体层158可以在P型区域50P中掺杂有N型杂质，并且在N型区域50N中掺杂有P型杂质。使用于半导体层158的N型杂质及/或P型杂质可以是上文所讨论的任何杂质。在P型区域50P中，半导体层158可以具有在约5×1016原子/cm3至大约1×1017原子/cm3的范围内的N型杂质浓度。在N型区域50N中，半导体层158可以具有在约5×1016原子/cm3至大约1×1017原子/cm3的范围内的P型杂质浓度。
在图8中，形成鳍片52于半导体层158及基底50中。鳍片52是半导体条带(semiconductor strip)，并且可以包括由半导体层158所形成的通道区域58。在一些实施例中，通道区域58具有在大约40nm至大约60nm的范围内的高度。在一些实施例中，可以通过蚀刻穿过半导体层158并进入基底50的沟槽，而在半导体层158及基底50中形成鳍片52。此蚀刻可以是任何可接受的蚀刻制程，例如，反应离子蚀刻(reactive ion etch；RIE)、中性粒子束蚀刻(neutral beam etch；NBE)、其他类似方法或上述的组合。此蚀刻可以是非等向性的。
可以通过任何合适的方法将鳍片图案化。举例而言，可以使用一个或多个光学微影制程将鳍片52图案化，包括双重图案化(double-patterning)制程或多重图案化(multi-patterning)制程。一般而言，双重图案化或多重图案化制程结合了光学微影制程及自对准制程(self-aligned process)，以创造具有较小节距的图案，举例而言，此图案所具有的节距比使用单一直接光学微影制程所能够得到的节距更小。举例而言，在一实施例中，形成牺牲层于基底之上并使用光学微影制程将其图案化。使用自对准制程形成间隔物于经过图案化的牺牲层旁。之后，移除牺牲层，并且可接着使用剩余的间隔物将鳍片图案化。在一些实施例中，掩膜(或其他膜层)可以保留在鳍片52上。
在将鳍片52及通道区域58图案化之后，通道区域58、P型井602及N型井604可以具有不同浓度的掺质。在由半导体层158所形成的通道区域58中，P型掺质(例如，磷)的掺质浓度与N型掺质(例如，硼)的掺质浓度可以在大约5×1016原子/cm3至大约1×1017原子/cm3的范围内。在P型井602中，P型掺质(例如，磷)的掺质浓度可以在约1018原子/cm3至大约1019原子/cm3的范围内。在N型井604中，N型掺质(例如，硼)的掺质浓度可以在大约1018原子/cm3至大约1019原子/cm3的范围内。
依据一些实施例，图9绘示出相对于鳍片52中的深度而绘制的掺质浓度。如图所示，在一些实施例中，掺质浓度可以具有P型杂质梯度跨越通道区域58与P型井602之间的边界及/或具有N型杂质梯度跨越通道区域58与N型井604之间的边界。举例而言，P型掺质浓度可以以大约每纳米8×1017原子/cm3至大约每纳米2×1018原子/cm3的范围内的速率改变而跨越通道区域58与P型井602之间的边界，且N型掺质浓度可以以大约每纳米2×1017原子/cm3至大约每纳米4×1017原子/cm3的范围内的速率改变而跨越通道区域58与N型井604之间的边界。
在图10中，绝缘材料54形成于基底50上并且位于相邻的鳍片52之间。绝缘材料54可以是氧化物(例如，氧化硅)、氮化物、其他类似物或上述的组合，并且可通过下列方法形成，包括高密度等离子体化学气相沉积(high density plasma chemical vapordeposition；HDP-CVD)、流动式化学气相沉积(flowable chemical vapor deposition；FCVD)(例如，在远距等离子体系统中进行的基于CVD的材料沉积，以及后固化(postcuring)而使其转化为另一种材料，例如，氧化物)、其他类似方法或上述的组合。可以使用通过任何可接受的方法所形成的其他绝缘材料。在所示的实施例中，绝缘材料54是通过流动式化学气相沉积制程所形成的氧化硅。当形成绝缘材料后，即可进行退火制程。在一实施例中，形成绝缘材料54，使得多余的绝缘材料54覆盖鳍片52。虽然绝缘材料54被绘示为单层，但是一些实施例可以使用多层结构。举例而言，在一些实施例中，可先沿着基底50及鳍片52的表面形成衬层(未绘示)。之后，可在衬层上形成填充材料，例如，如上文所讨论的材料。
在图11中，对绝缘材料54进行移除制程，以移除位于鳍片52上方的多余的绝缘材料54。在一些实施例中，可以使用平坦化制程，例如，化学机械研磨(chemical mechanicalpolish；CMP)、回蚀刻制程、上述的组合或其他类似方法。平坦化制程暴露出鳍片52，使得在平坦化制程完成之后，鳍片52的通道区域58的顶表面与绝缘材料54的顶表面是齐平的。在将掩膜保留于鳍片52上的实施例中，平坦化制程可以暴露出掩膜或是移除掩膜，使得在平坦化过程完成之后，掩膜的顶表面或鳍片52的顶表面分别与绝缘材料54的顶表面是齐平的。
在图12A及图12B中，将绝缘材料54凹陷化，以形成浅沟槽隔离(shallow trenchisolation；STI)区域56。将绝缘材料54凹陷化，使得位于N型区域50N及P型区域50P中的鳍片52的上部分从相邻的浅沟槽隔离区域56之间突出。此外，浅沟槽隔离区域56的顶表面可具有如图式所绘示的平坦表面、凸表面、凹表面(例如，碟形凹陷)或上述的组合。浅沟槽隔离区域56的顶表面可以通过适当的蚀刻而形成为平坦的、凸的及/或凹的。可以使用可接受的蚀刻制程将浅沟槽隔离区域56凹陷化，例如，对绝缘材料54的材料具有选择性的蚀刻制程(例如，以比鳍片52的材料更快的速率蚀刻绝缘材料54的材料)。举例而言，可以使用，例如，使用稀氢氟酸的氧化物移除(oxide removal)。依据一些实施例，图12A绘示出浅沟槽隔离区域56受到凹陷化，使得浅沟槽隔离区域56的顶表面与通道区域58的底表面齐平。依据其他实施例，图12B绘示出浅沟槽隔离区域56受到凹陷化，使得浅沟槽隔离区域56的顶表面高于通道区域58的底表面。后续的图式是接续图12B而绘示，但是所公开的实施例的范围也包括接续图12A而绘示的实施例，其中浅沟槽隔离区域56受到凹陷化，使得浅沟槽隔离区域56的顶表面与通道区域58的底表面齐平。在其他实施例(未绘示)中，浅沟槽隔离区域56可以受到凹陷化，使得浅沟槽隔离区域56的顶表面低于通道区域58的底表面。
在图13中，形成虚置介电层60于鳍片52上。虚置介电层60可以是，例如，氧化硅、氮化硅、上述的组合或其他类似物，并且可以通过可接受的技术沉积或热成长虚置介电层60。形成虚置栅极层62于虚置介电层60之上，并且形成掩膜层64于虚置栅极层62之上。可沉积虚置栅极层62于虚置介电层60之上，然后通过例如，化学机械研磨将其平坦化。可沉积掩膜层64于虚置栅极层62之上。虚置栅极层62可以是导电或非导电材料，并且可选自包括非晶硅、多晶硅(polycrystalline-silicon；polysilicon)、多晶硅-锗(poly-crystallinesilicon-germanium；poly-SiGe)、金属氮化物、金属硅化物、金属氧化物及金属所组成的群组。可以通过物理气相沉积(physical vapor deposition，PVD)、化学气相沉积、溅镀沉积(sputter deposition)或用于沉积所选材料的其他技术，而沉积虚置栅极层62。虚置栅极层62可以由其他材料所制成，这些材料对隔离区域(例如，浅沟槽隔离区域56及/或虚置介电层60)的蚀刻具有高蚀刻选择性。掩膜层64可以包括一层或多层的以下材料，例如，氮化硅、氮氧化硅或其他类似物。在本实施例中，形成单一个虚置栅极层62及单一个掩膜层64跨越N型区域50N及P型区域50P。应注意的是，虚置介电层60被绘示为仅覆盖鳍片52，这仅是基于说明的目的。在一些实施例中，可沉积虚置介电层60，使得虚置介电层60覆盖浅沟槽隔离区域56，其中虚置介电层60位于浅沟槽隔离区域之上并且在虚置栅极层62与浅沟槽隔离区域56之间延伸。
图14A至图22B绘示出实施例装置的制造中的各种其他步骤。图14A至图22B绘示出位于N型区域50N与P型区域50P其中之一的部件。举例而言，图14A至图22B所绘示的结构可以适用于N型区域50N与P型区域50P两者。在每个图式的说明中描述了N型区域50N与P型区域50P的结构上的差异(如果有的话)。
在图14A及图14B中，可以使用可接受的光学微影及蚀刻技术对掩膜层64(参照图13)进行图案化，以形成掩膜74。然后可以将掩膜74的图案转移至虚置栅极层62。在一些实施例(未绘示)中，掩膜74的图案也可以通过可接受的蚀刻技术而转移到虚置介电层60，以形成虚置栅极72。虚置栅极72覆盖鳍片52的相应的通道区域58。掩膜74的图案可以用于将每个虚置栅极72与相邻的虚置栅极物理性地分隔。虚置栅极72还可以具有实质上垂直于相应的外延鳍片52的长度方向的长度方向。
此外，在图14A及图14B中，可以在虚置栅极72、掩膜74及/或鳍片52的暴露表面上形成栅极密封间隔物(gate seal spacer)80。可以通过热氧化或沉积，然后进行非等向性蚀刻，而形成栅极密封间隔物80。栅极密封间隔物80可以由氧化硅、氮化硅、氮氧化硅或其他类似物而形成。
在形成栅极密封间隔物80之后，可以进行用于轻掺杂源极/漏极(lightly dopedsource/drain；LDD)区域(未明确绘示出)的布植。在具有不同装置类型的实施例中，相似于上文在图4及图5中所讨论的布植，可在N型区域50N上方形成掩膜，例如光阻，同时暴露P型区域50P，并且可将适当类型(例如，P型)的杂质布植到位于P型区域50P中的暴露的鳍片52中。然后可移除掩膜。随后，可在P型区域50P上方形成掩膜，例如光阻，同时暴露N型区域50N，并且可将适当类型(例如，N型)的杂质布植到位于N型区域50N中的暴露的鳍片52中。然后可移除掩膜。上述N型杂质可以是先前讨论的任何N型杂质，并且上述P型杂质可以是先前讨论的任何P型杂质。轻掺杂源极/漏极区域可具有在大约1015cm-3与大约1019cm-3之间的杂质浓度。可以进行退火，以修复布植损伤并且活化所布植的杂质。
在图15A及图15B中，沿着虚置栅极72的侧壁及掩膜74的侧壁而形成栅极间隔物86于栅极密封间隔物80上。可以通过顺应性地沉积绝缘材料并且随后非等向性地蚀刻此绝缘材料，以形成栅极间隔物86。栅极间隔物86的绝缘材料可以是氧化硅、氮化硅、氮氧化硅、氮碳化硅(silicon carbonitride)、上述的组合或其他类似物。
应注意的是，以上所公开的内容一般性地描述了形成间隔物及轻掺杂源极/漏极区域的制程。可以使用其他制程及顺序。举例而言，可以使用更少的间隔物或额外的间隔物，可以使用不同的步骤顺序(例如，可以在形成栅极间隔物86之前不蚀刻栅极密封间隔物80，而产生「L形」栅极密封间隔物；可以形成及/或移除间隔物；及/或其他类似的步骤顺序)。此外，可以使用不同的结构及步骤而形成N型装置及P型装置。举例而言，可以在形成栅极密封间隔物80之前形成用于N型装置的轻掺杂源极/漏极区域，而可以在形成栅极密封间隔物80之后形成用于P型装置的轻掺杂源极/漏极区域。
在图16A及图16B中，形成外延源极/漏极区域82于鳍片52中。形成外延源极/漏极区域82于鳍片52中，使得每一个虚置栅极72设置于各个相邻成对的外延源极/漏极区域82之间。一些实施例中，外延源极/漏极区域82可以延伸进入鳍片52中，并且也可以穿过鳍片52。在一些实施例中，栅极间隔物86用于将外延源极/漏极区域82从虚置栅极72分开适当的横向距离，以使外延源极/漏极区域82不会造成后续形成的鳍式场效晶体管的栅极短路。可以选择外延源极/漏极区域82的材料，以在相应的通道区域58中施加应力，而改善性能。
可以通过以下步骤而形成位于N型区域50N中的外延源极/漏极区域82，通过遮蔽P型区域50P并蚀刻位于N型区域50N中的鳍片52的源极/漏极区域，以形成凹口于鳍片52中。然后，在凹口中外延成长位于N型区域50N中的外延源极/漏极区域82。外延源极/漏极区域82可以包括任何可接受的材料，例如，可适用于N型鳍式场效晶体管。举例而言，若鳍片52是硅，则位于N型区域50N中的外延源极/漏极区域82可以包括在通道区域58中实现拉伸应变的材料，例如，硅、碳化硅、掺杂磷的碳化硅、磷化硅或其他类似物。位于N型区域50N中的外延源极/漏极区域82可具有从鳍片52的相应表面突起的表面并且可以具有刻面(facet)。
可以通过以下步骤而形成位于P型区域50P中的外延源极/漏极区域82，通过遮蔽N型区域50N并蚀刻位于P型区域50P中的鳍片52的源极/漏极区域，以形成凹口于鳍片52中。然后，在凹口中外延成长位于P型区域50P中的外延源极/漏极区域82。外延源极/漏极区域82可以包括任何可接受的材料，例如，可适用于P型鳍式场效晶体管。举例而言，若鳍片52是硅，则位于P型区域50P中的外延源极/漏极区域82可以包括在通道区域58中实现压缩应变的材料，例如，硅锗、掺杂硼的硅锗、锗、锗锡(germanium tin)或其他类似物。位于P型区域50P中的外延源极/漏极区域82可具有从鳍片52的相应表面突起的表面并且可以具有刻面。
可以使用掺质布植外延源极/漏极区域82及/或鳍片52，以形成源极/漏极区域，相似于上文所讨论的用于形成轻掺杂源极/漏极区域，然后进行退火的制程。源极/漏极区域的杂质浓度可以在大约1019cm-3与大约1021cm-3之间。用于源极/漏极区域的n型及/或p型杂质可以是上文所讨论的任何杂质。在一些实施例中，可在成长期间原位掺杂外延源极/漏极区域82。
作为用于在N型区域50N及P型区域50P中形成外延源极/漏极区域82的外延制程的结果，外延源极/漏极区域的上表面具有刻面，这些刻面横向地向外扩展超过鳍片52的侧壁。在一些实施例中，这些刻面导致同一个鳍式场效晶体管的相邻的源极/漏极区域82合并，如图16C所绘示。在其他实施例中，如图16D所绘示，在外延制程完成之后，相邻的源极/漏极区域82保持分离。在图16C及图16D所绘示的实施例中，栅极间隔物86形成为覆盖鳍片52的侧壁的一部分，其中此鳍片52的侧壁的此部分在浅沟槽隔离区域56上方延伸，而阻挡外延成长。在一些其他实施例中，可以调整用于形成栅极间隔物86的间隔物蚀刻，以移除间隔物材料，进而允许外延成长的区域延伸到浅沟槽隔离区域56的表面。
在图17A及图17B中，沉积第一层间介电层(ILD)88于图16A及图16B所绘示的结构之上。第一层间介电层88可以由介电材料所形成，并且可以通过任何合适的方法而沉积，例如，化学气相沉积、等离子体辅助化学气相沉积或流动式化学气相沉积。介电材料可包括磷硅酸盐玻璃(phospho-silicate glass；PSG)、硼硅酸盐玻璃(boro-silicate glass；BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phospho-silicate glass；BPSG)、未掺杂的硅酸盐玻璃(undoped silicate glass；USG)或其他类似物。可以使用通过任何可接受的方法所形成的其他绝缘材料。在一些实施例中，接触蚀刻停止层(contact etch stop layer；CESL)87设置在第一层间介电质88与外延源极/漏极区域82、掩膜74及栅极间隔物86之间。接触蚀刻停止层87可以包括介电材料，例如，氮化硅、氧化硅、氮氧化硅或其他类似物，其蚀刻速率不同于上述第一层间介电层88的材料的蚀刻速率。
在图18A及图18B中，可以进行平坦化制程(例如，化学机械研磨)，以使第一层间介电层88的顶表面与虚置栅极72的顶表面或掩膜74的顶表面齐平。平坦化制程可以也移除位于虚置栅极72上的掩膜74，以及沿着掩膜74的侧壁的栅极密封间隔物80的一部分及栅极间隔物86的一部分。在平坦化制程之后，虚置栅极72的顶表面、栅极密封间隔物80的顶表面、栅极间隔物86的顶表面与第一层间介电层88的顶表面是齐平的。因此，虚置栅极72的顶表面穿过第一层间介电层88而暴露。在一些实施例中，可以保留掩膜74，在这种情况下，平坦化制程使第一层间介电层88的顶表面与掩膜74的顶表面齐平。
在图19A及图19B中，在一个或多个蚀刻步骤中移除虚置栅极72及掩膜74(如果存在)，以形成凹口90。虚置介电层60位于凹口90中的部分也可以被移除。在一些实施例中，只有虚置栅极72被移除，而虚置介电层60被保留并且由凹口90暴露。在一些实施例中，虚置介电层60从位于晶粒的第一区域(例如，核心逻辑区域)的凹口90中被移除，并且保留在位于晶粒的第二区域(例如，输入/输出区域)的凹口90中。在一些实施例中，通过非等向性干式蚀刻制程移除虚置栅极72。举例而言，此蚀刻制程可包括使用反应气体的干式蚀刻制程，此反应气体选择性地蚀刻虚置栅极72而轻微地蚀刻或不蚀刻第一层间介电层88或栅极间隔物86。每一个凹口90暴露及/或覆盖各自的鳍片52的通道区域58。每一个通道区域58设置在相邻的一对外延源极/漏极区域82之间。在移除期间，当蚀刻虚置栅极72时，虚置介电层60可以被使用作为蚀刻停止层。在移除虚置栅极72之后，可以视需要而移除虚置介电层60。
在图20A及图20B中，形成栅极介电层92及栅极电极94作为替换栅极(replacementgate)。图20C绘示出图20B的区域89的详细剖面图。栅极介电层92包括沉积在凹口90中的一层或多层，例如，位于鳍片52的顶表面及侧壁上且位于栅极密封间隔物80栅极密封间隔物80/栅极间隔物86的侧壁上。栅极介电层92也可以形成在第一层间介电层88的顶表面上。在一些实施例中，栅极介电层92包括一个或多个介电层，例如，一层或多层的氧化硅、氮化硅、金属氧化物、金属硅酸盐或其他类似物。举例而言，在一些实施例中，栅极介电层92包括界面层以及位于界面层上方的高介电常数(high-k)介电材料，其中界面层包括通过热或化学氧化而形成的氧化硅，而高介电常数介电材料包括，例如，下列金属的金属氧化物或硅酸盐，这些金属包括：铪、铝、锆、镧、锰、钡、钛、铅及上述的组合。栅极介电层92可以包括高介电常数介电材料，其中此高介电常数介电材料具有大于约7.0的k值。栅极介电层92的形成方法可包括分子束沉积(molecular-beam deposition；MBD)、原子层沉积、等离子体辅助化学气相沉积及其他类似方法。在虚置介电层60的一部分保留在凹口90中的实施例中，栅极介电层92包括虚置介电层60的材料(例如，二氧化硅)。
栅极电极94分别沉积在栅极介电层92上，并填充凹口90的其余部分。栅极电极94可以包括含金属的材料，例如，氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、上述的组合或上述的多层结构。举例而言，虽然在图20B中绘示单层栅极电极94，但是栅极电极94可以包括任何数量的衬层94A、任何数量的功函数调整层94B以及填充材料94C，如图20C所绘示。在填充凹口90之后，可以进行平坦化制程，例如，化学机械研磨，以移除栅极介电层92的多余部分以及栅极电极94的材料，这些多余部分及材料是位于第一层间介电层88的顶表面上方。栅极电极94及栅极介电层92的材料的其余部分因此形成所得到的鳍式场效晶体管的替换栅极。栅极电极94与栅极介电层92可以合称为「栅极堆叠」。栅极与栅极堆叠可以沿着鳍片52的通道区域58的侧壁延伸。
位于N型区域50N与P型区域50P中的栅极介电层92的形成可以同时发生，使得位于每一个区域中的栅极介电层92由相同的材料所形成，并且栅极电极94的形成可以同时发生，使得位于每一个区域中的栅极电极94由相同的材料所形成。在一些实施例中，位于每一个区域中的栅极介电层92可以通过不同的制程而形成，使得栅极介电层92可以是不同的材料，及/或位于每一个区域中的栅极电极94可以通过不同的制程而形成，使得栅极电极94可以是不同的材料。当使用不同的制程时，可以使用各种遮蔽步骤以遮蔽并暴露适当的区域。
在图21A及图21B中，形成栅极掩膜96于栅极堆叠(包括栅极介电层92及相应的栅极电极94)之上，并且栅极掩膜可以设置在栅极间隔物86的相对两侧的部分之间。在一些实施例中，形成栅极掩膜96包括将栅极堆叠凹陷化，使得凹口形成于栅极堆叠正上方并且位于栅极间隔物86相对两侧的部分之间。将包括一层或多层介电材料(例如，氮化硅、氮氧化硅或其他类似物)的栅极掩膜96填充于此凹口中，然后进行平坦化制程，以移除在第一层间介电层88上方延伸的介电材料的多余部分。
同样如图21A及图21B所绘示，沉积第二层间介电层108于第一层间介电层88之上。在一些实施例中，第二层间介电层108是通过流动式化学气相沉积方法形成的可流动膜。在一些实施例中，第二层间介电层108由介电材料所形成，例如，磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、未掺杂的硅酸盐玻璃或其他类似物，并且可通过的任何合适的方法，例如，化学气相沉积及等离子体辅助化学气相沉积，而沉积第二层间介电层108。后续形成的栅极接触件110(图22A及图22B)穿过第二层间介电层108及栅极掩膜96而接触经过凹陷化的栅极电极94的顶表面。
依据一些实施例，在图22A及图22B中，形成栅极接触件110及源极/漏极接触件112穿过第二层间介电层108及第一层间介电层88。形成用于源极/漏极接触件112的开口穿过第一层间介电层88及第二层间介电层108，并且形成用于栅极接触件110的开口穿过第二层间介电层108及栅极掩膜96。可以使用可接受的光学微影及蚀刻技术而形成开口。形成衬层(未绘示，例如，扩散阻障层、粘着层或其他类似物)以及导电材料于上述开口中。衬层可包括钛、氮化钛、钽、氮化钽或其他类似物。导电材料可以是铜、铜合金、银、金、钨、钴、铝、镍或其他类似物。可以进行平坦化制程，例如，化学机械研磨，以从层间介电层108的表面移除多余的材料。剩余的衬层及导电材料在开口中形成源极/漏极接触件112及栅极接触件110。可以进行退火制程，以在外延源极/漏极区域82与源极/漏极接触件112之间的界面处形成硅化物。源极/漏极接触件112物理性且电性耦合到外延源极/漏极区域82，并且栅极接触件110物理性且电性耦合到栅极电极94。源极/漏极接触件112与栅极接触件110可以通过不同的制程而形成，或者可以通过相同的制程而形成。虽然绘示出形成为相同的剖面，但是应当理解，源极/漏极接触件112与栅极接触件110中的每一者可以形成为不同的剖面，如此可避免接触件的短路。
在此所公开的鳍式场效晶体管实施例也可以应用于纳米结构装置，例如，纳米结构(例如，纳米片、纳米线、全绕式栅极等)场效晶体管。在纳米结构场效晶体管实施例中，通过将通道层及牺牲层的交替层的堆叠图案化，以形成纳米结构而替换鳍片。通过与上述实施例类似的方式，而形成虚置栅极堆叠及外延源极/漏极区域。在移除虚置栅极堆叠之后，可在通道区域中部分移除或全部移除牺牲层。替换栅极结构通过与上述类似的方式而形成，并且替换栅极结构可以部分地围绕或完全地围绕位于纳米结构场效晶体管装置的通道区域中的通道层。可以通过与上述类似的方式而形成层间介电层以及接触件，其中上述接触件连接到栅极结构及源极/漏极。可以通过如美国专利申请公开2016/0365414中所公开的方法而形成纳米结构装置，其整体内容通过引用而并入本文。
本文所描述的实施例可实现许多优点。通过减小井电阻及隔离漏电流，例如，从高掺杂源极/漏极区域到井区域的漏电流，可以实现晶体管(例如，金属氧化物半导体场效晶体管)的大于约1.7V的触发电压。如此的隔离漏电流及井电阻的减小可以通过形成具有更高剂量的布植杂质的井区域而实现。在高温(例如，高于约150℃)下进行掺质的重型物种的布植，如此可有利于防止/减少点缺陷，如此可进一步在后续热处理期间防止/减少基底广延缺陷的形成，并且改善在后续形成的外延通道区域中的迁移率。在一些实施例中，在上述布植之前形成覆盖基底的掩膜层，例如，垫氧化物或垫氮化物，如此可有利于减少在布植期间所使用的光阻的脱气及残留。
依据一实施例，本发明实施例提供一种半导体装置的形成方法，其中上述半导体装置的形成方法包括：布植第一导电类型的多个掺质到半导体基底中，以形成第一井，其中上述半导体基底包括第一半导体材料，布植上述第一导电类型的上述掺质的步骤是在150℃至500℃的范围内的温度下进行；外延成长通道层于上述半导体基底上，其中上述通道层包括第二半导体材料，上述通道层受到上述第一导电类型的上述掺质所掺杂；从上述第二半导体材料形成鳍片；以及形成栅极结构于上述鳍片的通道区域之上，并且形成多个源极/漏极区域于上述该通道区域的相对两侧上的上述鳍片之上，其中上述源极/漏极区域受到第二导电类型的多个掺质所掺杂。在一实施例中，其中布植上述第一导电类型的上述掺质的步骤是在300℃至500℃的范围内的温度下进行。在一实施例中，其中上述第一导电类型的上述掺质是N型掺质。在一实施例中，其中上述第一导电类型的上述掺质包括砷或磷。在一实施例中，其中上述第二半导体材料不同于上述第一半导体材料。在一实施例中，其中在上述通道区域中的上述第一导电类型的上述掺质的浓度在5×1016原子/cm3至1017原子/cm3的范围内。在一实施例中，其中在上述第一井中的上述第一导电类型的上述掺质的浓度在1018原子/cm3和1019原子/cm3的范围内。在一实施例中，其中布植上述第一导电类型的上述掺质包括以在1.5×1014cm-2至3.0×1014cm-2的范围内的剂量进行布植。
依据另一实施例，本发明实施例提供一种半导体装置的形成方法，其中上述半导体装置的形成方法包括：形成第一掩膜于基底的第一区域及第二区域之上；形成第二掩膜于上述基底的上述第一区域中的上述第一掩膜之上；在上述第二区域中以1.5×1014cm-2至3.0×1014cm-2的剂量布植第一掺质，以形成第一井，上述布植是在170℃至500℃的范围内的温度下进行，其中上述布植是通过驱动上述第一掺质穿过上述第一掩膜而进行；移除上述第二掩膜；移除上述第一掩膜；以及形成第一鳍片于上述第一区域中，且形成第二鳍片于上述第二区域中。在一实施例中，其中上述第一掩膜包括氧化物或氮化物。在一实施例中，其中将上述第一掺质布植到上述第一井中至距离上述第一井的表面20nm至600nm范围内的深度。在一实施例中，其中上述第一掺质的浓度以每纳米8×1017原子/cm3至每纳米2×1018原子/cm3的范围内的速率改变而跨越上述第一井与上述第二鳍片之间的边界。在一实施例中，其中上述第一掺质是砷或磷。在一实施例中，其中上述第一井包括多个点缺陷，其中上述点缺陷具有面积密度小于5×107cm-2。在一实施例中，其中位于上述第一井中的上述第一掺质的浓度在1018原子/cm3与1019原子/cm3的范围内。
依据一实施例，本发明实施例提供一种半导体装置，其中上述半导体装置包括：半导体基底，上述半导体基底包括第一井，其中上述第一井包括第一掺质，其中上述第一掺质具有浓度在1017原子/cm3至1019原子/cm3范围内，上述第一井具有多个基底缺陷，其中上述基底缺陷具有面积密度在1.0×107cm-2至5.0×107cm-2的范围内；第一鳍片，从上述第一井延伸，其中上述第一掺质的上述浓度以每纳米8×1017原子/cm3至每纳米2×1018原子/cm3的范围内的速率改变而跨越上述第一井与上述第一鳍片之间的一边界；第一源极/漏极区及第二源极/漏极区，其中上述第一源极/漏极区及上述第二源极/漏极区从上述第一鳍片延伸；以及第一栅极电极，位于上述第一鳍片之上。在一实施例中，其中上述半导体基底更包括第二井，其中上述第二井具有第二掺质。在一实施例中，其中上述第一掺质是N型掺质，且上述第二掺质是P型掺质。在一实施例中，其中上述第一掺质是磷或砷。在一实施例中，其中上述第二掺质是二氟化硼。
前述内文概述了许多实施例的部件，使本技术领域中具有通常知识者可以从各个方面更佳地了解本发明实施例。本技术领域中具有通常知识者应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他制程及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中具有通常知识者也应了解这些相等的结构并未背离本发明实施例的发明精神与范围。在不背离本发明实施例的发明精神与范围的前提下，可对本发明实施例进行各种改变、置换或修改。

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1.一种半导体装置的形成方法，包括：
布植一第一导电类型的多个掺质到一半导体基底中，以形成一第一井，其中该半导体基底包括一第一半导体材料，布植该第一导电类型的所述掺质的步骤是在150℃至500℃的范围内的一温度下进行；
外延成长一通道层于该半导体基底上，其中该通道层包括一第二半导体材料，该通道层受到该第一导电类型的所述掺质所掺杂；
从该第二半导体材料形成一鳍片；以及
形成一栅极结构于该鳍片的一通道区域之上，并且形成多个源极/漏极区域于该通道区域的相对两侧上的该鳍片之上，其中所述源极/漏极区域受到一第二导电类型的多个掺质所掺杂。
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