CN101452903A - 用于无引脚封装的引脚架和其封装结构 - Google Patents
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- H01L24/93—Batch processes
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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Abstract
本发明揭示一种用于无引脚封装的引脚架，其包含多个封装区域、一绝缘层和一胶带。每一所述封装区域包含多个封装单元，且每一所述封装单元包含一芯片座和多个接脚。所述绝缘层填充于每一所述封装单元周围的间隙，且所述绝缘层的厚度小于所述接脚的厚度。所述胶带固定所述多个封装区域。
Description
技术领域
本发明涉及一种用于无引脚封装的引脚架，尤其涉及四方扁平无引脚封装(QuadFlat Non-leaded Package；QFN)所使用的引脚架。
背景技术
为适应消费性电子产品强调轻薄短小的趋势，QFN封装目前已经超越传统的引线封装，用来取代成本较高的晶片级芯片尺寸封装(wafer level CSP)，而芯片尺寸封装(CSP)虽将封装外形缩减成芯片大小，却须使用间距很近的锡球阵列作为元件接脚，使得产品制造难度提高。相对QFN封装不但体积小、成本低、生产产量高，还能为高速和电源管理电路提供更佳的共面性以及散热能力等优点，此外，QFN封装不必从两侧引出接脚，因此电气性能胜于引脚封装必须从侧面引出多只接脚的传统封装。举例来说，SO系列或QFP等引脚封装都必须从侧面引出多只接脚，这些接脚有时就像天线一样会给高频应用带来许多噪声。
图1是常规QFN封装的半成品10的上视图。引脚架12包含多个封装区域11，每一封装区域11中具有多个阵列状布置的封装单元112。切割道113、114位于封装单元112四周，可供切割刀经过而将各封装单元112分隔为独立的元件，所述切割刀同时会将封装体111和引脚架12的支撑条(supporting bar)(图未示)切开。
图2是常规QFN封装的单片化(singulation)步骤的示意图。切割刀80沿切割道113或114希望将相邻的封装单元112分开，切割刀80的刀刃需同时切割封装体111和引脚架12。一般封装体111是由环氧树脂、硅颗粒填充物和硬化剂等材料组成的混合物(compound)，而引脚架12由金属合金材料制成。切割刀80要将引脚架12切开时，对于刀刃会造成较大的磨损，即切割刀80的寿命会因切割金属材料而较短，从而更换新刀具的频率更快。如果牺牲切割速度以减缓切割刀80的磨损程度，那么势必造成单位小时产出(UPH)下降而无量产效益。显然常规QFN封装仍存在前述许多待解决的问题。
发明内容
本发明的目的是提供一种用于无引脚封装的引脚架，其中多个间隙设置于各封装单元的四周，可作为单片化步骤的切割道，因此能减少切割刀具的磨损和提升切割效率。
本发明的又一目的是提供一种整体刚性佳的无引脚封装引脚架，各封装单元周围的间隙用于填充绝缘材料，甚至芯片座和接脚周围的间隙也可填充绝缘材料，因此可以增加无引脚封装引脚架的整体刚性，以利于引脚架的取放。
为达到上述目的，本发明揭示一种用于无引脚封装的引脚架，其包含多个封装区域、一绝缘层和一胶带。每一所述封装区域包含多个封装单元，且每一所述封装单元包含一芯片座和多个接脚。所述绝缘层填充于每一所述封装单元周围的间隙，且所述绝缘层的厚度小于所述接脚的厚度。所述胶带固定所述多个封装区域。
本发明另揭示一种无引脚封装，其包含一芯片座、多个接脚、一绝缘层、至少一芯片和一封装体。所述多个接脚围绕所述芯片座。所述绝缘层填充于所述芯片座和所述多个接脚的周围，且所述绝缘层的厚度小于所述接脚的厚度。所述芯片配置于芯片座表面并电性连接到所述多个接脚。所述封装体覆盖所述芯片、芯片座和接脚。
通过上述设计，本发明设置多个间隙在各个封装单元的四周，且各封装单元周围的间隙用于填充绝缘材料，甚至芯片座和接脚周围的间隙也可填充绝缘材料，因此能减少切割刀具的磨损和提升切割效率，还可以增加无引脚封装引脚架的整体刚性，以利于引脚架的取放。
附图说明
图1是常规QFN封装的半成品的上视图；
图2是常规QFN封装的单片化步骤的示意图；
图3(a)是本发明用于无引脚封装的引脚架的上视图；
图3(b)是图3(a)中沿A—A剖面线的剖面示意图；
图4(a)是本发明另一实施例用于无引脚封装的引脚架的上视图；
图4(b)是图4(a)中沿B—B剖面线的剖面示意图；
图4(c)是本发明另一实施例引脚架的剖面示意图；
图4(d)是图4(a)中沿C—C剖面线的剖面示意图；
图4(e)是本发明另一实施例引脚架的剖面示意图；以及
图5是本发明无引脚封装的剖面示意图。
具体实施方式
图3(a)是本发明用于无引脚封装的引脚架的上视图。引脚架30包含多个封装区域31、多个间隙321和322、绝缘层35、多个连接部36和胶带34。各封装区域31包含多个呈阵列状布置的封装单元311，相邻两个封装区域31之间设置有一连接部36。各封装单元311包含一芯片座312和多个接脚313，芯片座312和周围的接脚313之间也有空隙存在。所述多个间隙321、322位于各封装单元311的四周，其中各间隙321沿引脚架30纵向(长边)延伸，并与边框331或连接部36相接；而且间隙322沿引脚架30横向(短边)延伸，并与边框332相接，且与一开槽333相连接或连通。绝缘层35填充于每一所述封装单元311周围的间隙321和322，且所述绝缘层35的厚度小于所述接脚313的厚度。胶带34用于固定所述多个封装区域31、所述多个连接部35、绝缘层35和边框331、332、芯片座312以及围绕所述芯片座312的多个接脚313。
图3(b)是图3(a)中沿A—A剖面线的剖面示意图。芯片座312和接脚313之间的间隙323与封装单元311周围的间隙321存在有填充绝缘层35，且绝缘层35的厚度小于所述接脚313的厚度。
如果上方第二边框332的上表面作为压模工艺中流道和进胶口的底部，那么开槽333′可设置于第二边框322的下表面，如图4(a)所示。图4(a)是本发明另一实施例用于无引脚封装的引脚架的上视图。相较于图3，本图引脚架40的开槽333′设置于第二边框322的下表面，可采用半蚀刻(half-etching)工艺形成，并和间隙322相连通。
图4(b)是图4(a)中沿B—B剖面线的剖面示意图。相较于图3(b)，图4(b)中开槽333′未贯穿第二边框332的上、下表面，但仍填充有绝缘层45。或者，第二边框332′可不设置开槽，那么绝缘层45′仅填充于封装单元311的范围内，如图4(c)所示。
图4(d)是图4(a)中沿C—C剖面线的剖面示意图。充满绝缘层45的开槽333′朝向胶带34，且被胶带34覆盖。图4(e)是对应于图4(c)中第二边框332′相同位置的另一剖面示意图，两图的剖面相互垂直。
图5是本发明无引脚封装的剖面示意图。无引脚封装50包含一芯片座312、多个接脚313、一绝缘层35、至少一芯片51和一封装体53。所述多个接脚313围绕芯片座313，但彼此相互分离。绝缘层35填充于芯片座312和多个接脚313的周围，且所述绝缘层35的厚度小于接脚313的厚度。芯片51配置于芯片座312表面，并通过金属引脚52电性连接到所述多个接脚313。封装体53覆盖芯片51、芯片座312、多个金属引脚52和接脚313。
本发明的技术内容和技术特点已揭示如上，然而所属领域的技术人员仍可能基于本发明的教示和揭示而作种种不背离本发明精神的替换和修饰。因此，本发明的保护范围应不限于实施例所揭示的保护范围，而应包括各种不背离本发明的替换和修饰，并为所附的权利要求书所涵盖。
Claims (11)
1.一种用于无引脚封装的引脚架，其特征在于包含：
多个封装区域，每一所述封装区域包含多个封装单元，每一所述封装单元包含：芯片座；以及
多个接脚，其围绕所述芯片座；
绝缘层，其填充于每一所述封装单元周围的间隙，其中所述绝缘层的厚度小于所述接脚的厚度；以及
胶带，其固定所述多个封装区域。
2.根据权利要求1所述的用于无引脚封装的引脚架，其特征在于所述绝缘层进一步填充于所述芯片座和所述多个接脚的周围。
3.根据权利要求1所述的用于无引脚封装的引脚架，其特征在于所述绝缘层延伸到每一所述封装区域的边界。
4.根据权利要求1所述的用于无引脚封装的引脚架，其特征在于另外包含多个环绕于所述多个封装区域外围的边框。
5.根据权利要求4所述的用于无引脚封装的引脚架，其特征在于所述绝缘层从每一所述封装单元之间延伸到边框。
6.根据权利要求5所述的用于无引脚封装的引脚架，其特征在于所述边框包含多个开槽，所述绝缘层填充于所述多个开槽内。
7.根据权利要求6所述的用于无引脚封装的引脚架，其特征在于所述开槽的深度占所述边框的部分厚度。
8.一种无引脚封装结构，其特征在于包含：
芯片座；
多个接脚，其围绕所述芯片座；
绝缘层，其填充于所述芯片座和所述多个接脚的周围，其中所述绝缘层的厚度小于所述接脚的厚度；
至少一芯片，所述芯片配置于所述芯片座表面并电性连接到所述多个接脚；以及封装体，其覆盖所述芯片、芯片座和接脚。
9.根据权利要求8所述的无引脚封装结构，其特征在于每一所述芯片座与多个接脚的至少一表面露出于所述封装体。
10.根据权利要求9所述的无引脚封装结构，其特征在于另外包含多个电性连接所述电路小片和所述多个接脚的金属引脚。
11.一种用于无引脚封装的引脚架，其特征在于包含：
多个封装区域，每一所述封装区域包含多个封装单元，每一所述封装单元包含：
芯片座；及
多个接脚，其围绕所述芯片座；以及
绝缘层，其填充于每一所述封装单元周围的间隙，其中所述绝缘层的厚度小于所述接脚的厚度。
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074535A (zh) * | 2009-11-19 | 2011-05-25 | 瑞鼎科技股份有限公司 | 在导电点间提供绝缘保护的电子芯片与基板 |
| CN103681585A (zh) * | 2013-12-31 | 2014-03-26 | 苏州日月新半导体有限公司 | 引线框架、qfn封装体、及形成qfn封装体的方法 |
-
2007
- 2007-12-05 CN CN 200710196595 patent/CN101452903A/zh active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074535A (zh) * | 2009-11-19 | 2011-05-25 | 瑞鼎科技股份有限公司 | 在导电点间提供绝缘保护的电子芯片与基板 |
| CN102074535B (zh) * | 2009-11-19 | 2013-08-21 | 瑞鼎科技股份有限公司 | 在导电点间提供绝缘保护的电子芯片与基板 |
| CN103681585A (zh) * | 2013-12-31 | 2014-03-26 | 苏州日月新半导体有限公司 | 引线框架、qfn封装体、及形成qfn封装体的方法 |
| US9972561B2 (en) | 2013-12-31 | 2018-05-15 | Suzhou Asen Semiconductors Co., Ltd. | QFN package with grooved leads |
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