CN101431075B - Semiconductor device and inverter circuit having the same - Google Patents
Semiconductor device and inverter circuit having the same Download PDFInfo
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- CN101431075B CN101431075B CN2008101748334A CN200810174833A CN101431075B CN 101431075 B CN101431075 B CN 101431075B CN 2008101748334 A CN2008101748334 A CN 2008101748334A CN 200810174833 A CN200810174833 A CN 200810174833A CN 101431075 B CN101431075 B CN 101431075B
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Abstract
A semiconductor device includes a semiconductor substrate (1), an insulated gate transistor (21) formed to the semiconductor substrate (1), a diode (22) formed to the semiconductor substrate (1), and a control transistor (ST1-ST3) formed to the semiconductor substrate (1). A first current terminal of the insulated gate transistor (21) is coupled to a cathode of the diode (22) at a high potential side. A second current terminal of the insulated gate transistor (21) is coupled to an anode (22a) of the diode (22) at a low potential side. The control transistor (ST1-ST3) is configured to turn off the insulated gate transistor (21) by reducing a potential of a gate terminal of the insulated gate transistor (21) when the diode (22) conducts an electric current.
Description
Technical field
The present invention relates to the semiconductor device that a kind of utilization is formed on insulated gate transistor and the antiparallel diode structure in the common semiconductor substrate.
Background technology
For example, at the US 2005/0258493 of the open No.2005-317751 corresponding to Japan Patent, disclosed in corresponding to the US 2007/0108468 of the open No.2007-134625 of Japan Patent and US 2007/0170549 and utilized the insulated gate transistor that is formed in the common semiconductor substrate and the semiconductor device of antiparallel diode structure corresponding to the open No.2007-214541 of Japan Patent.
Figure 19 shows disclosed semiconductor device 100 in US 2007/0170549.
In semiconductor device 100, in common semiconductor substrate 1, form insulated gate bipolar transistor (IGBT) unit 100i and diode 100d.
In the first groove T1, form first electrode layer of processing by polysilicon 8 through dielectric film 7.First electrode layer 8 is as the gate electrode of IGBT unit 100i.On first side of Semiconductor substrate 1, form the second electrode lay 10 made of aluminum.Utilize the second electrode lay 10 to fill the second groove T2.The second electrode lay 10 penetrates the first side N type district 3a and the first side p type island region 4a, thereby can make the first side N type district 3a and the first side p type island region 4a electric coupling.In addition, the second electrode lay 10 is electrically coupled to P type layer 2a.The second electrode lay 10 is as the emitter electrode of IGBT unit 100i and the anode electrode of diode 100d.The second side P+ type district 5 and the second side N+ type district 6 are formed on the surface portion of second side of Semiconductor substrate 1.Third electrode layer 11 is formed on second side of Semiconductor substrate 1 and it is electrically coupled on each in the second side P+ type district 5 and the second side N+ type district 6.Thus, make the second side P+ type district 5 and second side N+ type district's 6 electric coupling through third electrode layer 11.Third electrode layer 11 is as the collector electrode of IGBT unit 100i and the cathode electrode of diode 100d.
That is to say, in semiconductor device 100, insulated gate transistor and diode-coupled are in the same place with anti-parallel arrangement.Be coupled at the first terminal (for example collector electrode) and the negative electrode of diode of hot side, be coupled at second terminal (for example emitter) and the anode of diode of low potential side with insulated gate transistor with insulated gate transistor.Semiconductor device as semiconductor device 100 is integrated in the inverter circuit to control electric loading through pulse width modulation (PWM) technology usually.
Usually, when the semiconductor device that in inverter circuit, uses as semiconductor device 100, the gating signal gating signal with the IGBT that is applied to the inverter circuit Lower Half on phase place of IGBT that is applied to the inverter circuit first half is opposite.Therefore, even during the diode continuousing flow work of being coupled to IGBT with anti-parallel arrangement (freewheel operation), also can gating signal be applied to IGBT.That is, having a period of time IGBT and diode works simultaneously.As stated, in semiconductor device 100, the collector electrode of IGBT and the negative electrode of diode are coupled, and the anode of the emitter of IGBT and diode is coupled.Therefore, when the IGBT conducting, the negative electrode of diode attempts to be in identical current potential with anode.As a result, the forward bias of diode raises, so the forward loss of diode increases.In this way, in semiconductor device shown in Figure 19 100,, and may increase the forward loss of diode because IGBT and diode are interfering with each other.
The inventor after deliberation semiconductor device 90 shown in Figure 20 (Japanese patent application No.2007-229959).Semiconductor device 90 is configured to avoid the interference between IGBT and the diode, thereby can prevents the increase of diode forward loss.
Shown in figure 20, semiconductor device 90 comprises and circuit 50, the IGBT20 with diode-built-in, sense resistor 30 and feedback circuit 40.
With circuit 50 is a kind ofly only just to produce the gate that high level is exported when all be high level in all inputs.The PWM gating signal that will be used to drive IGBT20 is input to and circuit 50 from external circuit.In addition, the output with feedback circuit 40 is input to and circuit 50.
IGBT20 comprises IGBT part 21 and diode section 22.IGBT part 21 is formed in the common semiconductor substrate with diode section 22.IGBT part 21 comprises the main IGBT 21a that is coupled to electric loading and is used to detect the auxiliary IGBT 21b of electric current of main IGBT 21a of flowing through.Be applied to the voltage of the grid of IGBT 21a, 21b by PWM gating signal control with circuit 50 outputs.The emitter-coupled of auxiliary IGBT 21b is to first end of sense resistor 30, and the voltage drop Vs at sense resistor 30 two ends is fed back to feedback circuit 40.Diode section 22 is configured to the load current of transform stream through IGBT21a.Diode section 22 comprises the main diode 22a that is coupled to main IGBT 21a and is used to detect the booster diode 22b of electric current of main diode 22a of flowing through.The anode of booster diode 22b is coupled to first end of sense resistor 30.
Thus, in semiconductor device shown in Figure 20 90, main diode 22a can not disturb main IGBT 21a along the positive orientation guide electric current.Therefore, avoid the increase of the forward voltage of main diode 22a, therefore can prevent the increase of the forward loss of main diode 22a.
In addition, if the overcurrent main IGBT 21a that flows through is arranged, feedback circuit 40 to circuit 50 outputs forbid the PWM gating signal through with the signal of circuit 50.Thus, can protect IGBT 21a not receive the influence of overcurrent.
Summary of the invention
The purpose of this invention is to provide the semiconductor device that a kind of utilization is formed on insulated gate transistor and the antiparallel diode structure in the common semiconductor substrate.This semiconductor device has can be with the oxide-semiconductor control transistors of high speed operation, to guarantee the preventing increase of diode forward loss and to guarantee to protect insulated gate transistor not receive the influence of overcurrent.Another object of the present invention provides a kind of inverter circuit that utilizes this semiconductor device constructions.
According to an aspect of the present invention, semiconductor device comprise Semiconductor substrate, be formed into the insulated gate transistor of said Semiconductor substrate, the oxide-semiconductor control transistors that is formed into the diode of said Semiconductor substrate and is formed into said Semiconductor substrate.First current terminal of said insulated gate transistor is coupled to the negative electrode of said diode at hot side.Second current terminal of said insulated gate transistor is coupled to the anode of said diode at low potential side.The current potential that said oxide-semiconductor control transistors is configured to when the said diodes conduct electric current gate terminal through reducing insulated gate transistor ends said insulated gate transistor.
According to another aspect of the present invention; Inverter circuit comprises a plurality of semiconductor device, the oxide-semiconductor control transistors that each in the said semiconductor device comprises Semiconductor substrate, is formed into the insulated gate transistor of said Semiconductor substrate, is formed into the diode of said Semiconductor substrate and is formed into said Semiconductor substrate.First current terminal of said insulated gate transistor is coupled to the negative electrode of said diode at hot side.Second current terminal of said insulated gate transistor is coupled to the anode of said diode at low potential side.The current potential that said oxide-semiconductor control transistors is configured to when the said diodes conduct electric current gate terminal through reducing insulated gate transistor ends said insulated gate transistor.
Description of drawings
Through the following detailed description of doing with reference to accompanying drawing, above-mentioned and other purposes, feature and advantage of the present invention will become more obvious.In the accompanying drawings:
Fig. 1 is the diagrammatic sketch that illustrates according to the equivalent electric circuit of the semiconductor device of first embodiment of the invention;
Fig. 2 is the diagrammatic sketch that illustrates according to the equivalent electric circuit of the semiconductor device of second embodiment of the invention;
Fig. 3 is the diagrammatic sketch that illustrates according to the equivalent electric circuit of the semiconductor device of third embodiment of the invention;
Fig. 4 A is the bottom view that illustrates as the semiconductor device of first instance of the semiconductor device of Fig. 2, and Fig. 4 B is the diagrammatic sketch that illustrates along the sectional view of the line IVB-IVB intercepting of Fig. 4 A;
Fig. 5 is the diagrammatic sketch of top view that the semiconductor device of Fig. 4 A is shown;
Fig. 6 A is the diagrammatic sketch that illustrates as the bottom view of the semiconductor device of second instance of the semiconductor device of Fig. 2, and Fig. 6 B is the diagrammatic sketch that illustrates as the bottom view of the semiconductor device of the 3rd instance of the semiconductor device of Fig. 2;
Fig. 7 is the diagrammatic sketch that illustrates as the bottom view of the semiconductor device of the 4th instance of the semiconductor device of Fig. 2;
Fig. 8 A is the diagrammatic sketch that is illustrated in the bipolar transistor structure that uses in the semiconductor device of Fig. 2; Fig. 8 B is the diagrammatic sketch that is illustrated in another structure of the bipolar transistor that uses in the semiconductor device of Fig. 2, and Fig. 8 C is the diagrammatic sketch that is illustrated in another structure of the bipolar transistor that uses in the semiconductor device of Fig. 2;
Fig. 9 is the diagrammatic sketch that the partial enlarged drawing of Fig. 4 B is shown;
Figure 10 is the circuit diagram that the inverter circuit that is used to produce three-phase ac power is shown;
Figure 11 is the diagrammatic sketch of top view of the semiconductor chip of the inverter circuit that illustrates Figure 10 integrated;
Figure 12 is the diagrammatic sketch that illustrates along the sectional view of the line XII-XII intercepting of Figure 11;
Figure 13 A is the terminal layout that is integrated in the circuit diagram of the inverter circuit in the semiconductor chip of Figure 11 and the semiconductor chip of Figure 11 is shown; Figure 13 B be illustrate Figure 11 semiconductor chip bottom view and the diagrammatic sketch of terminal layout is shown, and Figure 13 C be illustrate Figure 11 semiconductor chip top view and the diagrammatic sketch of terminal layout is shown;
Figure 14 A is the terminal layout that is integrated in the circuit diagram of the inverter circuit in second half conductor chip and second half conductor chip is shown; Figure 14 B is the diagrammatic sketch that the bottom view of second half conductor chip is shown and the terminal layout is shown, and Figure 14 C is the diagrammatic sketch that the top view of second half conductor chip is shown and the terminal layout is shown;
The circuit diagram of the semiconductor chip of the inverter circuit first half of Figure 15 A is integrated Figure 10, and the circuit diagram of the semiconductor chip of the inverter circuit Lower Half of Figure 15 B Figure 10 that is integrated;
Figure 16 A is the diagrammatic sketch of top view that the semiconductor chip of Figure 15 A is shown, and Figure 16 B is the diagrammatic sketch of bottom view that the semiconductor chip of Figure 15 A is shown;
Figure 17 A is the diagrammatic sketch of top view that the semiconductor chip of Figure 15 B is shown, and Figure 17 B is the diagrammatic sketch of bottom view that the semiconductor chip of Figure 15 B is shown;
Figure 18 A illustrates the diagrammatic sketch that the semiconductor die package of Figure 15 A, 15B is arrived the top view of encapsulation together, and Figure 18 B is the diagrammatic sketch that the bottom view of this encapsulation is shown;
Figure 19 is the diagrammatic sketch that illustrates according to the semiconductor device of prior art; And
Figure 20 is the diagrammatic sketch that illustrates according to the semiconductor device of correlation technique.
Embodiment
(first embodiment)
Fig. 1 is the diagrammatic sketch that illustrates according to the equivalent electric circuit of the semiconductor device 60 of first embodiment of the invention.
For example, can semiconductor device 60 be integrated in the inverter circuit, this inverter circuit utilizes pulse width modulation (PWM) technology control electric loading.Semiconductor device 60 comprises insulated gate bipolar transistor (IGBT) 21 and diode 22.IGBT 21 is formed in the common semiconductor substrate and with anti-parallel arrangement with diode 22 and is coupled.Particularly, be coupled at the collector terminal (as first current terminal) and the cathode terminal of diode 22 of hot side IGBT 21.At low potential side the emitter terminal 21a (as second current terminal) of IGBT 21 and the anode terminal 22a of diode 22 are coupled.For example, the structure of IGBT 21 and diode 22 can be identical with structure shown in Figure 19.
As stated, bipolar transistor ST1 is arranged to adjacent to reduce length of arrangement wire with IGBT 21 or diode 22.In this method, reduced wiring inductance and electric capacity, make that bipolar transistor ST1 can be with high speed operation.In addition, can reduce the manufacturing cost of semiconductor device 60.For example, in the time of in the inverter circuit of the inductive load that semiconductor device 60 is integrated in control such as motor, semiconductor device 60 can be tackled the transient high-current such as surge current (inrush current) and flyback current as follows.
In semiconductor device 60, when diode 22 conduction forward currents, bipolar transistor ST1 has reduced the current potential of the gate terminal of IGBT 21, thereby can end IGBT 21.Particularly, when forward current is flowed through diode 22, with the proportional electric current of forward current flow through the sensing anode terminal 22b and first sense resistor 31.Then, between the base stage of bipolar transistor ST1 and emitter terminal, apply the voltage drop at first sense resistor, 31 two ends, thereby can make bipolar transistor ST1 conducting.Therefore, the current potential of the gate terminal of IGBT 21 is lowered near the current potential of emitter terminal 21a of IGBT 21.Thus, IGBT 21 is ended.
In a word, when forward current was flowed through diode 22, bipolar transistor ST1 ended IGBT 21.That is, the bipolar transistor ST1 of semiconductor device 60 can be to work with the feedback circuit 40 identical modes of the semiconductor device 90 of Figure 20, to prevent the interference between IGBT 21 and the diode 22.
As stated, according to first embodiment, semiconductor device 60 comprises can be as the bipolar transistor ST1 of feedback circuit 40 to prevent to disturb between IGBT 21 and the diode 22.Therefore, diode 22 can not disturb IGBT 21 along the forward conduction electric current, thereby can avoid the increase of the forward voltage of diode 22.Therefore, can prevent the increase of the forward loss of diode 22.
Compare with feedback circuit 40, bipolar transistor ST1 can have simple structure and small size.Therefore, can reduce the size of semiconductor device 60.In addition, because that bipolar transistor ST1 is arranged to is adjacent with IGBT 21 or diode 22 reducing length of arrangement wire, so bipolar transistor ST1 can be with high speed operation with the reply transient high-current.Therefore, can guarantee that bipolar transistor ST1 can prevent the increase of the forward loss of diode 22.
(second embodiment)
Fig. 2 position illustrates the diagrammatic sketch according to the equivalent electric circuit of the semiconductor device 61 of second embodiment of the invention.Difference between first and second embodiment is following.
In semiconductor device 61, IGBT 21 has extra sensing emitter terminal 21b, is used to export and the proportional electric current of electric current of the IGBT 21 that flows through.Second sense resistor 32 is coupling between the emitter terminal 21a and sensing emitter terminal 21b of IGBT21.The base terminal of bipolar transistor ST2 (as control terminal) is coupled to the sensing emitter terminal 21b of IGBT 21.The collector terminal of bipolar transistor ST2 (as first current terminal) is coupled to the gate terminal of IGBT 21.The emitter terminal of bipolar transistor ST2 (as second current terminal) is coupled to the emitter terminal 21a of IGBT 21.Second sense resistor 32 for example can be thin film resistor, diffused resistor etc.In common semiconductor substrate, form second sense resistor 32, in this substrate, be formed with IGBT 21 and diode 22.
In semiconductor device 61, when excessive electric current was flowed through IGBT 21, bipolar transistor ST2 had reduced the current potential of the gate terminal of IGBT 21, thereby IGBT 21 is ended.Particularly, when excessive electric current is flowed through IGBT 21, with the proportional electric current of overcurrent flow through the sensing emitter terminal 21b and second sense resistor 32.Then, between the base stage of bipolar transistor ST2 and emitter terminal, apply the voltage drop at second sense resistor, 32 two ends, thereby can make bipolar transistor ST2 conducting.Therefore, the current potential of the gate terminal of IGBT 21 is lowered near the current potential of emitter terminal 21a of IGBT 21.Thus, IGBT 21 is ended.
In a word, when excessive electric current was flowed through IGBT 21, bipolar transistor ST2 ended IGBT 21.That is, the bipolar transistor ST2 of semiconductor device 60 can not receive the influence of overcurrent to work with the feedback circuit 40 identical modes of the semiconductor device 90 of Figure 20 with protection IGBT 21.
As stated, according to second embodiment, semiconductor device 61 comprises can be as the bipolar transistor ST2 of feedback circuit 40 to protect IGBT 21 not influenced by overcurrent.Compare with feedback circuit 40, bipolar transistor ST2 can have simple structure and small size.Therefore, can reduce the size of semiconductor device 61.In addition, because that bipolar transistor ST2 is arranged to is adjacent with IGBT 21 or diode 22 reducing length of arrangement wire, so bipolar transistor ST2 can be with high speed operation with the reply overcurrent.Therefore, can guarantee that bipolar transistor ST2 can protect IGBT 21 not receive the influence of overcurrent.
(the 3rd embodiment)
Fig. 3 is the diagrammatic sketch that illustrates according to the equivalent electric circuit of the semiconductor device 70 of third embodiment of the invention.Difference between previous embodiment and the 3rd embodiment is following.
The base terminal of bipolar transistor ST3 (as control terminal) is coupled to the sensing emitter terminal 21b of IGBT 21.The collector terminal of bipolar transistor ST3 (as first current terminal) is coupled to the gate terminal of IGBT 21.The emitter terminal of bipolar transistor ST3 (as second current terminal) is coupled to the anode terminal 22a of diode 22.
In semiconductor device 70, when diode 22 conduction forward currents, with the proportional electric current of forward current flow through the sensing anode terminal 22b and first and second sense resistor 33,34.Because the resistance R 1 of first resistor 33 is greater than the resistance R 2 of second resistor 34, so bipolar transistor ST3 works as counter-rotating transistor (reverse transistor) and is switched on.Therefore, the current potential of the gate terminal of IGBT 21 is lowered near the current potential of emitter terminal 21a of IGBT 21.Thus, IGBT 21 is ended, thereby can prevent the increase of the forward loss of diode 22.
In addition, in semiconductor device 70, when excessive electric current is flowed through IGBT 21, with the proportional electric current of overcurrent flow through the sensing emitter terminal 21b and second sense resistor 34.Then, between the base stage of bipolar transistor ST3 and emitter terminal, apply the voltage drop at second sense resistor, 34 two ends, thereby can make bipolar transistor ST3 conducting.Therefore, the current potential of the gate terminal of IGBT 21 is lowered near the current potential of emitter terminal 21a of IGBT 21.Thus, make IGBT 21 by and protect it not receive the influence of overcurrent.
(modification)
Can use multiple mode to revise the foregoing description.Although in semiconductor device 60,61,70, IGBT 21 is used as insulated gate transistor, insulated gate transistor can be the transistor except that IGBT.For example, can be with vertical MOSFET as insulated gate transistor.In this case, the drain terminal of vertical MOSFET is corresponding to the collector terminal of IGBT 21, and the source terminal of vertical MOSFET is corresponding to the emitter terminal 21a of IGBT 21.
Although in semiconductor device 60,61,70, bipolar transistor ST1-ST3 is used as oxide-semiconductor control transistors, oxide-semiconductor control transistors also can be the transistor except that bipolar transistor.For example, can be with MOSFET as oxide-semiconductor control transistors.In this case; The gate terminal of MOSFET is corresponding to each the base terminal among the bipolar transistor ST1-ST3; The drain terminal of MOSFET is corresponding to each the collector terminal among the bipolar transistor ST1-ST3, and the source terminal of MOSFET is corresponding to each the emitter terminal among the bipolar transistor ST1-ST3.
Hereinafter with reference Fig. 4 A-7 describes the instance of the structure of semiconductor device shown in Figure 2 61.Although not shown in the drawings, Fig. 1, the semiconductor device shown in 3 60,70 can have and semiconductor device 61 similar structures.
Fig. 4 A-5 illustrates the schematic structure as the semiconductor device 61a of first instance of semiconductor device 61.Fig. 4 A is the diagrammatic sketch that the bottom view of semiconductor device 61a is shown.Fig. 4 B is the diagrammatic sketch that illustrates along the sectional view of the line IV-IV intercepting of Fig. 4 A.Fig. 5 is the diagrammatic sketch that the top view of semiconductor device 61a is shown.
Fig. 6 A illustrates the schematic structure as the semiconductor device 61b of second instance of semiconductor device 61.In semiconductor device 61b; With the first's separated into two parts that forms IGBT zone and diode area; Be separated from each other by second portion these two parts, in said second portion, form IGBT sensing region, diode sensing region, oxide-semiconductor control transistors ST1 zone and oxide-semiconductor control transistors ST2 zone first.
Fig. 6 B illustrates the schematic structure as the semiconductor device 61c of the 3rd instance of semiconductor device 61.In semiconductor device 61c, first is arranged to have the C shape of inner space, second portion is arranged in the inner space of the first of C shape.
Fig. 7 illustrates the schematic structure as the semiconductor device 61d of the 4th instance of semiconductor device 61.In semiconductor device 61d, first is arranged to have the rectangular ring in closed interior space, second portion is arranged in the closed interior space of the first of ring-type.
In in semiconductor device 61b-61d each, it is adjacent to improve sensitivity through reducing length of arrangement wire with the IGBT zone that second portion is arranged to.
The instance of structure of the bipolar transistor ST1 of semiconductor device shown in Figure 2 61 below will be described with reference to figure 8A-8C.Although not shown in the drawings, bipolar transistor ST2, ST3 can have the similar structure with bipolar transistor ST1.
Fig. 8 A illustrates the schematic structure as the bipolar transistor ST1a of first instance of bipolar transistor ST1.Bipolar transistor ST1a is centered on by the insulated trench ZT that is formed in the Semiconductor substrate 1.In this method,, can prevent that also parasitic thyratron from moving (thyristor action) even be arranged to IGBT zone when adjacent with diode area at bipolar transistor ST1a.
Fig. 8 B illustrates the schematic structure as the bipolar transistor ST1b of second instance of bipolar transistor ST1.Isolate bipolar transistor ST1b by insulated trench ZT and buried insulator layer ZU.In this method, even be arranged to IGBT zone can prevent that also parasitic thyratron from moving when adjacent with diode area at bipolar transistor ST1b.
Fig. 8 C illustrates the schematic structure as the bipolar transistor ST1c of the 3rd instance of bipolar transistor ST1.Bipolar transistor ST1c is centered on by insulated trench ZT.In addition, heavily doped layer N1, N2 be positioned at bipolar transistor ST1c under.Among heavily doped layer N1, the N2 each has the conduction type identical with Semiconductor substrate 1.But each among heavily doped layer N1, the N2 has the impurity concentration higher than Semiconductor substrate 1.In this method, even be arranged to IGBT zone can prevent that also parasitic thyratron from moving when adjacent with diode area at bipolar transistor ST1c.
Fig. 9 is the diagrammatic sketch that the partial enlarged drawing of Fig. 4 B is shown.Comparison diagram 9 can find out that with Figure 19 semiconductor device 61a, the difference between 100 are that semiconductor device 61a has the heavily doped layer 1a between the drift layer of channel layer 2a and IGBT.Heavily doped layer 1a has the conduction type identical with Semiconductor substrate 1.But heavily doped layer 1a has the impurity concentration higher than Semiconductor substrate 1.In this method,, also can prevent parasitic thyratron action even be arranged to the IGBT zone when adjacent with diode area at bipolar transistor ST1, ST2.
As stated, comprise according to the semiconductor device of said embodiment and being formed in the common semiconductor substrate and with the insulated gate transistor and the diode of anti-parallel arrangement coupling.Said semiconductor device also comprises oxide-semiconductor control transistors, and this oxide-semiconductor control transistors not only can be used to prevent the interference between insulated gate transistor and the diode, but also can be used to protect insulated gate transistor not receive the influence of overcurrent.Because it is adjacent with insulated gate transistor or diode that oxide-semiconductor control transistors is arranged to, so oxide-semiconductor control transistors can be with high speed operation, thus reply transient high-current (overcurrent).In addition, because oxide-semiconductor control transistors has simple structure and small size, therefore can reduce size of semiconductor device.
In view of foregoing, can suitably be applied to inverter circuit according to the semiconductor device of said embodiment.
For example, the semiconductor device shown in Fig. 1-3 60,61,70 can be applied to inverter circuit through following mode.
Figure 10 illustrates the inverter circuit K1 that is used to produce three-phase alternating current (AC) power.Inverter circuit K1 comprises six semiconductor device 80a-80f, and wherein each is corresponding in semiconductor device 60,61 and 70 any one.Although Figure 10 only illustrates IGBT and diode, each among the semiconductor device 80a-80f have with semiconductor device 60,61 and 70 in any one identical structure.That is, each among the semiconductor device 80a-80f has the oxide-semiconductor control transistors corresponding to oxide-semiconductor control transistors ST1-ST3.
Can inverter circuit K1 be integrated among the single semiconductor chip IC1 shown in Figure 11.Semiconductor chip IC1 comprises power supply area PKa-PKf, makes them electrically isolated from one through the insulated trench ZK that penetrates Semiconductor substrate.IGBT and the diode of semiconductor device 80a are formed into power supply area PKa.IGBT and the diode of semiconductor device 80b are formed into power supply area PKb.IGBT and the diode of semiconductor device 80c are formed into power supply area PKc.IGBT and the diode of semiconductor device 80d are formed into power supply area PKd.IGBT and the diode of semiconductor device 80e are formed into power supply area PKe.IGBT and the diode of semiconductor device 80f are formed into power supply area PKf.To be formed on jointly among the SK of controlled area except that the IGBT of semiconductor device 80a-80f and the element the diode.Shown in figure 11, controlled area SK is positioned at the central authorities of semiconductor chip IC1 and is centered on by power supply area PKa-PKf.For example, will be formed on jointly among the SK of controlled area corresponding to the oxide-semiconductor control transistors of the semiconductor device 80a-80f of bipolar transistor ST1-ST3.Owing to through insulated trench ZK semiconductor device 80a-80f is isolated from each other, so inverter circuit K1 can tackle big electric current.In addition, because inverter circuit K1 is integrated among the single semiconductor chip IC1, therefore can reduce the size of inverter circuit K1.
Particularly, shown in figure 12, in power supply area, be formed integrally as vertical IGBT and diode.IGBT has emitter and gate terminal in the top side of semiconductor chip IC1, has collector terminal at the dorsal part of semiconductor chip IC1.The emitter of IGBT and gate terminal are electrically coupled to the outside through the conducting film 10 such as the aluminium film.The collector terminal of IGBT is electrically coupled to the outside through the conducting film 11 such as the aluminium film.
In addition, shown in figure 12, in the SK of controlled area, form as MOS transistor ST1d (being lateral transistor) as oxide-semiconductor control transistors.Form MOS transistor ST1d in the soi layer on buried insulator layer ZU.The dorsal part of controlled area SK is protected by dielectric film ZR.
For example, can shown in the thick line among Figure 12, oxide-semiconductor control transistors, IGBT and diode be electrically coupled to one another.The resistance of resistor 31 can be in tens ohm to several kilohms scope.Resistor 31 is corresponding to first sense resistor 31 among Fig. 1.Resistor 31 can be thin film resistor, diffused resistor, polyresistor etc.Can resistor 31 be formed into controlled area SK or power supply area PKa-PKf.MOS transistor ST1d has drain terminal D (n+), gate terminal G and source terminal S (n+).
When using NPN transistor to replace MOS transistor ST1d, the collector electrode of NPN transistor, base stage and emitter terminal correspond respectively to drain electrode, grid and source terminal D, G, S.In this case; As shown in Figure 1; The collector terminal of NPN transistor is coupled to the gate terminal of IGBT21; The base terminal of NPN transistor is coupled to the emitter terminal of IGBT21, and the emitter terminal of NPN transistor is coupled to each among the sensing anode terminal 22b of resistor 31 and diode 22.
Shown in figure 12, make power supply area PKa-PKf electrically isolated from one through insulated trench ZK.In addition, through insulated trench ZK each and controlled area SK among the power supply area PKa-PKf are kept apart.When being used in semiconductor chip IC1 in the hybrid electric vehicle, can between the IGBT in adjacent power supply area PKa-PKf, apply about 1200 volts voltage.Quantity and thickness through increasing insulated trench ZK can improve applying the resistance of voltage.For example, insulated trench ZK can be multilayer to improve the resistance that voltage is applied.
Figure 13 A-13C illustrates the terminal layout of semiconducter IC shown in Figure 11 1.Figure 13 A is the circuit diagram that is integrated in the inverter circuit K1 among the semiconductor chip IC1.Figure 13 B is the diagrammatic sketch that the bottom view of semiconductor chip IC1 is shown.Figure 13 C is the diagrammatic sketch that the top view of semiconductor chip IC1 is shown.
Shown in Figure 13 A, each IGBT that in semiconductor chip IC1, uses is N raceway groove IGBT.Therefore, shown in Figure 13 B, be formed among the power supply area PKa-PKc, have common collector terminal C corresponding to the IGBT of the inverter circuit K1 first half.Shown in Figure 13 C, be formed among the power supply area PKd-PKf, have common issue gate terminal E corresponding to the IGBT of inverter circuit K1 Lower Half.Common collector terminal C is coupled to power supply potential Vcc, and common issue gate terminal E is coupled to ground potential GND.The emitter terminal that is formed on the IGBT among the power supply area PKa-PKc is coupled to the collector terminal that is formed on the IGBT among the power supply area PKd-PKf, so that the sub-U of three-phase output end, V, W to be provided respectively.
Figure 14 A-14C illustrates the terminal layout of semiconductor chip IC2.Figure 14 A illustrates the circuit diagram that is integrated in the inverter circuit among the semiconductor chip IC2.Figure 14 B illustrates the diagrammatic sketch of the bottom view of semiconductor chip IC2.Figure 14 C illustrates the diagrammatic sketch of the top view of semiconductor chip IC2.
Shown in Figure 14 A, in semiconductor chip IC2, utilize the first half of N raceway groove IGBT structure inverter circuit, utilize the Lower Half of P raceway groove IGBT structure inverter circuit.
In N raceway groove IGBT, through ion implantation technique P type tagma and N type emitter region are formed into the top side of n type semiconductor layer, P type collector area is formed into the dorsal part of n type semiconductor layer.In addition, the N type cathodic region of diode is formed into the dorsal part of n type semiconductor layer.
In P raceway groove IGBT, through ion implantation technique N type tagma and P type emitter region are formed into the top side of p type semiconductor layer, N type collector area is formed into the dorsal part of p type semiconductor layer.In addition, the p type anode district of diode is formed into the dorsal part of p type semiconductor layer.
Therefore, shown in Figure 14 B, be formed among the power supply area PKa-PKc, have common collector terminal C1 corresponding to the IGBT of the inverter circuit first half.Shown in Figure 14 C, be formed among the power supply area PKd-PKf, have common collector terminal C2 corresponding to the IGBT of inverter circuit Lower Half.Common collector terminal C1 is coupled to power supply potential Vcc, and common collector terminal C2 is coupled to ground potential GND.The emitter terminal that is formed on the IGBT among the element region PKa-PKc is coupled to the emitter terminal that is formed on the IGBT among the element region PKd-PKf, so that the sub-U of three-phase output end, V, W to be provided respectively.
In semiconductor chip IC1, six semiconductor device are integrated in the single semiconductor chip to construct inverter circuit K1 shown in Figure 10.
Perhaps, can utilize two semiconductor chip IC3u shown in Figure 15 A, the 15B, IC3d structure inverter circuit K1.Three semiconductor device are integrated in each among semiconductor chip IC3u, the IC3d.Semiconductor chip IC3u constitutes the first half of inverter circuit K1, and semiconductor chip IC3d constitutes the Lower Half of inverter circuit K1.
Figure 15 A illustrates the circuit diagram of the first half of the inverter circuit K1 that is integrated among the semiconductor chip IC3u.Figure 15 B illustrates the circuit diagram of the Lower Half of the inverter circuit K1 that is integrated among the semiconductor chip IC3d.Figure 16 A is the diagrammatic sketch that the top view of semiconductor chip IC3u is shown.Figure 16 B is the diagrammatic sketch that the bottom view of semiconductor chip IC3u is shown.Figure 17 A is the diagrammatic sketch that the top view of semiconductor chip IC3d is shown.Figure 17 B is the diagrammatic sketch that the bottom view of semiconductor chip IC3d is shown.Figure 18 A is the diagrammatic sketch that the top view of the encapsulation that semiconductor chip IC3u, IC3d are packaged together is shown.Figure 18 B is the diagrammatic sketch that the bottom view of this encapsulation is shown.
In this way, can utilize two semiconductor chip IC3u, the IC3d structure inverter circuit K1 that shown in Figure 18 A, 18B, is packaged together.Thus, can reduce the size of inverter circuit K1 and with the low cost manufacturing.
As stated, can work reliably according to the semiconductor device of said embodiment and have little size.Therefore, for example can semiconductor device suitably be applied to be installed in the device on the vehicle.
This change and modification be interpreted as to be in like enclosed in the scope of the present invention that claim limits.
Claims (18)
1. semiconductor device comprises:
Semiconductor substrate (1);
Be formed into the insulated gate transistor (21) of said Semiconductor substrate (1);
Be formed into the diode (22) of said Semiconductor substrate (1); And
Be formed into said Semiconductor substrate (1) first oxide-semiconductor control transistors (ST1, ST3),
First current terminal of wherein said insulated gate transistor (21) is coupled to the negative electrode of said diode (22) at hot side,
Second current terminal of wherein said insulated gate transistor (21) is coupled to the anode of said diode (22) at low potential side, and
Wherein (ST1 ST3) is configured to, and when said diode (22) conduction first electric current, the current potential of the gate terminal through reducing said insulated gate transistor (21) ends said insulated gate transistor (21) with said first oxide-semiconductor control transistors.
2. semiconductor device according to claim 1 also comprises:
Be formed into first sense resistor (31) of said Semiconductor substrate (1),
Wherein said diode (22) has the sensing anode terminal (22b) that is used to export with proportional second electric current of said first electric current,
Wherein said first sense resistor (31) is coupling between the said anode and said sensing anode terminal (22b) of said diode (22),
The control terminal of wherein said first oxide-semiconductor control transistors (ST1) is coupled to the said anode of said diode (22),
First current terminal of wherein said first oxide-semiconductor control transistors (ST1) is coupled to the said gate terminal of said insulated gate transistor (21),
Second current terminal of wherein said first oxide-semiconductor control transistors (ST1) is coupled to the said sensing anode terminal (22b) of said diode (22).
3. semiconductor device according to claim 2 also comprises:
Be formed into second oxide-semiconductor control transistors (ST2) of said Semiconductor substrate (1); And
Be formed into second sense resistor (32) of said Semiconductor substrate (1),
Wherein said second oxide-semiconductor control transistors (ST2) is configured to; When the 3rd electric current of the said insulated gate transistor (21) of flowing through surpasses admissible current value; The current potential of the said gate terminal through reducing said insulated gate transistor (21) ends said insulated gate transistor (21)
Wherein said insulated gate transistor (21) has the current sensor terminal (21b) that is used to export with proportional the 4th electric current of said the 3rd electric current; Wherein said second sense resistor (32) is coupling between said second current terminal of said current sensor terminal (21b) and said insulated gate transistor (21) of said insulated gate transistor (21)
The control terminal of wherein said second oxide-semiconductor control transistors (ST2) is coupled to the said current sensor terminal (21b) of said insulated gate transistor (21),
First current terminal of wherein said second oxide-semiconductor control transistors (ST2) is coupled to the said gate terminal of said insulated gate transistor (21), and
Second current terminal of wherein said second oxide-semiconductor control transistors (ST2) is coupled to said second current terminal of said insulated gate transistor (21).
4. semiconductor device according to claim 1 also comprises:
Be formed into first sense resistor (33) of said Semiconductor substrate (1); And
Be formed into second sense resistor (34) of said Semiconductor substrate (1),
Wherein said diode (22) has the sensing anode terminal (22b) that is used to export with proportional second electric current of said first electric current, the 3rd electric current said insulated gate transistor (21) of flowing through wherein,
Wherein said insulated gate transistor (21) has the current sensor terminal (21b) that is used to export with proportional the 4th electric current of said the 3rd electric current; Wherein said first sense resistor (33) is coupling between the said current sensor terminal (21b) of said sensing anode terminal (22b) and said insulated gate transistor (21) of said diode (22)
Wherein said second sense resistor (34) is coupling between the said current sensor terminal (21b) and said second current terminal of said insulated gate transistor (21), and
The resistance of wherein said first sense resistor (33) is greater than the resistance of said second sense resistor (34),
The control terminal of wherein said first oxide-semiconductor control transistors (ST3) is coupled to the said current sensor terminal (21b) of said insulated gate transistor (21),
First current terminal of wherein said first oxide-semiconductor control transistors (ST3) is coupled to the said gate terminal of said insulated gate transistor (21), and
Second current terminal of wherein said first oxide-semiconductor control transistors (ST3) is coupled to the said anode (22a) of said diode (22).
5. semiconductor device according to claim 1,
Wherein said insulated gate transistor (21) is insulated gate bipolar transistor or VMOS Vertical Metal Oxide Semiconductor transistor,
Collector terminal that said first current terminal of wherein said insulated gate transistor (21) is said insulated gate bipolar transistor or said VMOS Vertical Metal Oxide Semiconductor transistor drain terminal, and
Emitter terminal that said second current terminal of wherein said insulated gate transistor (21) is said insulated gate bipolar transistor or the transistorized source terminal of said VMOS Vertical Metal Oxide Semiconductor.
6. semiconductor device according to claim 2,
Wherein said first oxide-semiconductor control transistors (ST1 ST3) is bipolar transistor or metal oxide semiconductor transistor,
Wherein said first oxide-semiconductor control transistors (ST1, said control terminal ST3) are the base terminal of said bipolar transistor or the gate terminal of said metal oxide semiconductor transistor,
Wherein said first oxide-semiconductor control transistors (ST1, said first current terminal ST3) is the collector terminal of said bipolar transistor or the drain terminal of said metal oxide semiconductor transistor, and
(ST1, said second current terminal ST3) is the emitter terminal of said bipolar transistor or the source terminal of said metal oxide semiconductor transistor to wherein said first oxide-semiconductor control transistors.
7. semiconductor device according to claim 3,
Wherein said second oxide-semiconductor control transistors (ST2) is bipolar transistor or metal oxide semiconductor transistor,
The said control terminal of wherein said second oxide-semiconductor control transistors (ST2) is the base terminal of said bipolar transistor or the gate terminal of said metal oxide semiconductor transistor,
Said first current terminal of wherein said second oxide-semiconductor control transistors (ST2) is the collector terminal of said bipolar transistor or the drain terminal of said metal oxide semiconductor transistor, and
Said second current terminal of wherein said second oxide-semiconductor control transistors (ST2) is the emitter terminal of said bipolar transistor or the source terminal of said metal oxide semiconductor transistor.
8. semiconductor device according to claim 1,
Wherein said first oxide-semiconductor control transistors (ST1, ST3) be arranged to adjacent with said insulated gate transistor (21) or said diode (22).
9. semiconductor device according to claim 3,
It is adjacent with said insulated gate transistor (21) or said diode (22) that wherein said second oxide-semiconductor control transistors (ST2) is arranged to.
10. semiconductor device according to claim 1 also comprises:
Be formed into the insulated trench (ZK) of said Semiconductor substrate (1),
Wherein by said insulated trench (ZK) around said first oxide-semiconductor control transistors (ST1, ST3).
11. semiconductor device according to claim 1 also comprises:
Be formed into the insulated trench (ZK) of said Semiconductor substrate (1); And
Be formed into the buried insulator layer (ZU) of said Semiconductor substrate (1),
Wherein by said insulated trench (ZK) and said buried insulator layer (ZU) isolate said first oxide-semiconductor control transistors (ST1, ST3).
12. semiconductor device according to claim 1 also comprises:
Be formed into said Semiconductor substrate (1) and be positioned at said first oxide-semiconductor control transistors (ST1, first heavily doped layer under ST3) (N1, N2),
(N1 N2) has the conduction type identical with said Semiconductor substrate (1) and have the impurity concentration greater than said Semiconductor substrate (1) to wherein said first heavily doped layer.
13. semiconductor device according to claim 1 also comprises:
Be formed into second heavily doped layer (1a) of said Semiconductor substrate (1),
Wherein said second heavily doped layer (1a) has the conduction type identical with said Semiconductor substrate (1) and has the impurity concentration greater than said Semiconductor substrate (1),
Wherein said insulated gate transistor (21) has trench gate structure, and
Wherein said second heavily doped layer (1a) is positioned between the channel layer (2a) and drift layer of said insulated gate transistor (21).
14. according to each described semiconductor device among the claim 1-13,
Wherein said semiconductor device is installed on the vehicle.
15. an inverter circuit comprises:
A plurality of semiconductor device, wherein each are semiconductor device as claimed in claim 1.
16. inverter circuit according to claim 15,
Wherein said a plurality of semiconductor device comprises six semiconductor device and is configured to produce three-phase alternating current to be exported, and
Wherein said six semiconductor device be integrated in single semiconductor chip (IC1, IC2) in.
17. inverter circuit according to claim 15,
Wherein said a plurality of semiconductor device comprises six semiconductor device and is configured to produce three-phase alternating current to be exported, and
Three in wherein said six semiconductor device are integrated in first single semiconductor chip (IC3u), and
Other three in wherein said six semiconductor device are integrated in second single semiconductor chip (IC3d).
18. according to each described inverter circuit among the claim 15-17,
The said insulated gate transistor (21) of each in wherein said a plurality of semiconductor device and each in the said diode (22) they all are perpendicular elements, and electric current flows along the direction perpendicular to said Semiconductor substrate (1) surface in said perpendicular elements, and
Wherein said a plurality of semiconductor device is isolated from each other through the insulated trench (ZK) that penetrates said Semiconductor substrate (1) along said direction.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP290062/2007 | 2007-11-07 | ||
| JP2007290062 | 2007-11-07 | ||
| JP2008186427A JP4577425B2 (en) | 2007-11-07 | 2008-07-17 | Semiconductor device |
| JP186427/2008 | 2008-07-17 |
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| Publication Number | Publication Date |
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| CN101431075A CN101431075A (en) | 2009-05-13 |
| CN101431075B true CN101431075B (en) | 2012-06-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101748334A Expired - Fee Related CN101431075B (en) | 2007-11-07 | 2008-11-07 | Semiconductor device and inverter circuit having the same |
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| JP (1) | JP4577425B2 (en) |
| CN (1) | CN101431075B (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP2317553B1 (en) * | 2009-10-28 | 2012-12-26 | STMicroelectronics Srl | Double-sided semiconductor structure and method for manufacturing the same |
| JP5407808B2 (en) * | 2009-11-26 | 2014-02-05 | トヨタ自動車株式会社 | Power control device |
| US8816497B2 (en) | 2010-01-08 | 2014-08-26 | Transphorm Inc. | Electronic devices and components for high efficiency power circuits |
| JP5553652B2 (en) * | 2010-03-18 | 2014-07-16 | ルネサスエレクトロニクス株式会社 | Semiconductor substrate and semiconductor device |
| DE102012202180A1 (en) * | 2012-02-14 | 2013-08-14 | Robert Bosch Gmbh | Semiconductor arrangement for a current sensor in a power semiconductor |
| JP5990437B2 (en) * | 2012-09-10 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP2014072385A (en) * | 2012-09-28 | 2014-04-21 | Toyota Motor Corp | Semiconductor device |
| JP6077309B2 (en) * | 2013-01-11 | 2017-02-08 | 株式会社豊田中央研究所 | Diode and semiconductor device incorporating diode |
| JP5949727B2 (en) * | 2013-10-31 | 2016-07-13 | トヨタ自動車株式会社 | Power converter |
| JP5800006B2 (en) * | 2013-10-31 | 2015-10-28 | トヨタ自動車株式会社 | Semiconductor device |
| WO2015128975A1 (en) * | 2014-02-26 | 2015-09-03 | 株式会社日立製作所 | Power module and power conversion device |
| JP2016039477A (en) * | 2014-08-07 | 2016-03-22 | 株式会社デンソー | Drive controller |
| JP6428503B2 (en) * | 2015-06-24 | 2018-11-28 | 株式会社デンソー | Semiconductor device |
| JP2018137392A (en) * | 2017-02-23 | 2018-08-30 | トヨタ自動車株式会社 | Semiconductor device |
| JP7411465B2 (en) * | 2020-03-18 | 2024-01-11 | 日産自動車株式会社 | semiconductor equipment |
| CN116646351B (en) * | 2021-03-29 | 2024-02-09 | 新唐科技日本株式会社 | Semiconductor device, battery protection circuit and power management circuit |
| US20240014206A1 (en) | 2021-04-26 | 2024-01-11 | Mitsubishi Electric Corporation | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2837054B2 (en) * | 1992-09-04 | 1998-12-14 | 三菱電機株式会社 | Insulated gate semiconductor device |
| JPH0964707A (en) * | 1995-08-21 | 1997-03-07 | Matsushita Electron Corp | Semiconductor output circuit device |
| JP3381491B2 (en) * | 1995-11-30 | 2003-02-24 | 三菱電機株式会社 | Semiconductor element protection circuit |
| JPH10145206A (en) * | 1996-11-07 | 1998-05-29 | Hitachi Ltd | Protective circuit for semiconductor device |
| JP4504543B2 (en) * | 2000-09-22 | 2010-07-14 | 株式会社森本組 | Drilling method of parent-child shield and different diameter connecting segment for receiving reaction force |
| DE10300577B4 (en) * | 2003-01-10 | 2012-01-26 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Semiconductor device with vertical power device comprising a separation trench and method for its preparation |
| JP2005137072A (en) * | 2003-10-29 | 2005-05-26 | Nissan Motor Co Ltd | Overcurrent protecting circuit |
| JP2007134625A (en) * | 2005-11-14 | 2007-05-31 | Mitsubishi Electric Corp | Semiconductor device and its process for fabrication |
| JP2008072848A (en) * | 2006-09-14 | 2008-03-27 | Mitsubishi Electric Corp | Semiconductor device |
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2008
- 2008-07-17 JP JP2008186427A patent/JP4577425B2/en not_active Expired - Fee Related
- 2008-11-07 CN CN2008101748334A patent/CN101431075B/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| JP2009135414A (en) | 2009-06-18 |
| CN101431075A (en) | 2009-05-13 |
| JP4577425B2 (en) | 2010-11-10 |
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