CN101404321B - Method for producing vertical channel organic field effect transistor - Google Patents
Method for producing vertical channel organic field effect transistor Download PDFInfo
- Publication number
- CN101404321B CN101404321B CN2008102254539A CN200810225453A CN101404321B CN 101404321 B CN101404321 B CN 101404321B CN 2008102254539 A CN2008102254539 A CN 2008102254539A CN 200810225453 A CN200810225453 A CN 200810225453A CN 101404321 B CN101404321 B CN 101404321B
- Authority
- CN
- China
- Prior art keywords
- organic
- electrode
- layer
- gate electrode
- preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a method for manufacturing a vertical channel organic field effect transistor, and belongs to the field of organic microelectronics. The method mainly comprises the following steps: manufacturing a plane source electrode on an insulating substrate; depositing an insulating layer on a source electrode layer and enabling the insulating layer graphical so as to isolate a gate electrode and the source electrode; manufacturing the long strip-shaped gate electrode on the upper surface of the insulating layer; depositing a dielectric layer coating both ends of the gate electrode; depositing an organic semiconductor layer coating outside of the dielectric layer; depositing the insulating layer tightly close to the outside area of the semiconductor on the surface of the source electrode; manufacturing a plane drain electrode. The method adopts a low temperature process without damaging well done organic function films, and can be compatible with the prior silicon micro machining technology, make full use of the prior devices, and reduce the manufacture cost of new apparatus.
Description
Technical field
The present invention relates to organic electronic and learn field, the particularly preparation method of vertical channel organic field-effect transistor.
Background technology
Along with deepening continuously of information technology, electronic product has entered each link of people's life and work; People are increasing to the demand of low cost, flexibility, low weight, portable electronic product in daily life, and traditional device and circuit based on inorganic semiconductor material are difficult to satisfy these requirements, and the organic microelectric technique based on the organic polymer semi-conducting material that therefore can realize these characteristics has obtained people and more and more paid close attention under this trend.
Organic field effect tube is as the basic device of organic circuit, and its performance is to the performance decisive role of circuit.Wherein mobility has determined the speed of device work, and then influences the operating frequency of circuit; Voltage comprises operating voltage and threshold voltage, has determined the power consumption of device and circuit.
Because the amount of information explosive growth, people wish that all the time the information processing technology can be more and more faster, and the content that can handle is more and more.The factor of restriction information processing technology speed has a lot, comprises hardware aspect, also comprises the software aspect.The operating frequency of unit component is the basic problem of hardware aspect.The operating frequency that improves device mainly contains two paths: Yi Tiaolu and reduces channel length, and another road is to improve the mobility of charge carrier rate.Under the situation that does not have important breakthrough aspect the present material, the mobility of charge carrier rate improves very limited, and the method that therefore improves the device operating frequency mainly is exactly the length that reduces raceway groove.The factor of restriction information processing technology capacity equally also has a lot, mainly is the integrated level of circuit at hardware aspect.The integrated level that improves circuit need reduce the area of unit component.
Adopt the vertical channel organic field-effect transistor of method preparation of the present invention, by raceway groove is improved to vertical-type by traditional plane, thereby as long as the channel length that the film thickness by controlling organic semiconductor layer just can oxide-semiconductor control transistors, avoided the lower electron beam lithography of service efficiency, reduce the difficulty of preparation short channel organic transistor significantly, thereby reduced the cost of preparation.This structure can reduce the device area occupied effectively, improves the integrated level of circuit.Preparation method of the present invention has made the gate electrode of strip, thereby length-width ratio that can the regulated at will device channel has enlarged its range of application.Its structure of vertical channel organic field-effect transistor of method preparation of the present invention has adopted the structure of double channel, has increased the current driving ability of device.
Simultaneously, the preparation method of vertical channel organic field-effect transistor provided by the invention adopts low temperature process, can not cause damage to ready-made organic functional thin film, and can with existing silicon micromachining technology compatibility, can make full use of existing equipment, reduce the cost of new unit preparation.
Summary of the invention
In order to improve the integrated level of device operating frequency and circuit, the invention provides a kind of vertical channel organic field-effect transistor.Described technical scheme is as follows:
The present invention prepares the method for vertical channel organic field-effect transistor structure, and its step is as follows:
The drain electrode on step 7, preparation plane.
The preparation method of vertical channel organic field-effect transistor structure of the present invention,
In described step 1, the concrete grammar of preparation plane source electrode is: adopt the method for the hot physical deposition of vacuum, electron beam deposition or sputter to prepare metal electrode; Or adopt the method for inkjet printing, spin coating to prepare the organic substance electrode;
In described step 7, the concrete grammar of preparation plane drain electrode is: at first by photoetching technique gate electrode, medium and organic semiconductor are protected with photoresist; Come the deposit metal electrodes film by the method for the hot physical deposition of vacuum, electron beam deposition or sputter then, or adopt the method for inkjet printing or spin coating to come the sedimentary organic material electrode film; Remove the photoresist of gate electrode area and unnecessary electrode material by the method for peeling off at last.
The preparation method of vertical channel organic field-effect transistor structure of the present invention,
In described step 2, the concrete grammar of depositing insulating layer is on the electrode of source: adopt the method deposition inorganic insulation layer of low-pressure chemical vapor deposition (LPCVD), sputter or ald (ALD), or adopt spin coating or inkjet printing methods deposition organic insulator; Described patterned concrete grammar is: photoetching adds etching method;
In described step 6, the concrete grammar of depositing insulating layer is: at first by photoetching technique the strip district is protected with photoresist; Method by low-pressure chemical vapor deposition, sputter or ald deposits inorganic insulation layer then, perhaps deposits organic insulator by spin coating method; Remove the photoresist at gate electrode top and unnecessary insulating barrier at last.
The preparation method of vertical channel organic field-effect transistor structure of the present invention,
In described step 3, adopt photoetching technique to define its corresponding glue pattern of carving for metal gate electrode, come plated metal by the method for electron beam evaporation, sputter or thermal evaporation again, come transition diagram by the method for metal-stripping (lift-off) at last, thereby prepare gate electrode; Adopt inkjet printing methods to deposit for organic gate electrode with graphical.
The preparation method of vertical channel organic field-effect transistor structure of the present invention,
In described step 4, adopt the method for low-pressure chemical vapor deposition, sputter or ald to deposit inorganic gate dielectric layer, pass through anisotropic dry etching then the material removal medium beyond the sidewall, thereby obtain the gate dielectric layer of groove shape; Preparation for organic dielectric layer at first defines its figure by photoetching technique, comes the deposition medium film by spin coating technique then, after the annealed processing by lift-off technology the material removal medium beyond the strip district, thereby obtain the dielectric layer of groove shape.
The preparation method of vertical-channel organic crystalline field effect body tubular construction of the present invention,
In described step 5, semiconductive layer prepares film by vacuum heat deposition method at a slow speed, makes it have good step coverage, thereby can be wrapped in the gate dielectric layer both sides; By anisotropic dry etching the organic semiconducting materials beyond the sidewall is removed then, formed patterned active layer.
The beneficial effect of technical scheme provided by the invention is: the preparation method who adopts the vertical channel organic field-effect transistor of the present invention's proposition, by raceway groove is improved to vertical-type by traditional plane, thereby as long as the channel length that the film thickness by controlling organic semiconductor layer just can oxide-semiconductor control transistors, avoided the lower electron beam lithography of service efficiency, reduce the difficulty of preparation short channel organic transistor significantly, thereby reduced the cost of preparation.This structure can also reduce the device area occupied effectively, improves the integrated level of circuit.
In addition, adopt its structure of vertical channel organic field-effect transistor of method of the present invention preparation to adopt the gate electrode of strip, thereby length-width ratio that can the regulated at will device channel has enlarged its range of application.The structure that the present invention proposes has adopted the structure of double channel, has increased the current driving ability of device.
Simultaneously, the preparation method of vertical channel organic field-effect transistor of the present invention adopts low temperature process, can not cause damage to ready-made organic functional thin film, and can with existing silicon micromachining technology compatibility, can make full use of existing equipment, reduce the cost of new unit preparation.
Description of drawings
Fig. 1 is the planar structure schematic diagram that adopts the vertical channel organic field-effect transistor of method preparation provided by the invention;
Fig. 2 is the perspective view that adopts the vertical channel organic field-effect transistor of method preparation provided by the invention;
Fig. 3 is the flow chart of the preparation vertical channel organic field-effect transistor that provides of the embodiment of the invention;
The schematic diagram that on the SiO2 of thermal oxide growth dielectric substrate, prepares Au source, plane electrode that Fig. 4 provides for the embodiment of the invention;
The schematic diagram that on source electrode layer, passes through the electron-beam evaporation insulating barrier that Fig. 5 provides for the embodiment of the invention;
Fig. 6 passes through the schematic diagram that photoetching adds the lithographic technique patterned insulator layer for what the embodiment of the invention provided;
Fig. 7 passes through the schematic diagram that photoetching technique prepares the glue pattern of strip gate electrode for what the embodiment of the invention provided;
The electron-beam evaporation Au film that Fig. 8 provides for the embodiment of the invention prepares the schematic diagram of Au gate electrode then on insulating barrier by lift-off technology.
Fig. 9 makes around its gate electrode that is wrapped in strip for the technique for atomic layer deposition that passes through that the embodiment of the invention provides prepares the SiO2 dielectric layer, and removes the schematic diagram of strip district dielectric layer in addition by lithographic technique;
Figure 10 deposits organic semiconductor layer for what the embodiment of the invention provided on gate dielectric layer, it is wrapped in around the gate medium, removes organic semi-conductor schematic diagram beyond the strip district by lithographic technique;
The schematic diagram that passes through electron beam evaporation secondary deposition SiO2 insulating barrier that Figure 11 provides for the embodiment of the invention;
Figure 12 passes through electron beam evaporation for the preparation on insulating barrier that the embodiment of the invention provides, and photoetching and lithographic technique prepare the schematic diagram of plane Au drain electrode.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
By shown in Figure 1, adopt the basic structure of the vertical channel organic field-effect transistor of method preparation of the present invention to comprise the insulating barrier of dielectric substrate, metal gate electrode, dielectric layer, isolation source-drain electrode, vertical organic semiconductor layer, planar metal source electrode and planar metal drain electrode.
Dielectric substrate is the substrate of this structure, and its manufactured materials is the long silicon chip that insulation films such as silica, silicon nitride are arranged, or is insulating glass, ambroin film etc.
On dielectric substrate top is the source electrode, and the material of source electrode can be counted metal material for gold, platinum or silver-colored contour official letter, or is conductive organic matter such as PEDOT:PSS.The source electrode is a plane electrode, is tiled on the dielectric substrate.
Middle body on electrode top, source is a dielectric layer, and dielectric layer is U shape trench structure.The material of dielectric layer is inorganic dielectric material such as silica, silicon nitride, zirconia, aluminium oxide, tantalum oxide or hafnium oxide, or is polyimides (PI), polyethylene pyrrolidone (PVP), polymethyl acrylate (PMMA), Parylene organic media materials such as (parylene).
Dielectric layer inside at trench structure is gate electrode, and gate electrode is the strip structure, by the dielectric layer parcel wherein.Gate material is metallic conduction materials such as gold, aluminium, platinum, copper or silver, or is conductive organic matters such as PEDOT:PSS.
Both sides at electrode top, source, grooved dielectric layer are insulating barriers, the material of insulating barrier is inorganic insulating materials such as silica, silicon nitride, zirconia, aluminium oxide, tantalum oxide or hafnium oxide, perhaps also can be organic insulating materials such as polyimides, polyethylene pyrrolidone, polymethyl acrylate or Parylene.
Part between electrode top, source, two side insulation layers and dielectric layer has semiconductor layer respectively in addition, and semiconductor layer is kept apart insulating barrier and dielectric layer.The material of semiconductor layer is pentacene, CuPc (CuPc), P3HT, thiophene or red glimmering organic semiconducting materials such as rare.
Top at two side insulation layers and semiconductor layer is coated with drain electrode, the very plane electrode of leaking electricity, and its material is that gold, platinum or silver-colored contour official letter are counted metal material, or is conductive organic matter such as PEDOT:PSS.
In the present embodiment, vertical channel organic field-effect transistor of the present invention selects for use length the silicon chip of silica to be arranged as dielectric substrate; Au is as the plane source electrode; Strip Au is as metal gate electrode; Silicon dioxide is as dielectric layer; Pentacene is as organic semiconductor layer; Silicon dioxide is as insulating barrier; And select for use as the plane drain electrode.
In vertical channel organic field-effect transistor of the present invention, the height of dielectric layer U-lag is higher than the insulating barrier and the drain electrode of its both sides, can fully drain electrode, the semiconductor layer of gate electrode and both sides be kept apart; Simultaneously the dielectric layer U-lag the bottom effectively the source electrode isolation of gate electrode and its underpart is opened again.In addition, structure of the present invention guarantees that two parts semiconductor layer that dielectric layer connects side contacts with the drain electrode at dielectric layer and top and the source electrode of bottom respectively simultaneously.Owing in the gate electrode both sides semi-conducting material is arranged all, so the structure that the present invention proposes still is a kind of transistor of double channel.
As shown in Figure 3, the invention discloses a kind of method for preparing vertical channel organic field-effect transistor, its concrete preparation process is as follows:
Referring to Fig. 4 to Figure 12.
Step 101: gold source, preparation plane electrode on the thermal oxidation silicon dielectric substrate.The concrete preparation method of wherein used plane source electrode adopts the hot physical deposition of vacuum, electron beam deposition, splash-proofing sputtering metal electrode, the method for inkjet printing or spin coating organic substance electrode.
Step 102: depositing insulating layer on source electrode layer.Wherein the deposition process to inorganic insulation layer is low-pressure chemical vapor deposition (LPCVD), sputter or ald (ALD) etc.; Organic insulator is deposited as spin coating or inkjet printing etc.Adopt electron beam vapor deposition method deposition of silica insulating barrier in the present embodiment.
Step 103: add lithographic technique by photoetching insulating barrier is carried out graphically, so that isolate gate electrode and source electrode.
Step 104: the photoresist figure for preparing the strip gate electrode at the upper surface of insulating barrier.
Step 105: the upper surface at insulating barrier prepares the strip gate electrode.Come plated metal by methods such as electron beam evaporation, sputter or thermal evaporations, come transition diagram by the method for metal-stripping (lift-off) at last, thereby prepare gate electrode.Organic gate electrode adopts inkjet technology to deposit and is graphical.
Step 106: preparation dielectric layer.By low-pressure chemical vapor deposition, methods such as sputter or ald deposit, and make it have good step coverage, thereby can be wrapped in around the gate electrode.Pass through anisotropic dry etching then the material removal medium beyond the sidewall, thereby obtain the gate medium of groove shape.Secondly the preparation of organic dielectric layer at first defines its figure by photoetching technique, comes the deposition medium film by spin coating technique, after the annealed processing by lift-off technology the material removal medium beyond the strip district, thereby obtain the dielectric layer of groove shape.Adopt technique for atomic layer deposition and reactive ion etching technology to prepare the silica dioxide medium layer in the present embodiment.
Step 107: preparation semiconductor layer.Vacuum heat deposition method by at a slow speed prepares semiconductive thin film, makes it have good step coverage, thereby can be wrapped in the dielectric layer both sides.By anisotropic dry etching the organic semiconducting materials beyond the sidewall is removed then, formed patterned active layer.Adopt pentacene at the outside preparation of dielectric layer semiconductor layer in the present embodiment.
Step 108: secondary depositing insulating layer.At first the strip district is protected with photoresist by photoetching technique; Pass through low-pressure chemical vapor deposition on the surface of dielectric layer then, methods such as sputter or ald deposit inorganic insulation layer, and make on its two sides attached to dielectric layer; Perhaps deposit organic insulator by methods such as spin coatings; Remove the photoresist at gate electrode top and unnecessary insulating barrier at last.Adopt silica membrane to prepare insulating barrier in the present embodiment.
Step 109: preparation plane drain electrode.At first by photoetching technique gate electrode, medium and organic semiconductor are protected with photoresist, by the hot physical deposition of vacuum, technology such as electron beam deposition or sputter are come the deposit metal electrodes film then; Perhaps inkjet printing or spin coating technique come the sedimentary organic material electrode film, go then to remove the photoresist of gate electrode area and unnecessary electrode material by the method for peeling off, and finish the preparation of entire device.Adopt photoetching and lithographic technique to prepare plane gold drain electrode in the present embodiment.
The method for preparing vertical channel organic field-effect transistor of the present invention adopts low temperature process, can not cause damage to ready-made organic functional thin film, and can with existing silicon micromachining technology compatibility, can make full use of existing equipment, reduce the cost of new unit preparation.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a method for preparing the vertical channel organic field-effect transistor structure is characterized in that, described method concrete steps are as follows:
Step 1, on dielectric substrate preparation plane source electrode;
Step 2, on source electrode layer depositing insulating layer, and make it graphically with isolate gate electrode and source electrode;
Step 3, prepare the gate electrode of strip at the upper surface of insulating barrier;
Step 4, metallization medium layer make it be wrapped in the gate electrode both sides;
Step 5, deposition organic semiconductor layer make it be wrapped in the outside of dielectric layer;
Step 6, at the source electrode surface, be close to the lateral surface depositing insulating layer of organic semiconductor layer;
The drain electrode on step 7, preparation plane.
2. the preparation method of vertical channel organic field-effect transistor structure according to claim 1,
It is characterized in that in described step 1, the concrete grammar of preparation plane source electrode is: adopt the method for the hot physical deposition of vacuum, electron beam deposition or sputter to prepare metal electrode; Or adopt the method for inkjet printing, spin coating to prepare the organic substance electrode;
In described step 7, the concrete grammar of preparation plane drain electrode is: at first by photoetching technique gate electrode, dielectric layer and organic semiconductor layer are protected with photoresist; Come the deposit metal electrodes film by the method for the hot physical deposition of vacuum, electron beam deposition or sputter then, or adopt the method for inkjet printing or spin coating to come the sedimentary organic material electrode film; Remove the photoresist of gate electrode area and unnecessary electrode material by the method for peeling off at last.
3. the preparation method of vertical channel organic field-effect transistor structure according to claim 1,
It is characterized in that, in described step 2, the concrete grammar of depositing insulating layer is on the electrode of source: adopt the method deposition inorganic insulation layer of low-pressure chemical vapor deposition (LPCVD), sputter or ald (ALD), or adopt spin coating or inkjet printing methods deposition organic insulator; Described patterned concrete grammar is: photoetching adds etching method;
In described step 6, the concrete grammar of depositing insulating layer is: at first by photoetching technique the strip district is protected with photoresist; Method by low-pressure chemical vapor deposition, sputter or ald deposits inorganic insulation layer then, perhaps deposits organic insulator by spin coating method; Remove the photoresist at gate electrode top and unnecessary insulating barrier at last.
4. according to the preparation method of the described vertical channel organic field-effect transistor structure of claim 1,
It is characterized in that, in described step 3, adopt photoetching technique to define its corresponding glue pattern of carving for metal gate electrode, come plated metal by the method for electron beam evaporation, sputter or thermal evaporation again, come transition diagram by the method for metal-stripping (lift-off) at last, thereby prepare gate electrode; Adopt inkjet printing methods to deposit for organic gate electrode with graphical.
5. the preparation method of vertical channel organic field-effect transistor structure according to claim 1,
It is characterized in that, in described step 4, adopt the method for low-pressure chemical vapor deposition, sputter or ald to deposit inorganic gate dielectric layer, pass through anisotropic dry etching then, thereby obtain the gate dielectric layer of groove shape the material removal medium beyond the sidewall; Preparation for organic dielectric layer at first defines its figure by photoetching technique, comes the deposition medium film by spin coating technique then, after the annealed processing by lift-off technology the material removal medium beyond the strip district, thereby obtain the dielectric layer of groove shape.
6. the preparation method of vertical-channel organic crystalline field effect body tubular construction according to claim 1,
It is characterized in that in described step 5, semiconductor layer prepares film by the vacuum heat deposition method, makes it have step coverage, thereby can be wrapped in the gate dielectric layer both sides; By anisotropic dry etching the organic semiconducting materials beyond the sidewall is removed then, formed patterned active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102254539A CN101404321B (en) | 2008-10-31 | 2008-10-31 | Method for producing vertical channel organic field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102254539A CN101404321B (en) | 2008-10-31 | 2008-10-31 | Method for producing vertical channel organic field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101404321A CN101404321A (en) | 2009-04-08 |
| CN101404321B true CN101404321B (en) | 2011-04-20 |
Family
ID=40538242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008102254539A Active CN101404321B (en) | 2008-10-31 | 2008-10-31 | Method for producing vertical channel organic field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101404321B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8653584B2 (en) * | 2010-03-19 | 2014-02-18 | Nanya Technology Corp. | Dual vertical channel transistor and fabrication method thereof |
| CN102263200A (en) * | 2010-05-25 | 2011-11-30 | 中国科学院微电子研究所 | Organic field effect transistor and preparation method thereof |
| CN102263201A (en) * | 2010-05-25 | 2011-11-30 | 中国科学院微电子研究所 | Organic field effect transistor and preparation method thereof |
| CN102299260B (en) * | 2011-06-27 | 2013-12-25 | 福州华映视讯有限公司 | Manufacturing method of vertical organic thin film transistor |
| CN105322092B (en) * | 2014-12-04 | 2018-05-04 | 中国计量学院 | A kind of organic field-effect tube of composite channel |
| CN105789120B (en) * | 2016-05-23 | 2019-05-31 | 深圳市华星光电技术有限公司 | The production method and TFT substrate of TFT substrate |
| CN106953011B (en) * | 2017-03-28 | 2019-04-30 | 武汉华星光电技术有限公司 | Vertical-channel Organic Thin Film Transistors and preparation method thereof |
| CN107478320B (en) | 2017-08-23 | 2019-11-05 | 京东方科技集团股份有限公司 | Transistor sound sensing element and preparation method thereof, sonic transducer and portable equipment |
| CN109449121B (en) * | 2018-10-26 | 2022-04-19 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN116799057A (en) * | 2022-03-14 | 2023-09-22 | 华为技术有限公司 | Vertical channel transistor structure and manufacturing method |
-
2008
- 2008-10-31 CN CN2008102254539A patent/CN101404321B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101404321A (en) | 2009-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101404321B (en) | Method for producing vertical channel organic field effect transistor | |
| CN101447552B (en) | Tubular gate electrode vertical channel organic field-effect transistor and preparation method thereof | |
| US9088000B2 (en) | Transistor structures and methods of fabrication thereof | |
| CN1186822C (en) | Organic film transistor and preparing method | |
| CN102867914B (en) | The manufacture method of electronic device and semiconductor devices | |
| CN103325836B (en) | A kind of graphene field effect transistor and preparation method thereof | |
| CN101308904A (en) | Organic thin-film transistor and manufacture method thereof | |
| TW200524012A (en) | Method for forming metal single-layer film, method for forming wiring, and method for producing field effect transistors | |
| CN104766888A (en) | High-dielectric-constant gate dielectric composite channel field effect transistor and preparing method thereof | |
| CN101257092B (en) | Organic thin-film transistor and manufacturing method thereof | |
| CN1282259C (en) | Organic semiconductor FET with protecting layer and its making process | |
| CN102117887A (en) | Low-voltage organic thin-film transistor and preparation method thereof | |
| CN102683592A (en) | Method for preparing organic field effect transistor structure | |
| CN1144301C (en) | Organic film transistor switch device and making method thereof | |
| CN114242780A (en) | Indium tin oxide vertical ring grid field effect transistor and preparation method thereof | |
| CN101425562B (en) | Nano-scale channel organic field effect transistor and preparation thereof | |
| CN102263201A (en) | Organic field effect transistor and preparation method thereof | |
| JP2004349292A (en) | Field-effect transistor and its fabricating process | |
| CN101393966A (en) | Dual dielectric layer organic field-effect transistors and preparation thereof | |
| CN102263200A (en) | Organic field effect transistor and preparation method thereof | |
| CN104332559A (en) | Low operation voltage organic field effect transistor and preparation method thereof | |
| CN100421279C (en) | Organic thin film transistor device having modification layer and processing method thereof | |
| CN105470389A (en) | Three-dimensional structured flexible organic field effect transistor | |
| CN105679939A (en) | Doped thiophene isoindigo-based organic thin-film field effect transistor and preparation method thereof | |
| CN102683591A (en) | Method for preparing organic field effect transistor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |