CN102299260B - Manufacturing method of vertical organic thin film transistor - Google Patents
Manufacturing method of vertical organic thin film transistor Download PDFInfo
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- CN102299260B CN102299260B CN 201110174163 CN201110174163A CN102299260B CN 102299260 B CN102299260 B CN 102299260B CN 201110174163 CN201110174163 CN 201110174163 CN 201110174163 A CN201110174163 A CN 201110174163A CN 102299260 B CN102299260 B CN 102299260B
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Abstract
The invention discloses a vertical organic thin film transistor and a manufacturing method thereof. The vertical organic thin film transistor comprises a source electrode layer, a first patterned insulation layer, a patterned gate electrode layer, a second patterned insulation layer, an organic semiconductor layer and a drain electrode layer, wherein the first patterned insulation layer is arranged on the source electrode layer, the patterned gate electrode layer is correspondingly arranged on the first patterned insulation layer, the second patterned insulation layer has the preset thickness and is covered on the patterned gate electrode layer, and the local surface of the source electrode layer is exposed out. The organic semiconductor layer is covered on the second patterned insulation layer and the local surface. The drain electrode layer is arranged on the organic semiconductor layer.
Description
Technical field
The invention relates to a kind of transistor and preparation method thereof, be particularly to a kind of vertical organic thin film transistor and preparation method thereof.
Background technology
Industry normally adopts plane formula transistor (planar transistor) as basic circuit unit.In general, so-called plane formula transistor is to refer to that transistorized gate channel (gate channel) is parallel with the surface of substrate, and transistorized drain/source region is separately positioned on this gate passage two ends.
The plane formula transistor has easily and circuit integrated advantage, thereby is applied to widely the manufacture of integrated circuit.Yet the plane formula transistor can occupy more substrate surface area, make the integration of integrated circuit to promote.In addition, in field of liquid crystal, along with picture is day by day meticulous, the area of its single picture element is also more and more less, causes the ratio of the shared picture element area of existing plane formula thin-film transistor increasing, and this has caused aperture opening ratio decline, contrasts not high problem.
Therefore, in order to overcome the transistorized area constraints of plane formula, someone has proposed vertical type bipolar transistor.Yet, manufacture the method for vertical type bipolar transistor because it needs complicated multiple tracks exposure imaging processing procedure, therefore be not suitable for volume production.
On the other hand, display towards gentlier, the target development of thinner, deflection, lower OTFT (the Organic Thin Film Transistor for the interdependency of substrate, OTFT) be developed, its great advantage is that assembly can be in the lower making of low temperature (<200 ℃), applicable to plastic base, and the transistor component characteristic still can maintain when panel bending.
By this, someone has proposed vertical organic thin film transistor and has overcome the problems referred to above.Yet vertical organic thin film transistor is higher in making upper degree of difficulty.Generally speaking, utilize traditional manufacture of semiconductor to make the assembly of vertical stratification, need to carry out multiple tracks film forming processing procedure and patterning process, therefore need to make the multiaspect light shield.Therefore not only on processing procedure, make comparatively complexity, also can make manufacturing cost increase.And, through the organic semiconductor characteristic after micro image etching procedure, all destroy to some extent, can't obtain good component characteristic and make through the OTFT of the vertical stratification of method made thus.
People Advanced Materials in document such as Fujimoto Kiyoshi, 19,525,2007 propose to utilize polystyrene (polystyrene, PS) characteristic of the own mutual exclusion of rice spheroid how, and coordinate the electrostatic control of substrate to produce vertical organic thin film transistor.Yet, controlling the positional stability of diameter polystyrene spheres on substrate with electrostatic means not good, therefore to the position of the vertical channel of position that should diameter polystyrene spheres, also can't precisely control.In addition, it utilizes aluminium to be used as the gate metal, and with the oxide layer (aluminium oxide Al of aluminium self-assembling formation
2o
3) as insulating barrier, and form vague and general layer (depletion layer) with the contact interface of this insulating barrier and organic semiconductor layer.Yet the thickness of oxide layer is very thin, the voltage therefore be applied thereto can not be too large, in order to avoid cause the damage of this vertical organic thin film transistor.Moreover, in general, due to the more general inorganic thin-film transistors of conductivity of OTFT come poor, therefore need to use conductivity preferably metal as electrode, and in the document, use aluminium will cause the electrical characteristic of made vertical organic thin film transistor not good as gate electrode.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of vertical organic thin film transistor, it can adopt the good metal of conductivity as gate electrode, and the insulating barrier that a predetermined thickness is set is thereon to solve problem withstand voltage and that electrical characteristic is not good.
Another object of the present invention is to provide a kind of method of making above-mentioned vertical organic thin film transistor, it utilizes soft printing moulding (micro contact) technology, has overcome traditional sky high cost problem that needs the multiple tracks optical cover process.
In order to achieve the above object, the vertical organic thin film transistor of preferred embodiment of the present invention comprises a substrate, one source pole layer, one first patterned insulation layer, a patterned gate, one second patterned insulation layer, an organic semiconductor layer and a drain layer.
This source layer is arranged at this substrate surface.This first patterned insulation layer is arranged on source layer, and exposes a local surfaces of this source layer.This patterned gate correspondence is arranged on this first patterned insulation layer.This second patterned insulation layer has a predetermined thickness, and this second patterned insulation layer is covered in this patterned gate and this first patterned insulation layer, and exposes this local surfaces.This organic semiconductor layer is covered in this second patterned insulation layer and this local surfaces.This drain layer is arranged on this organic semiconductor layer, and wherein this organic semiconductor layer is as the vertical channel between this source layer and drain layer.
In a preferred embodiment, the predetermined thickness of this second patterned insulation layer between 10 how rice to 2 microns between, and this second patterned insulation layer is an inorganic insulation layer, is for example silicon nitride.In addition, this first patterned insulation layer is an organic insulator, and its material is polyimides.
For reaching another purpose, the invention provides a kind of manufacture method of vertical organic thin film transistor, it comprises the following steps: to utilize one first film benevolence to impress out the one source pole layer on a substrate; Utilize one second film benevolence to impress out one first patterned insulation layer on this source layer, this first patterned insulation layer covers this source layer but exposes one of this source layer local surfaces; Utilize this second film benevolence to impress out a patterned gate on this first patterned insulation layer; Utilize an optical cover process to form one second patterned insulation layer with a predetermined thickness, this second patterned insulation layer is covered in this patterned gate and this first patterned insulation layer, and exposes this local surfaces of this source layer; Utilize this tertiary membrane benevolence to impress out an organic semiconductor layer on this second patterned insulation layer and this local surfaces; And utilize this tertiary membrane benevolence to impress out a drain layer on this organic semiconductor layer.
In one embodiment, impression system implements with soft printing moulding (micro contact) processing procedure.Preferably, the material of this first, second and third film benevolence is to be nickel or dimethyl silicone polymer (PDMS).In one embodiment, this optical cover process is to lift (lift off) method.
According to vertical organic thin film transistor of the present invention and preparation method thereof, it only makes this second patterned insulation layer with one optical cover process, and can control the electrical characteristic that this predetermined thickness is adjusted vertical organic thin film transistor, solve by this problem withstand voltage and that electrical characteristic is not good.In addition, the present invention's manufacture method adopts soft printing molding manufacture procedure, has overcome traditional sky high cost problem that needs the multiple tracks optical cover process.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below.
The accompanying drawing explanation
Fig. 1 illustrates the vertical organic thin film transistor of preferred embodiment of the present invention.
Fig. 2 illustrates the flow chart of manufacture method of the vertical organic thin film transistor of preferred embodiment of the present invention.
Fig. 3 illustrates the schematic diagram of step S10.
Fig. 4 illustrates the schematic diagram of step S20.
Fig. 5 illustrates the schematic diagram of step S30.
Fig. 6 A to Fig. 6 C illustrates the schematic diagram of step S40.
Fig. 7 illustrates the schematic diagram of step S50.
Fig. 8 illustrates the schematic diagram of step S60.
[primary clustering symbol description]
100 vertical organic thin film transistor 110 substrates
120 source layer 122 local surfaces
125 rice gold particle 130 first patterned insulation layers how
135 polyimides 140 patterned gate
150 second patterned insulation layer 152 light resistance structures
154 inorganic insulation layer 160 organic semiconductor layers
165 pentacene 170 drain layers
220 first film benevolence 240 second film benevolence
260 tertiary membrane benevolence D predetermined thickness
The distance of d two plates
Embodiment
Specification of the present invention provides different embodiment that the technical characterictic of the different execution modes of the present invention is described.Wherein, the configuration of each assembly in embodiment is the content disclosed for clearly demonstrating the present invention, not in order to limit the present invention.And in different embodiment, the part of reference numerals repeats, and is for the purpose of simplifying the description, not means the relevance between different embodiment.
Please refer to Fig. 1, Fig. 1 illustrates the vertical organic thin film transistor of preferred embodiment of the present invention, should notice that it not means with actual ratio.This vertical organic thin film transistor 100 comprises a substrate 110, one source pole layer 120, one first patterned insulation layer 130, a patterned gate 140, one second patterned insulation layer 150, an organic semiconductor layer 160 and a drain layer 170.This substrate 110 is preferably flexible base plate, plastic base for example, and its better material can be poly-to naphthalenedicarboxylic acid ethyl ester (PEN), ethylene terephthalate (PET), polyether sulfone (PES) and polyimides (PI).Yet the present invention is not limited to implement with flexible base plate, general glass substrate also can be implemented.
This source layer 120 is arranged at this substrate 110 surfaces, and its material is preferably gold.Should be noted, be only Local Representation in Fig. 1, and source layer 120 not covers all surfaces of this substrate 110.This first patterned insulation layer 130 is arranged on source layer 120, and exposes a local surfaces 122 of this source layer 120.The material of this first patterned insulation layer 130 is preferably polyimides (PI) or fluorinated polymer (CYTOP).
These patterned gate 140 correspondences are arranged on this first patterned insulation layer 130, and its material is preferably the high conductivity metals such as gold or silver, thereby can increase this organic semi-conductor conductivity.Accordingly, be difficult for forming oxide layer on this patterned gate 140.
This second patterned insulation layer 150 has a predetermined thickness D, and this second patterned insulation layer 150 is covered in the side of this patterned gate 140 and this first patterned insulation layer 130, and exposes this local surfaces 122 of this source layer 120.It should be noted that this second patterned insulation layer 150 is to form (its details is specified in rear) with an optical cover process, therefore can control its predetermined thickness D.The predetermined thickness of this second patterned insulation layer 150 between 10 how rice to 2 microns between, and this second patterned insulation layer 150 is an inorganic insulation layer, is for example silicon nitride (SiN
x) or silica (SiO
2).
This organic semiconductor layer 160 is covered in this second patterned insulation layer 150 and this local surfaces 122, to contact with this source layer 120.Preferably, the material of this organic semiconductor layer 160 is pentacene (pentacene) or copper phthalocyanine (copper phthalocyanine, CuPc).This drain layer 170 is arranged on organic semiconductor layer 160, and wherein this organic semiconductor layer 160 is as the vertical channel between this source layer 120 and drain layer 170.
Compared to known techniques, the present invention utilizes optical cover process to make this second patterned insulation layer 150, and can control the electrical characteristic that this predetermined thickness D adjusts vertical organic thin film transistor.For instance, this patterned gate 140 and drain layer 170 can be considered two parallel metal sheets of capacitor, between two plates, fill out with medium (second patterned insulation layer 150 and organic semiconductor layer 160).The size of electric capacity is directly proportional to the area A of metallic plate and the dielectric coefficient ε of medium, and and being inversely proportional to apart from d between two plates, i.e. C=(ε A)/d.Therefore, the present invention can control the predetermined thickness D of the second patterned insulation layer 150, further control and change capacitance apart from d between two plates, improve by this in known techniques that only to using the oxide layer (aluminium oxide) of self-assembling formation too thin and can't apply the shortcoming of large voltage as the thickness of insulating barrier.
Below will describe the step of making above-mentioned vertical organic thin film transistor 100 in detail.Please refer to Fig. 2, Fig. 2 illustrates the flow chart of manufacture method of the vertical organic thin film transistor of preferred embodiment of the present invention.The method starts from step S10.
Please refer to Fig. 3, Fig. 3 illustrates the schematic diagram of step S10.In step S10, utilize one first film benevolence 220 to impress out source layer 120 on a substrate 110.Should be noted, above-mentioned impression refers to soft printing moulding (micro contact) processing procedure and implements.Particularly, this first film benevolence 220 first is stained with glutinous how rice gold particle 125 or other applicable material, more how a rice gold particle 125 is stamped on this substrate 110, then seeing through the demoulding known of this technical field, release how a rice gold particle 125 remains on this substrate 110.Wherein this first film benevolence 220 is preferably nickel or soft dimethyl silicone polymer (PDMS).
Please refer to Fig. 4, Fig. 4 illustrates the schematic diagram of step S20.In step S20, utilize one second film benevolence 240 to impress out the first patterned insulation layer 130 on this source layer 120, this first patterned insulation layer 130 covers these source layers 120 but exposes the local surfaces 122 of this source layer 120.Similarly, above-mentioned impression refers to soft printing moulding (micro contact) processing procedure.For example, this second film benevolence 240 first is stained with glutinous polyimides (PI) 135 or other applicable material, then polyimides 135 is stamped on this source layer 120.Wherein this second film benevolence 240 is preferably nickel or soft dimethyl silicone polymer (PDMS).
Please refer to Fig. 5, Fig. 5 illustrates the schematic diagram of step S30.In step S20, utilize this second film benevolence 240 to impress out patterned gate 140 on this first patterned insulation layer 130.Should be noted, patterned gate 140 is identical with the profile of the first patterned insulation layer 130, therefore can use same die impression, i.e. this second film benevolence 240.Similarly, this second film benevolence 240 first is stained with glutinous how rice gold particle 125, more how a rice gold particle 125 is stamped on this first patterned insulation layer 130.
Please refer to Fig. 6 A to Fig. 6 C, Fig. 6 A to Fig. 6 C illustrates the schematic diagram of step S40.In step S40, utilize an optical cover process to form the second patterned insulation layer 150 with a predetermined thickness D, this second patterned insulation layer 150 is covered in this patterned gate 140 and this first patterned insulation layer 130, and exposes this local surfaces 122 of this source layer 120.In this preferred embodiment, this optical cover process is to lift (lift off) method.Specifically, utilize a light shield to form a light resistance structure 152 in this local surfaces 122, as shown in Figure 6A.Then, the long-pending one deck inorganic insulation layer 154 in Shen, be for example silicon nitride (SiN thereon
x) or silica (SiO
2), as shown in Figure 6B.Finally, this light resistance structure 152 and part inorganic insulation layer 154 are got rid of in the agent of recycling stripping, and draw this second patterned insulation layer 150, as shown in Figure 6 C.
Please refer to Fig. 7, Fig. 7 illustrates the schematic diagram of step S50.In step S50, utilize a tertiary membrane benevolence 260 to impress out organic semiconductor layer 160 on this second patterned insulation layer 150 and this local surfaces 122.Similarly, this tertiary membrane benevolence 260 first is stained with glutinous pentacene 165 or other applicable material, then pentacene 165 is stamped on this second patterned insulation layer 150 and this local surfaces 122.Wherein this tertiary membrane benevolence 260 is preferably nickel or soft dimethyl silicone polymer (PDMS).
Please refer to Fig. 8, Fig. 8 illustrates the schematic diagram of step S60.In step S60, utilize this tertiary membrane benevolence 260 to impress out drain layer 170 on this organic semiconductor layer 160, finally obtain the vertical organic thin film transistor 100 of this preferred embodiment.Should be noted, drain layer 170 is identical with the profile of organic semiconductor layer 160, therefore can use same die impression, i.e. this tertiary membrane benevolence 260.Similarly, this tertiary membrane benevolence 260 first is stained with glutinous how rice gold particle 125 or other applicable material, more how a rice gold particle 125 is stamped on this organic semiconductor layer 160.
In sum, according to vertical organic thin film transistor of the present invention and preparation method thereof, it only makes this second patterned insulation layer 150 with one optical cover process, and can control the electrical characteristic that this predetermined thickness D adjusts vertical organic thin film transistor, solve by this problem withstand voltage and that electrical characteristic is not good.In addition, manufacture method of the present invention adopts soft printing molding manufacture procedure, has overcome traditional sky high cost problem that needs the multiple tracks optical cover process.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; the persond having ordinary knowledge in the technical field of the present invention; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (4)
1. the manufacture method of a vertical organic thin film transistor, is characterized in that, it comprises the following steps:
Utilize one first film benevolence to impress out the one source pole layer on a substrate;
Utilize one second film benevolence to impress out one first patterned insulation layer on this source layer, this first patterned insulation layer covers this source layer but exposes a local surfaces of this source layer;
Utilize this second film benevolence to impress out a patterned gate on this first patterned insulation layer;
Utilize an optical cover process to form one second patterned insulation layer with a predetermined thickness, this second patterned insulation layer is covered in the side of this patterned gate and this first patterned insulation layer, and exposes this local surfaces of this source layer;
Utilize this tertiary membrane benevolence to impress out an organic semiconductor layer on this second patterned insulation layer and this local surfaces; And
Utilize this tertiary membrane benevolence to impress out a drain layer on this organic semiconductor layer.
2. according to the manufacture method of 1 described vertical organic thin film transistor of claim the, it is characterized in that, wherein impression is to implement with soft printing molding manufacture procedure.
3. according to the manufacture method of 1 described vertical organic thin film transistor of claim the, it is characterized in that, wherein the material of this first, second and third film benevolence is to be nickel or dimethyl silicone polymer.
4. according to the manufacture method of 1 described vertical organic thin film transistor of claim the, it is characterized in that, wherein this optical cover process is the method for lifting.
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| CN 201110174163 CN102299260B (en) | 2011-06-27 | 2011-06-27 | Manufacturing method of vertical organic thin film transistor |
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|---|---|---|---|
| CN 201110174163 CN102299260B (en) | 2011-06-27 | 2011-06-27 | Manufacturing method of vertical organic thin film transistor |
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| CN102299260A CN102299260A (en) | 2011-12-28 |
| CN102299260B true CN102299260B (en) | 2013-12-25 |
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| CN103915507A (en) * | 2012-12-31 | 2014-07-09 | 瀚宇彩晶股份有限公司 | Oxide thin film transistor structure and method for producing same |
| TWI655477B (en) * | 2018-04-18 | 2019-04-01 | 友達光電股份有限公司 | Active element substrate manufacturing method |
Citations (5)
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|---|---|---|---|---|
| DE10057502A1 (en) * | 2000-11-20 | 2002-05-29 | Siemens Ag | Organic field effect transistor has at least two current channels and/or one vertical current channel transverse to surface of substrate formed by field effect when voltage applied |
| CN1661813A (en) * | 2004-02-26 | 2005-08-31 | 三星Sdi株式会社 | TFT, flat panel display device having the same, method of manufacturing TFT, method of manufacturing flat panel display device, and method of manufacturing donor sheet |
| CN1906771A (en) * | 2004-10-04 | 2007-01-31 | 松下电器产业株式会社 | Vertical field effect transistor and method for fabricating the same |
| CN101404321A (en) * | 2008-10-31 | 2009-04-08 | 中国科学院微电子研究所 | Vertical channel organic field effect transistor and preparation method thereof |
| CN101447552A (en) * | 2008-11-25 | 2009-06-03 | 中国科学院微电子研究所 | Tubular gate electrode vertical channel organic field effect transistor and preparation method thereof |
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2011
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10057502A1 (en) * | 2000-11-20 | 2002-05-29 | Siemens Ag | Organic field effect transistor has at least two current channels and/or one vertical current channel transverse to surface of substrate formed by field effect when voltage applied |
| CN1661813A (en) * | 2004-02-26 | 2005-08-31 | 三星Sdi株式会社 | TFT, flat panel display device having the same, method of manufacturing TFT, method of manufacturing flat panel display device, and method of manufacturing donor sheet |
| CN1906771A (en) * | 2004-10-04 | 2007-01-31 | 松下电器产业株式会社 | Vertical field effect transistor and method for fabricating the same |
| CN101404321A (en) * | 2008-10-31 | 2009-04-08 | 中国科学院微电子研究所 | Vertical channel organic field effect transistor and preparation method thereof |
| CN101447552A (en) * | 2008-11-25 | 2009-06-03 | 中国科学院微电子研究所 | Tubular gate electrode vertical channel organic field effect transistor and preparation method thereof |
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