TWI655477B - Active element substrate manufacturing method - Google Patents

Abstract

A method for manufacturing an active element substrate includes: forming a source on a display area of the substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; forming a semiconductor layer on the auxiliary insulating layer, The semiconductor layer is electrically connected to the source through the opening; a gate insulating layer is formed on the opening, the semiconductor layer, and the auxiliary insulating layer; and a gate is formed on the opening, the semiconductor layer, and the gate insulating layer.

Description

Manufacturing method of active element substrate

The present invention relates to a method for manufacturing an active element substrate, and more particularly, to a method for manufacturing an active element substrate having a semiconductor layer formed on an auxiliary insulating layer.

At present, vertical thin film transistors (vertical thin film transistors, vertical TFTs) are gradually valued by many companies. Vertical thin film transistors have higher carrier mobility and can be used in devices with higher frequencies and lower operating bias.

However, in the manufacturing process of the vertical thin-film transistor, the active layer needs to cover multiple film layers at the same time. Therefore, multiple coating processes and patterning processes are required, and multiple photomasks are required. In this way, not only the complexity of the process is high, but the manufacturing cost is also difficult to reduce. In addition, the edges of the multiple film layers formed by the multi-layer coating process will appear stepped, so that when the active layer covers the stepped structure, the active layer is prone to poor film formation due to the uneven edges, which affects the vertical thin film electricity. Electron transfer within the crystal. Therefore, there is an urgent need for a method that can solve the aforementioned problems.

An embodiment of the present invention provides a method for manufacturing an active device substrate, which can increase the startup current of the active device.

A method for manufacturing an active device substrate according to an embodiment of the present invention includes: forming a source on a display area of the substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; forming a semiconductor Layer on the auxiliary insulating layer, the semiconductor layer is electrically connected to the source through the opening; forming a gate insulating layer on the opening, the semiconductor layer and the auxiliary insulating layer; and forming a gate on the opening, the semiconductor layer and the gate insulating layer .

One of the objectives of the present invention is to reduce the difficulty of manufacturing the active device substrate.

One of the objects of the present invention is to increase the starting current of an active device.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic top view of an active device substrate according to an embodiment of the present invention. 2A to 2M are schematic partial cross-sectional views of a method for manufacturing an active element substrate according to an embodiment of the present invention. 3A to 3I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that FIGS. 2C to 2I are schematic cross-sectional views taken along the line AA ′ of FIGS. 3A to 3G, respectively; FIG. 2K is a schematic cross-sectional view taken along the line AA ′ of FIG. 3H; AA ′ is a schematic cross-sectional view, in which the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For convenience of explanation, the illustration of the insulating layer is omitted in FIGS. 3A to 3I, and the position of the opening OP is indicated by a dotted line.

Referring to FIG. 1, the substrate 100 of the active device substrate 10 includes a display area AR and a peripheral area BR. The peripheral area BR is located on one side of the display area AR, or the peripheral area BR surrounds the display area AR. In other words, the peripheral area BR can be located on one side of the display area AR, and can be adjusted according to different needs. For example, when applied to a rectangular display area, the surrounding area BR is surrounded by the display area AR or may be located on one side, two sides, or three sides of the display area AR; applied to a non-rectangular display area or a circular display In the area, the peripheral area BR may be adjacent to the display area AR, for example, it may be a portion or all of the periphery of the display area AR. In this embodiment, the active device substrate 10 further includes a fan-out line 102 and a flexible circuit board 104. The fan-out line 102 and the flexible circuit board 104 are located on the peripheral area BR, and the fan-out line 102 extends from the peripheral area BR into the display area AR. For example, the fan-out line 102 is electrically connected to the flexible circuit board 104 on the peripheral area BR and the active component on the display area AR.

FIGS. 2A to 2I and FIGS. 3A to 3M are, for example, partially enlarged schematic diagrams of a method for manufacturing the display area AR of the active device substrate 10.

Please refer to FIG. 2A and FIG. 3A, a source S and a data line DL are formed on the display area AR of the substrate 100, and the data line DL is electrically connected to the source S.

Referring next to FIG. 2B, an auxiliary insulating layer 110 is formed on the source S. In this embodiment, the material of the auxiliary insulating layer 110 may include siloxane, polyimide, silicon nitride, other suitable materials, or A stacked layer of the at least two materials. In some embodiments, the auxiliary insulating layer 110 is further formed on the data line DL.

Referring to FIG. 2C and FIG. 3A at the same time, an opening OP is formed in the auxiliary insulating layer 110 to expose the source S.

Referring to FIG. 2D and FIG. 3B, a semiconductor material layer SM is formed on the upper surface of the auxiliary insulating layer 110. The semiconductor material layer SM covers the opening OP. The material of the semiconductor material layer SM includes, for example, indium gallium zinc oxide, indium zinc tin oxide, or indium gallium tin oxide.

Referring to FIG. 2E and FIG. 3C, a first patterned photoresist layer 120 is formed on the semiconductor material layer SM and the opening OP. The method for forming the first patterned photoresist layer 120 includes, for example, coating a photoresist material on the semiconductor material layer SM and the opening OP, and then performing a photolithography process on the photoresist material.

Please refer to FIG. 2F and FIG. 3D. With the first patterned photoresist layer 120 as a mask, a part of the semiconductor material layer SM is removed to form a semiconductor layer 130. The semiconductor layer 130 is electrically connected to the source S through the opening OP. The semiconductor layer 130 and the first patterned photoresist layer 120 expose a part of the upper surface of the auxiliary insulating layer 110. In this embodiment, the material of the semiconductor layer 130 includes, for example, indium gallium zinc oxide, indium zinc tin oxide, or indium gallium tin oxide.

Please refer to FIG. 2G and FIG. 3E together to form a second patterned photoresist layer 140. For example, an ashing process is performed on the first patterned photoresist layer 120 to remove a portion of the first patterned photoresist layer 120 that is not located on the opening OP to form a second patterned photoresist layer 140. In this embodiment, the second patterned photoresist layer 140 is located in the opening OP, and a portion of the semiconductor layer 130 that is not located in the opening OP is substantially exposed. The steps of performing the ashing process include, for example, applying carbon tetrafluoride or oxygen, but the present invention is not limited thereto.

Referring to FIG. 2H and FIG. 3F at the same time, a part of the semiconductor layer 130 is subjected to a conductive process to define a semiconductor channel CH, a drain electrode D, and a pixel electrode PE. The semiconductor channel CH is part of the semiconductor layer 130 '. The conductivity of the drain electrode D and the pixel electrode PE is higher than that of the semiconductor channel CH. The drain electrode D is connected to the semiconductor channel CH, and the pixel electrode PE is electrically connected to the drain electrode D. For example, the pixel electrode PE contacts the drain electrode D and does not contact the semiconductor channel CH.

The step of conducting the conductive process includes, for example, applying the second patterned photoresist layer 140 as a mask and applying hydrogen to the semiconductor layer 130, but the present invention is not limited thereto. In this embodiment, by using the second patterned photoresist layer 140 as a mask, the edge position of the semiconductor channel CH can be accurately controlled during the conducting process. In this embodiment, a part of the semiconductor channel CH substantially surrounds the sidewall of the opening OP. In this embodiment, the length L of the semiconductor channel CH is approximately the length of the sidewall of the opening OP, and the length L of the semiconductor channel CH refers to the effective length of the semiconductor channel CH. By setting the auxiliary insulating layer 110, the length L can be accurately controlled. In this embodiment, the length L of the semiconductor channel CH is about 0.5 μm to 4 μm, and preferably set to 1 μm to 2 μm. In this embodiment, the pixel electrode PE is not located in the opening OP and is viewed along the normal direction N of the substrate 100. A part of the drain electrode D is located between the semiconductor channel CH and the pixel electrode PE. The drain electrode D For example, it is ring-shaped and located on the upper surface of the auxiliary insulating layer 110.

Referring to FIG. 2I and FIG. 3G at the same time, the second patterned photoresist layer 140 is removed to expose the semiconductor layer 130 'located in the opening OP. The method of removing the second patterned photoresist layer 140 is, for example, a photoresist peeling process or an ashing process, but the invention is not limited thereto. If viewed in the normal direction N of the substrate 100, the pattern of the semiconductor layer 130 'in the opening OP is circular or oval, but the invention is not limited thereto.

Referring to FIG. 2J, a gate insulating layer GI is formed on the opening OP, the semiconductor layer 130 ', the drain electrode D, the pixel electrode PE, and the auxiliary insulating layer 110. The gate insulating layer GI covers the drain electrode D and the pixel electrode PE.

Please refer to FIG. 2K and FIG. 3H together to form a gate G on the opening OP, the semiconductor layer 130 ', and the gate insulating layer GI. In this embodiment, the gate G overlaps the drain D and the source S in the normal direction N of the substrate 100, respectively. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scanning line SL. At this time, the production of the active element T has been completed. The active element T is a top gate thin film transistor.

Referring to FIG. 2L, an interlayer insulating layer 150 is formed on the gate G. In some embodiments, the insulating layer 150 is further formed on the scan line SL.

Please refer to FIG. 2M and FIG. 3I, a common electrode COM is formed on the interlayer insulating layer 150. So far, the fabrication of the active device substrate 10 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE and a part of the drain electrode D and the gate electrode G in the normal direction N of the substrate 100. In this embodiment, the common electrode COM includes, for example, a plurality of slits SLI. The slit SLI of the common electrode COM overlaps the pixel electrode PE in the normal direction N of the substrate 100. In a preferred embodiment, the common electrode has an opening OP1 to expose the opening OP and a part of the gate insulating layer GI. The opening OP1 of the common electrode COM overlaps the gate electrode G in the normal direction N of the substrate 100. Furthermore, the common electrode COM reduces the coupling capacitance between the common electrode COM and the gate electrode G through the opening OP1.

In this embodiment, by using the first patterned photoresist layer 120 and the second patterned photoresist layer 140 as a mask, the semiconductor layer 130, the semiconductor channel CH, the drain D, the pixel electrode PE, and the gate can be made G can be more accurately set at the position of the process design, and can save the number of photomasks required for the process. In the manufacturing process of the active element substrate 10, the length L of the semiconductor channel CH is controlled by the setting of the auxiliary insulating layer 110 To increase the starting current of the active element T, further reduce the area of the active element T to increase the aperture ratio of the display area AR.

4A-4K are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 5A to 5I are schematic partial top views of a method for manufacturing an active element substrate according to an embodiment of the present invention. It must be noted here that FIGS. 4A to 4G are schematic cross-sectional views taken along the line BB ′ of FIGS. 5A to 5G, respectively; FIG. 4I is a schematic cross-sectional view taken along the line BB ′ of FIG. 5H; and FIG. 5I is taken along the line of FIG. 4K. BB 'is a schematic cross-sectional view, in which the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For convenience of explanation, FIGS. 5A to 5I omit the drawing of the insulating layer, and the position of the opening OP is indicated by a dotted line.

FIGS. 4A to 4K and FIGS. 5A to 5I are partially enlarged schematic diagrams of a method for manufacturing the display area AR of the active device substrate 20, for example. It must be explained here that the embodiments of FIGS. 4A to 4K and FIGS. 5A to 5I follow the component numbers and parts of the embodiments of FIGS. 2A to 2I and 3A to 3M, and the same reference numerals are used to indicate The same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

FIG. 4A and FIG. 5A follow the steps of FIG. 2D and FIG. 3B, for example. Please refer to FIG. 4A and FIG. 5A. A part of the semiconductor material layer SM outside the OP, and another part of the semiconductor material layer SM outside the opening OP is exposed. For example, when viewed in the normal direction N of the substrate 100, the first patterned photoresist layer 210 is, for example, circular. It can be understood that the first patterned photoresist layer 210 can be patterned into different shapes according to the requirements of process design, but the present invention is not limited thereto. In this embodiment, the material of the semiconductor material layer SM includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium germanium zinc oxide, Or other suitable materials, or combinations thereof), or other suitable materials, or containing dopants in the above materials, or combinations thereof.

Referring to FIG. 4B and FIG. 5B, a portion of the semiconductor material layer SM is removed using the first patterned photoresist layer 210 as a mask to form a semiconductor layer 220. The semiconductor layer 220 is electrically connected to the source S through the opening OP.

Please refer to FIGS. 4C and 5C to remove the first patterned photoresist layer 210.

Referring to FIG. 4D and FIG. 5D, a pixel electrode material layer PEM is formed on the opening OP, the semiconductor layer 220 and the auxiliary insulating layer 110, and is electrically connected to the semiconductor layer 220.

Please refer to FIGS. 4E and 5E to form a second patterned photoresist layer 230. In this embodiment, the second patterned photoresist layer 230 is located on the semiconductor layer 220, the pixel electrode material layer PEM, and the auxiliary insulating layer 110. In this embodiment, when viewed along the normal direction N of the substrate 100, the second patterned photoresist layer 230 is horizontally separated from the opening OP by a horizontal distance W, where the horizontal distance W is, for example, greater than 0 μm and less than or equal to 3 μm, The second patterned photoresist layer 230 is not overlapped with the opening OP, but is not limited thereto.

Referring to FIG. 4F and FIG. 5F, the second patterned photoresist layer 230 is used as a mask, and a part of the pixel electrode material layer PEM is removed to form a drain electrode D and a pixel electrode PE1 at the same time, wherein the drain electrode D is In contact with the semiconductor layer 220, the drain electrode D is electrically connected to the pixel electrode PE1. For example, the drain electrode D is directly connected to the pixel electrode PE1 and has the same material.

Referring to FIG. 4G and FIG. 5G, the second patterned photoresist layer 230 is removed to expose the drain electrode D and the pixel electrode PE1. The method for removing the second patterned photoresist layer 230 is, for example, a photoresist peeling process or an ashing process, but the invention is not limited thereto.

Referring to FIG. 4H, a gate insulating layer GI is formed on the opening OP, the semiconductor layer 220, and the auxiliary insulating layer 110. The gate insulating layer GI covers the pixel electrode PE1.

Referring to FIG. 4I and FIG. 5H, a gate G is formed on the opening OP, the semiconductor layer 220, and the gate insulating layer GI. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scanning line SL. At this time, the production of the active element T 'has been completed. The active element T' is a top gate thin film transistor.

Referring to FIG. 4J, an interlayer insulation layer 150 is formed on the gate electrode G. In some embodiments, the interlayer insulating layer 150 is also formed on the scan lines SL.

Referring to FIG. 4K and FIG. 5I, a common electrode COM is formed on the interlayer insulating layer 150. So far, the manufacturing process of the active device substrate 20 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE1 in the normal direction N along the substrate 100. The main difference between the active device substrate 20 and the active device substrate 10 is that the pixel electrode PE1 of the active device substrate 20 is formed by patterning the pixel electrode material layer PEM and covers a part of the semiconductor layer 220.

In this embodiment, the activation current of the active device can be increased by controlling the length L of the semiconductor channel CH by the setting of the auxiliary insulating layer 110 and the horizontal distance W to further reduce the area of the active device to increase the aperture ratio of the display area AR. A preferred active device substrate 20.

6A-6H are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 7A-7H are partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that FIGS. 6A to 6H are schematic cross-sectional views taken along lines CC ′ of FIGS. 7A to 7H, respectively, in which the same or similar reference numerals are used to indicate the same or similar elements, and the same technical content is omitted Instructions. For convenience of explanation, the drawing of the insulating layer is omitted in FIGS. 7A to 7H, and the position of the opening OP is indicated by a dotted line.

FIG. 6A to FIG. 6H and FIG. 7A to FIG. 7H are partially enlarged schematic diagrams of a method for manufacturing the display area AR of the active device substrate 30, for example. It must be explained here that the embodiments of FIGS. 6A to 6H and FIGS. 7A to 7H follow the component numbers and parts of the embodiments of FIGS. 4A to 4K and 5A to 5I, and the same reference numerals are used to indicate them. The same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

Please refer to FIGS. 6A and 7A. In this embodiment, the source electrode S further includes an ohmic contact layer 310, and the semiconductor material layer SM further includes an ohmic contact layer 320. For example, before the first patterned photoresist layer 330 is formed, an ion doping process is performed on the semiconductor material layer SM to form an ohmic contact layer 320 on the surface of the semiconductor material layer SM.

Referring to FIG. 6B and FIG. 7B, using the first patterned photoresist layer 330 as a mask, a part of the semiconductor material layer SM and the ohmic contact layer 320 are removed to form a semiconductor layer 340 and an ohmic contact layer 320 '. The semiconductor layer 340 is electrically connected to the source S through the opening OP. In this embodiment, the material of the semiconductor layer 340 includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium germanium zinc oxide, or Is another suitable material, or a combination thereof, or another suitable material, or contains a dopant in the above materials, or a combination thereof.

Referring to FIGS. 6C and 7C, an ashing process is performed on the first patterned photoresist layer 330 to form a second patterned photoresist layer 350. In this embodiment, the second patterned photoresist layer 350 is located in the opening OP, and a portion of the semiconductor layer 340 and a portion of the ohmic contact layer 320 'that are not located in the opening OP are substantially exposed.

Referring to FIGS. 6D and 7D, a pixel electrode material layer PEM is formed on the semiconductor layer 340, the second patterned photoresist layer 350, and the auxiliary insulating layer 110. A third patterned photoresist layer 360 is formed on the semiconductor layer 340, the pixel electrode material layer PEM, and the auxiliary insulating layer 110, and a first portion PEM1 of the pixel electrode material layer PEM is exposed. The second portion PEM2 of the pixel electrode material layer PEM is located between the third patterned photoresist layer 360 and the second patterned photoresist layer 350. The third part PEM3 of the pixel electrode material layer PEM is located between the first part PEM1 and the second part PEM2. In other words, in the direction N along the normal direction of the substrate 100, the first portion PEM1 of the pixel electrode material layer PEM does not overlap the third patterned photoresist layer 360. In this embodiment, the third patterned photoresist layer 360 has a through hole 370 and overlaps the opening OP in the normal direction N along the substrate 100 to expose a portion of the first pixel electrode material layer PEM PEM1.

Please refer to FIG. 6E and FIG. 7E, using the third patterned photoresist layer 360 as a mask, removing the first part PEM1 of the pixel electrode material layer PEM to expose a part of the second patterned photoresist layer 350 and auxiliary insulation. Part of layer 110.

Referring to FIG. 6F and FIG. 7F, the second patterned photoresist layer 350 and the third patterned photoresist layer 360 are removed to form a pixel electrode PE2. In this embodiment, the second portion PEM2 of the pixel electrode material layer PEM will be removed along with the photoresist stripping process of the second patterned photoresist layer 350 and the third patterned photoresist layer 360. The electrode PE2 is approximately equal to the third portion PEM3 of the pixel electrode material layer PEM. In this embodiment, a part of the pixel electrode PE2 is used as the drain electrode D, and the material of the pixel electrode PE2 is exemplified by a metal or a transparent metal oxide, but not limited thereto. In this embodiment, please refer to FIG. 6E and FIG. 6F at the same time. The width of the through hole 370 is smaller than the width of the opening OP. The boundary of the electrode PE2 is provided at the edge of the opening OP. Next, the auxiliary insulating layer 110 and the pixel electrode PE2 are used as a mask, and the unshielded ohmic contact layer 320 'is removed using, for example, an etching process, leaving the ohmic contact layer 320' '. The semiconductor channel CH is, for example, a portion of the semiconductor layer 340 that covers the sidewall of the opening OP.

Referring to FIGS. 6G and 7G, a gate insulating layer GI is formed on the opening OP, the semiconductor layer 340, and the auxiliary insulating layer 110. The gate insulating layer GI covers the pixel electrode PE2. A gate G is formed on the opening OP, the semiconductor layer 340 and the gate insulating layer GI. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scanning line SL. At this time, the production of the active element T '' has been completed, and the active element T '' is a top gate thin film transistor.

Referring to FIGS. 6H and 7H, an interlayer insulating layer 150 is formed on the gate electrode G. In some embodiments, the interlayer insulating layer 150 is also formed on the scan lines SL. The common electrode COM is formed on the interlayer insulating layer 150. So far, the manufacturing process of the active device substrate 30 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE2 in the normal direction N along the substrate 100.

The main difference between the active device substrate 30 and the active device substrate 20 is that the pixel electrode PE2 of the active device substrate 30 is patterned to remove the first portion PEM1 of the pixel electrode material layer PEM by the third patterned photoresist layer 360, and borrows It is formed by removing the second patterned photoresist layer 350 and the third patterned photoresist layer 360 while removing the second part PEM2 of the pixel electrode material layer PEM, and a part of the pixel electrode PE2 is covered on On the ohmic contact layer 320 "of the semiconductor layer 340.

In this embodiment, by using the first patterned photoresist layer 330, the second patterned photoresist layer 350, and the third patterned photoresist layer 360, the semiconductor layer 340, the semiconductor channel CH, the pixel electrode PE2, and The gate G can be more accurately set at the position of the process design, and can save the number of photomasks required for the process. In the manufacturing process of the active element substrate 30, the semiconductor channel CH is controlled by the setting of the auxiliary insulating layer 110. The length L is used to increase the startup current of the active device, further reduce the area of the active device to increase the aperture ratio of the display area AR, and obtain a better active device substrate 30.

8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and parts of the embodiments of FIGS. 2A to 2M, wherein the same reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

Referring to FIG. 8, a first wiring layer M1 is formed on the peripheral region BR of the substrate 100. In this embodiment, the first wiring layer M1 and the source electrode S can be formed by patterning the same film layer. In other alternative embodiments, the first wiring layer M1 and the source electrode S may be formed by patterning different film layers, but the present invention is not limited thereto.

A second wire layer M2 is formed on the gate insulating layer GI. The second wire layer M2 is located on the peripheral region BR of the substrate 100. In this embodiment, the second wire layer M2 and the gate electrode G may be formed by patterning the same film layer. In other alternative embodiments, the second wire layer M2 and the gate electrode G may be formed by patterning different film layers, but the present invention is not limited thereto.

The conductive structure 400 is formed in the contact window C1 of the gate insulating layer GI. The contact window C1 overlaps the first wire layer M1 and does not overlap the second wire layer M2. The conducting structure 400 is electrically connected to the first wire layer M1 and the second wire layer M2.

In this embodiment, the interlayer insulation layer 150 is formed on the second wire layer M2. The interlayer insulation layer 150 has a junction window C2 and a junction window C3. The junction window C2 overlaps the junction window C1 to expose the first wire. Layer M1, and the contact window C3 exposes the second wire layer M2. The conducting structure 400 is further formed in the junction window C2 and the junction window C3 to electrically connect the first wire layer M1 and the second wire layer M2. The first wire layer M1 and the second wire layer M2 are stacked on each other to form a fan-out line 102, thereby reducing the impedance of the fan-out line 102.

In this embodiment, the conductive structure 400 and the common electrode COM can be formed by patterning the same film layer. In other alternative embodiments, the conductive structure 400 and the common electrode COM may be formed by patterning different film layers, but the present invention is not limited thereto. In addition, the above-mentioned fan-out line 102 is described by taking a double-layer wire structure as an example, but the present invention is not limited thereto. In other embodiments, the fan-out line 102 described above may also be a single-layer wire structure.

In summary, by forming an opening in the auxiliary insulating layer of the active device substrate of the present invention, the semiconductor layer, the gate insulating layer, and the gate can be more accurately set at the position of the process design, and the manufacturing process can be saved. The required number of photomasks, and the length L of the semiconductor channel CH is controlled by the setting of the auxiliary insulating layer 110 to increase the startup current of the active device, further reducing the area of the active device to increase the aperture ratio of the display area AR, and the aperture ratio is better Active component substrate.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 20, 30‧‧‧‧ Active component substrate

100‧‧‧ substrate

102‧‧‧fanout line

104‧‧‧flexible circuit board

110‧‧‧ auxiliary insulation

120, 210, 330‧‧‧‧ the first patterned photoresist layer

130, 130 ’, 220, 340‧‧‧ semiconductor layer

140, 230, 350‧‧‧‧ Second patterned photoresist layer

150‧‧‧ interlayer insulation

310, 320, 320 ’, 320’’‧‧‧ohm contact layer

360‧‧‧ The third patterned photoresist layer

370‧‧‧through hole

400‧‧‧Conduction structure

AA ’, BB’, CC’‧‧‧ line

AR‧‧‧Display Area

BR‧‧‧Peripheral area

C1, C2, C3‧‧‧ contact windows

CH‧‧‧Semiconductor Channel

COM‧‧‧Common electrode

D‧‧‧ Drain

DL‧‧‧Data Line

G‧‧‧Gate

GI‧‧‧Gate insulation

L‧‧‧ length

M1‧‧‧First wire layer

M2‧‧‧Second wire layer

N‧‧‧normal direction

OP, OP1‧‧‧ opening

PE, PE1, PE2 ‧‧‧ pixel electrodes

PEM‧‧‧Pixel electrode material layer

PEM1‧‧‧Part I

PEM2‧‧‧ Part Two

PEM3‧‧‧ Part III

S‧‧‧Source

SL‧‧‧scan line

SLI‧‧‧Slit

SM‧‧‧Semiconductor material layer

T, T ’, T’’‧‧‧ active element

W‧‧‧Horizontal distance

FIG. 1 is a schematic top view of an active device substrate according to an embodiment of the present invention. 2A to 2M are schematic partial cross-sectional views of a method for manufacturing an active element substrate according to an embodiment of the present invention. 3A to 3I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 4A-4K are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 5A to 5I are schematic partial top views of a method for manufacturing an active element substrate according to an embodiment of the present invention. 6A-6H are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 7A-7H are partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

Claims (20)

A method for manufacturing an active element substrate includes: forming a source on a display area of a substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; forming a A semiconductor layer on the auxiliary insulating layer, the semiconductor layer being electrically connected to the source through the opening; forming a gate insulating layer on the opening, the semiconductor layer and the auxiliary insulating layer; and forming a gate on On the opening, the semiconductor layer and the gate insulating layer. The manufacturing method according to item 1 of the scope of patent application, further comprising: performing a conductive process on a portion of the semiconductor layer to define a semiconductor channel, a drain, and a pixel electrode, wherein a portion of the semiconductor channel is substantially The upper side wall surrounding the opening is such that the length of the semiconductor channel is about 0.5 μm to 3 μm, and the pixel electrode is not located in the opening. The manufacturing method according to item 2 of the scope of patent application, wherein the material of the semiconductor layer includes indium gallium zinc oxide, indium zinc tin oxide, or indium gallium tin oxide, and viewed along the normal direction of the substrate, the A part of the drain electrode is located between the semiconductor channel and the pixel electrode. The manufacturing method according to item 2 of the scope of patent application, wherein the step of forming the semiconductor layer on the auxiliary insulating layer includes: forming a semiconductor material layer to cover the opening and an upper surface of the auxiliary insulating layer; forming a first pattern A photoresist layer is formed on the semiconductor material layer and the opening; and a portion of the semiconductor material layer is removed by using the first patterned photoresist layer as a mask to form the semiconductor layer. The manufacturing method according to item 4 of the scope of patent application, wherein before the step of performing the conductorization process on the portion of the semiconductor layer, the method further includes: performing an ashing process on the first patterned photoresist layer. In order to form a second patterned photoresist layer, the second patterned photoresist layer is located in the opening and substantially exposes a part of the semiconductor layer that is not located in the opening. The manufacturing method according to item 5 of the scope of patent application, wherein the step of performing the ashing process includes applying carbon tetrafluoride or oxygen. The manufacturing method according to item 5 of the scope of patent application, wherein the step of performing the conductive process on the portion of the semiconductor layer includes: using the second patterned photoresist layer as a mask, and applying hydrogen to the semiconductor layer. . The manufacturing method according to item 7 of the scope of patent application, wherein after the step of performing the conductive process on the part of the semiconductor layer and before the step of forming the gate insulating layer, the method further includes removing the first Two patterned photoresist layers. The manufacturing method according to item 8 of the scope of patent application, wherein after the step of forming the gate electrode, the method further comprises: forming an interlayer insulating layer on the gate electrode; and forming a common electrode on the interlayer insulating layer and Superimposed on this pixel electrode. The manufacturing method according to item 1 of the patent application scope, wherein after the step of forming the semiconductor layer, the method further comprises: forming a pixel electrode material layer in the opening, the semiconductor layer and the auxiliary insulating layer and Electrically connected to the semiconductor layer; forming a second patterned photoresist layer on the semiconductor layer, the pixel electrode material layer, and the auxiliary insulating layer, wherein the second patterned photoresist layer is at a level from the opening Distance, the horizontal distance is greater than 0 micrometers and less than or equal to 3 micrometers so that the second patterned photoresist layer does not overlap the opening; using the second patterned photoresist layer as a mask, removing part of the pixel electrode material Layer to form a pixel electrode; and removing the second patterned photoresist layer. The manufacturing method according to item 10 of the application, wherein the material of the semiconductor layer includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, or oxide semiconductor materials. The manufacturing method according to item 11 of the scope of patent application, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and forming a common electrode on the interlayer insulating layer and Superimposed on this pixel electrode. The manufacturing method according to item 1 of the scope of patent application, wherein the step of forming the semiconductor layer on the auxiliary insulating layer includes: forming a semiconductor material layer in the opening and on the auxiliary insulating layer; forming a first patterning A photoresist layer on the upper surface of the semiconductor material layer and in the opening; and using the first patterned photoresist layer as a mask, removing a part of the semiconductor material layer to form the semiconductor layer. The manufacturing method according to item 13 of the patent application scope, wherein after the step of forming the semiconductor layer on the auxiliary insulating layer and before the step of forming the gate insulating layer, the method further includes: the first pattern Performing an ashing process on the photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer is located in the opening and substantially exposes a part of the semiconductor layer not located in the opening; forming A pixel electrode material layer is formed on the semiconductor layer, the second patterned photoresist layer, and the auxiliary insulation layer; a third patterned photoresist layer is formed on the semiconductor layer, the pixel electrode material layer, and the auxiliary insulation Layer, wherein the third patterned photoresist layer has a through hole overlapping the opening, and the width of the through hole is smaller than the width of the opening; using the third patterned photoresist layer as a mask, the pixel electrode is removed A first portion of one of the material layers; and removing the second patterned photoresist layer, the third patterned photoresist layer, and a second portion of the pixel electrode material layer to form a pixel electrode. The manufacturing method according to item 14 of the patent application, wherein before the step of forming the first patterned photoresist layer, the method further includes performing an ion doping process on the semiconductor material layer to place the semiconductor material layer on the semiconductor material layer. An ohmic contact layer is formed on the surface. The manufacturing method according to item 15 of the scope of patent application, wherein after removing the second patterned photoresist layer, the third patterned photoresist layer, and the second portion of the pixel electrode material layer, the method The method further includes removing a portion of the ohmic contact layer that is not shielded by the pixel electrode to form a semiconductor channel. The manufacturing method according to item 16 of the scope of patent application, wherein the material of the semiconductor layer includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, or oxide semiconductor materials. The manufacturing method according to item 17 of the scope of patent application, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and forming a common electrode on the interlayer insulating layer and Superimposed on this pixel electrode. The manufacturing method according to item 1 of the patent application scope further comprises: forming a first wiring layer on a peripheral area of the substrate, wherein the peripheral area is located on at least one side of the display area, wherein the first wiring layer and the The source electrode is formed by patterning the same film layer; and a second wire layer is formed on the gate insulating layer, the second wire layer is located on the peripheral region of the substrate, wherein the second wire layer and the gate The electrodes are patterned from the same film layer; and a conducting structure is formed, the conducting structure is electrically connected to the first wire layer and the second wire layer through a contact window of the gate insulation layer, and the contact windows do not overlap On the second wire layer. The manufacturing method according to item 19 of the scope of patent application, wherein after the step of forming the gate, the method further comprises: forming an interlayer insulating layer on the gate; and forming a common electrode on the interlayer insulating layer and Overlapping on the pixel electrode, the conductive structure and the common electrode are patterned from the same film layer.