TWI655477B - Active element substrate manufacturing method - Google Patents
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- TWI655477B TWI655477B TW107113188A TW107113188A TWI655477B TW I655477 B TWI655477 B TW I655477B TW 107113188 A TW107113188 A TW 107113188A TW 107113188 A TW107113188 A TW 107113188A TW I655477 B TWI655477 B TW I655477B
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- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 126
- 238000000034 method Methods 0.000 claims abstract description 69
- 239000010410 layer Substances 0.000 claims description 332
- 229920002120 photoresistant polymer Polymers 0.000 claims description 83
- 239000000463 material Substances 0.000 claims description 53
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- 239000007772 electrode material Substances 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 19
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- 238000000059 patterning Methods 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 238000004380 ashing Methods 0.000 claims description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 3
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 description 9
- 101100059990 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CHO2 gene Proteins 0.000 description 7
- 101100297830 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) OPI3 gene Proteins 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
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- RQIPKMUHKBASFK-UHFFFAOYSA-N [O-2].[Zn+2].[Ge+2].[In+3] Chemical compound [O-2].[Zn+2].[Ge+2].[In+3] RQIPKMUHKBASFK-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
一種主動元件基板的製造方法,包括:形成源極於基板的顯示區上;形成輔助絕緣層於源極上;於輔助絕緣層中形成開口以暴露出源極;形成半導體層於輔助絕緣層上,半導體層藉由開口與源極電性連接;形成閘極絕緣層於開口、半導體層以及輔助絕緣層上;以及形成閘極於開口、半導體層以及閘極絕緣層上。A method for manufacturing an active element substrate includes: forming a source on a display area of the substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; forming a semiconductor layer on the auxiliary insulating layer, The semiconductor layer is electrically connected to the source through the opening; a gate insulating layer is formed on the opening, the semiconductor layer, and the auxiliary insulating layer; and a gate is formed on the opening, the semiconductor layer, and the gate insulating layer.
Description
本發明是有關於一種主動元件基板的製造方法,且特別是有關於形成半導體層於輔助絕緣層上的主動元件基板的製造方法。The present invention relates to a method for manufacturing an active element substrate, and more particularly, to a method for manufacturing an active element substrate having a semiconductor layer formed on an auxiliary insulating layer.
目前,垂直式薄膜電晶體(vertical thin film transistor,vertical TFT)逐漸被許多公司所重視。垂直式薄膜電晶體具有較高的載子遷移率,可應用於具有較高頻率及較低工作偏壓的裝置中。At present, vertical thin film transistors (vertical thin film transistors, vertical TFTs) are gradually valued by many companies. Vertical thin film transistors have higher carrier mobility and can be used in devices with higher frequencies and lower operating bias.
然而,在垂直式薄膜電晶體的製造過程中,主動層需同時覆蓋多個膜層,因此需要進行多道鍍膜製程及圖案化製程,進而需要使用多個光罩。如此一來,不但製程的複雜度高,製造成本也難以減少。另外,多道鍍膜製程所形成的多個膜層的邊緣會呈現階梯狀,使得主動層在覆蓋階梯狀結構時,主動層易因邊緣不平滑而使成膜品質不良,進而影響垂直式薄膜電晶體內的電子傳遞。因此,目前亟需一種能解決前述問題的方法。However, in the manufacturing process of the vertical thin-film transistor, the active layer needs to cover multiple film layers at the same time. Therefore, multiple coating processes and patterning processes are required, and multiple photomasks are required. In this way, not only the complexity of the process is high, but the manufacturing cost is also difficult to reduce. In addition, the edges of the multiple film layers formed by the multi-layer coating process will appear stepped, so that when the active layer covers the stepped structure, the active layer is prone to poor film formation due to the uneven edges, which affects the vertical thin film electricity. Electron transfer within the crystal. Therefore, there is an urgent need for a method that can solve the aforementioned problems.
本發明之一實施例提供一種主動元件基板的製造方法,能提升主動元件的啟動電流。An embodiment of the present invention provides a method for manufacturing an active device substrate, which can increase the startup current of the active device.
本發明之一實施例的一種主動元件基板的製造方法,包括:形成源極於基板的顯示區上;形成輔助絕緣層於源極上;於輔助絕緣層中形成開口以暴露出源極;形成半導體層於輔助絕緣層上,半導體層藉由開口與源極電性連接;形成閘極絕緣層於開口、半導體層以及輔助絕緣層上;以及形成閘極於開口、半導體層以及閘極絕緣層上。A method for manufacturing an active device substrate according to an embodiment of the present invention includes: forming a source on a display area of the substrate; forming an auxiliary insulating layer on the source; forming an opening in the auxiliary insulating layer to expose the source; forming a semiconductor Layer on the auxiliary insulating layer, the semiconductor layer is electrically connected to the source through the opening; forming a gate insulating layer on the opening, the semiconductor layer and the auxiliary insulating layer; and forming a gate on the opening, the semiconductor layer and the gate insulating layer .
本發明之目的之一為降低主動元件基板的製程難度。One of the objectives of the present invention is to reduce the difficulty of manufacturing the active device substrate.
本發明之目的之一為提升主動元件的啟動電流。One of the objects of the present invention is to increase the starting current of an active device.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
圖1是依照本發明的一實施例的一種主動元件基板的上視示意圖。圖2A~圖2M是依照本發明的一實施例的一種主動元件基板的製造方法的局部剖面示意圖。圖3A~圖3I是依照本發明的一實施例的一種主動元件基板的製造方法的局部上視示意圖。在此必須說明的是,圖2C~圖2I是分別沿圖3A~圖3G之線AA’的剖面示意圖;圖2K是沿圖3H之線AA’的剖面示意圖;圖2M是沿圖3I之線AA’的剖面示意圖,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。為方便說明,圖3A~圖3I省略絕緣層的繪示,並以虛線表示開口OP的位置。FIG. 1 is a schematic top view of an active device substrate according to an embodiment of the present invention. 2A to 2M are schematic partial cross-sectional views of a method for manufacturing an active element substrate according to an embodiment of the present invention. 3A to 3I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that FIGS. 2C to 2I are schematic cross-sectional views taken along the line AA ′ of FIGS. 3A to 3G, respectively; FIG. 2K is a schematic cross-sectional view taken along the line AA ′ of FIG. 3H; AA ′ is a schematic cross-sectional view, in which the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For convenience of explanation, the illustration of the insulating layer is omitted in FIGS. 3A to 3I, and the position of the opening OP is indicated by a dotted line.
請參考圖1,主動元件基板10的基板100包括顯示區AR以及周邊區BR。周邊區BR位於顯示區AR的一側,或是周邊區BR環繞顯示區AR。換言之,周邊區BR可位於顯示區AR的其中一側邊,且可依不同需求而調整。舉例而言,應用於矩形顯示區時,周邊區BR係環繞於顯示區AR或可位於顯示區AR的其中一側邊、兩側邊或三側邊;應用於非矩形顯示區或圓形顯示區時,周邊區BR可鄰近於顯示區AR,例如為鄰近於顯示區AR的部分周邊或全部周邊。在本實施例中,主動元件基板10還包括扇出線102及軟性電路板104。扇出線102及軟性電路板104位於周邊區BR上,且扇出線102自周邊區BR延伸進顯示區AR。舉例來說,扇出線102電性連接周邊區BR上的軟性電路板104以及顯示區AR上的主動元件。Referring to FIG. 1, the substrate 100 of the active device substrate 10 includes a display area AR and a peripheral area BR. The peripheral area BR is located on one side of the display area AR, or the peripheral area BR surrounds the display area AR. In other words, the peripheral area BR can be located on one side of the display area AR, and can be adjusted according to different needs. For example, when applied to a rectangular display area, the surrounding area BR is surrounded by the display area AR or may be located on one side, two sides, or three sides of the display area AR; applied to a non-rectangular display area or a circular display In the area, the peripheral area BR may be adjacent to the display area AR, for example, it may be a portion or all of the periphery of the display area AR. In this embodiment, the active device substrate 10 further includes a fan-out line 102 and a flexible circuit board 104. The fan-out line 102 and the flexible circuit board 104 are located on the peripheral area BR, and the fan-out line 102 extends from the peripheral area BR into the display area AR. For example, the fan-out line 102 is electrically connected to the flexible circuit board 104 on the peripheral area BR and the active component on the display area AR.
圖2A~圖2I以及圖3A~圖3M例如為主動元件基板10之顯示區AR的製造方法之局部放大示意圖。FIGS. 2A to 2I and FIGS. 3A to 3M are, for example, partially enlarged schematic diagrams of a method for manufacturing the display area AR of the active device substrate 10.
請參考圖2A及圖3A,形成源極S與資料線DL於基板100的顯示區AR上,資料線DL與源極S電性連接。Please refer to FIG. 2A and FIG. 3A, a source S and a data line DL are formed on the display area AR of the substrate 100, and the data line DL is electrically connected to the source S.
接著請參考圖2B,形成輔助絕緣層110於源極S上,在本實施例中,輔助絕緣層110的材料可包括矽氧烷、聚醯亞胺、氮化矽、其它合適的材料、或上述至少二種材料的堆疊層。在一些實施例中,輔助絕緣層110還形成於資料線DL上。Referring next to FIG. 2B, an auxiliary insulating layer 110 is formed on the source S. In this embodiment, the material of the auxiliary insulating layer 110 may include siloxane, polyimide, silicon nitride, other suitable materials, or A stacked layer of the at least two materials. In some embodiments, the auxiliary insulating layer 110 is further formed on the data line DL.
請同時參考圖2C與圖3A,在輔助絕緣層110中形成開口OP,以暴露出源極S。Referring to FIG. 2C and FIG. 3A at the same time, an opening OP is formed in the auxiliary insulating layer 110 to expose the source S.
請參考圖2D與圖3B,形成半導體材料層SM於輔助絕緣層110的上表面。半導體材料層SM覆蓋開口OP。半導體材料層SM之材料例如包括銦鎵鋅氧化物、銦鋅錫氧化物或銦鎵錫氧化物。Referring to FIG. 2D and FIG. 3B, a semiconductor material layer SM is formed on the upper surface of the auxiliary insulating layer 110. The semiconductor material layer SM covers the opening OP. The material of the semiconductor material layer SM includes, for example, indium gallium zinc oxide, indium zinc tin oxide, or indium gallium tin oxide.
請參考圖2E與圖3C,形成第一圖案化光阻層120於半導體材料層SM以及開口OP上。形成第一圖案化光阻層120的方法例如包括塗佈光阻材料於半導體材料層SM上以及開口OP中,接著再對光阻材料進行微影製程。Referring to FIG. 2E and FIG. 3C, a first patterned photoresist layer 120 is formed on the semiconductor material layer SM and the opening OP. The method for forming the first patterned photoresist layer 120 includes, for example, coating a photoresist material on the semiconductor material layer SM and the opening OP, and then performing a photolithography process on the photoresist material.
請參考圖2F與圖3D,以第一圖案化光阻層120為遮罩,移除部分的半導體材料層SM,以形成半導體層130,半導體層130藉由開口OP與源極S電性連接,半導體層130及第一圖案化光阻層120暴露出輔助絕緣層110的部分上表面。在本實施例中,半導體層130之材料例如包括銦鎵鋅氧化物、銦鋅錫氧化物或銦鎵錫氧化物。Please refer to FIG. 2F and FIG. 3D. With the first patterned photoresist layer 120 as a mask, a part of the semiconductor material layer SM is removed to form a semiconductor layer 130. The semiconductor layer 130 is electrically connected to the source S through the opening OP. The semiconductor layer 130 and the first patterned photoresist layer 120 expose a part of the upper surface of the auxiliary insulating layer 110. In this embodiment, the material of the semiconductor layer 130 includes, for example, indium gallium zinc oxide, indium zinc tin oxide, or indium gallium tin oxide.
請同時參考圖2G及圖3E,形成第二圖案化光阻層140。舉例而言,對第一圖案化光阻層120進行灰化製程,以移除非位於開口OP上之部份的第一圖案化光阻層120而形成第二圖案化光阻層140。在本實施例中,第二圖案化光阻層140位於開口OP內,且實質上暴露出不位於開口OP內之部分的半導體層130。其中,進行灰化製程的步驟例如包括施加四氟化碳或氧氣,但本發明不以此為限。Please refer to FIG. 2G and FIG. 3E together to form a second patterned photoresist layer 140. For example, an ashing process is performed on the first patterned photoresist layer 120 to remove a portion of the first patterned photoresist layer 120 that is not located on the opening OP to form a second patterned photoresist layer 140. In this embodiment, the second patterned photoresist layer 140 is located in the opening OP, and a portion of the semiconductor layer 130 that is not located in the opening OP is substantially exposed. The steps of performing the ashing process include, for example, applying carbon tetrafluoride or oxygen, but the present invention is not limited thereto.
請同時參考圖2H及圖3F,對半導體層130的一部分進行導體化製程,以定義出半導體通道CH、汲極D以及畫素電極PE,其中半導體通道CH屬於半導體層130’的一部分。汲極D以及畫素電極PE的導電率高於半導體通道CH的導電率。汲極D連接半導體通道CH,且畫素電極PE與汲極D電性連接,畫素電極PE例如接觸於汲極D而不接觸於半導體通道CH。Referring to FIG. 2H and FIG. 3F at the same time, a part of the semiconductor layer 130 is subjected to a conductive process to define a semiconductor channel CH, a drain electrode D, and a pixel electrode PE. The semiconductor channel CH is part of the semiconductor layer 130 '. The conductivity of the drain electrode D and the pixel electrode PE is higher than that of the semiconductor channel CH. The drain electrode D is connected to the semiconductor channel CH, and the pixel electrode PE is electrically connected to the drain electrode D. For example, the pixel electrode PE contacts the drain electrode D and does not contact the semiconductor channel CH.
進行導體化製程的步驟例如包括以第二圖案化光阻層140為遮罩,對半導體層130施加氫氣,但本發明不以此為限。在本實施例中,藉由以第二圖案化光阻層140為遮罩,可以在進行導體化製程時精準的控制半導體通道CH的邊緣位置。在本實施例中,部份的半導體通道CH實質上環繞開口OP的側壁。在本實施例中,半導體通道CH的長度L約為開口OP的側壁的長度,半導體通道CH的長度L指的是半導體通道CH的有效長度。藉由輔助絕緣層110的設置,可以準確的控制長度L。在本實施例中,半導體通道CH的長度L約為0.5微米至4微米,較佳設置為1微米至2微米。在本實施例中,畫素電極PE不位於開口OP內,且沿基板100的法線方向N上觀察,一部份的汲極D位於半導體通道CH與畫素電極PE之間,汲極D舉例係呈環狀且位於輔助絕緣層110之上表面。The step of conducting the conductive process includes, for example, applying the second patterned photoresist layer 140 as a mask and applying hydrogen to the semiconductor layer 130, but the present invention is not limited thereto. In this embodiment, by using the second patterned photoresist layer 140 as a mask, the edge position of the semiconductor channel CH can be accurately controlled during the conducting process. In this embodiment, a part of the semiconductor channel CH substantially surrounds the sidewall of the opening OP. In this embodiment, the length L of the semiconductor channel CH is approximately the length of the sidewall of the opening OP, and the length L of the semiconductor channel CH refers to the effective length of the semiconductor channel CH. By setting the auxiliary insulating layer 110, the length L can be accurately controlled. In this embodiment, the length L of the semiconductor channel CH is about 0.5 μm to 4 μm, and preferably set to 1 μm to 2 μm. In this embodiment, the pixel electrode PE is not located in the opening OP and is viewed along the normal direction N of the substrate 100. A part of the drain electrode D is located between the semiconductor channel CH and the pixel electrode PE. The drain electrode D For example, it is ring-shaped and located on the upper surface of the auxiliary insulating layer 110.
請同時參考圖2I及圖3G,移除第二圖案化光阻層140,以暴露出位於開口OP內的半導體層130’。移除第二圖案化光阻層140的方法例如為進行光阻剝離製程或灰化製程,但本發明不以此為限。若沿基板100的法線方向N上觀察,開口OP內的半導體層130’之圖案舉例係為圓形或橢圓形,但本發明不以此為限。Referring to FIG. 2I and FIG. 3G at the same time, the second patterned photoresist layer 140 is removed to expose the semiconductor layer 130 'located in the opening OP. The method of removing the second patterned photoresist layer 140 is, for example, a photoresist peeling process or an ashing process, but the invention is not limited thereto. If viewed in the normal direction N of the substrate 100, the pattern of the semiconductor layer 130 'in the opening OP is circular or oval, but the invention is not limited thereto.
請參考圖2J,形成閘極絕緣層GI於開口OP、半導體層130’、汲極D、畫素電極PE以及輔助絕緣層110上。閘極絕緣層GI覆蓋汲極D以及畫素電極PE。Referring to FIG. 2J, a gate insulating layer GI is formed on the opening OP, the semiconductor layer 130 ', the drain electrode D, the pixel electrode PE, and the auxiliary insulating layer 110. The gate insulating layer GI covers the drain electrode D and the pixel electrode PE.
請同時參考圖2K及圖3H,形成閘極G於開口OP、半導體層130’以及閘極絕緣層GI上。在本實施例中,閘極G在沿基板100的法線方向N上分別重疊於汲極D與源極S。在一些實施例中,閘極G與掃描線SL是於同一道圖案化製程中所形成。閘極G與掃描線SL電性連接,此時已完成主動元件T之製作,主動元件T係為頂部閘極型薄膜電晶體。Please refer to FIG. 2K and FIG. 3H together to form a gate G on the opening OP, the semiconductor layer 130 ', and the gate insulating layer GI. In this embodiment, the gate G overlaps the drain D and the source S in the normal direction N of the substrate 100, respectively. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scanning line SL. At this time, the production of the active element T has been completed. The active element T is a top gate thin film transistor.
請參考圖2L,形成層間絕緣層150於閘極G上。在一些實施例中,絕緣層150還形成於掃描線SL上。Referring to FIG. 2L, an interlayer insulating layer 150 is formed on the gate G. In some embodiments, the insulating layer 150 is further formed on the scan line SL.
請參考圖2M以及圖3I,形成共用電極COM於層間絕緣層150上,至此,已大致上完成主動元件基板10的製作。在本實施例中,共用電極COM在沿基板100的法線方向N上,重疊於畫素電極PE及部份的汲極D與閘極 G。在本實施例中,共用電極COM例如包括多個狹縫SLI。共用電極COM的狹縫SLI在沿基板100的法線方向N上重疊於畫素電極PE。在較佳的實施例中,共用電極具有開口OP1以暴露出開口OP以及部份的閘極絕緣層GI。共用電極COM的開口OP1在沿基板100的法線方向N上重疊於閘極G。更進一步地說,共用電極COM藉由開口OP1以降低共用電極COM與閘極G之間的耦合電容。Please refer to FIG. 2M and FIG. 3I, a common electrode COM is formed on the interlayer insulating layer 150. So far, the fabrication of the active device substrate 10 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE and a part of the drain electrode D and the gate electrode G in the normal direction N of the substrate 100. In this embodiment, the common electrode COM includes, for example, a plurality of slits SLI. The slit SLI of the common electrode COM overlaps the pixel electrode PE in the normal direction N of the substrate 100. In a preferred embodiment, the common electrode has an opening OP1 to expose the opening OP and a part of the gate insulating layer GI. The opening OP1 of the common electrode COM overlaps the gate electrode G in the normal direction N of the substrate 100. Furthermore, the common electrode COM reduces the coupling capacitance between the common electrode COM and the gate electrode G through the opening OP1.
在本實施例中,藉由第一圖案化光阻層120及第二圖案化光阻層140為遮罩,可使半導體層130、半導體通道CH、汲極D、畫素電極PE以及閘極G能更精準的設置於製程設計的位置上,且能節省製程所需的光罩數量,並在主動元件基板10的製造過程中,藉由輔助絕緣層110的設置控制半導體通道CH的長度L來提升主動元件T的啟動電流,進一步縮小主動元件T的面積來提升顯示區AR的開口率。In this embodiment, by using the first patterned photoresist layer 120 and the second patterned photoresist layer 140 as a mask, the semiconductor layer 130, the semiconductor channel CH, the drain D, the pixel electrode PE, and the gate can be made G can be more accurately set at the position of the process design, and can save the number of photomasks required for the process. In the manufacturing process of the active element substrate 10, the length L of the semiconductor channel CH is controlled by the setting of the auxiliary insulating layer 110 To increase the starting current of the active element T, further reduce the area of the active element T to increase the aperture ratio of the display area AR.
圖4A~圖4K是依照本發明的一實施例的一種主動元件基板的製造方法的局部剖面示意圖。圖5A~圖5I是依照本發明的一實施例的一種主動元件基板的製造方法的局部上視示意圖。在此必須說明的是,圖4A~圖4G是分別沿圖5A~圖5G之線BB’的剖面示意圖;圖4I是沿圖5H之線BB’的剖面示意圖;圖5I是沿圖4K之線BB’的剖面示意圖,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。為方便說明,圖5A~圖5I省略絕緣層的繪示,並以虛線表示開口OP的位置。4A-4K are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 5A to 5I are schematic partial top views of a method for manufacturing an active element substrate according to an embodiment of the present invention. It must be noted here that FIGS. 4A to 4G are schematic cross-sectional views taken along the line BB ′ of FIGS. 5A to 5G, respectively; FIG. 4I is a schematic cross-sectional view taken along the line BB ′ of FIG. 5H; and FIG. 5I is taken along the line of FIG. 4K. BB 'is a schematic cross-sectional view, in which the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical content is omitted. For convenience of explanation, FIGS. 5A to 5I omit the drawing of the insulating layer, and the position of the opening OP is indicated by a dotted line.
圖4A~圖4K以及圖5A~圖5I例如為主動元件基板20之顯示區AR的製造方法之局部放大示意圖。在此必須說明的是,圖4A~圖4K以及圖5A~圖5I的實施例沿用圖2A~圖2I以及圖3A~圖3M的實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。FIGS. 4A to 4K and FIGS. 5A to 5I are partially enlarged schematic diagrams of a method for manufacturing the display area AR of the active device substrate 20, for example. It must be explained here that the embodiments of FIGS. 4A to 4K and FIGS. 5A to 5I follow the component numbers and parts of the embodiments of FIGS. 2A to 2I and 3A to 3M, and the same reference numerals are used to indicate The same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.
圖4A與圖5A例如接續圖2D與圖3B的步驟,請參考圖4A及圖5A,在本實施例中,第一圖案化光阻層210位於輔助絕緣層110的開口OP內,且覆蓋開口OP外的半導體材料層SM的一部份,並且暴露出開口OP外的半導體材料層SM的另一部份。舉例來說,在沿基板100的法線方向N上觀察,第一圖案化光阻層210例如是圓形。可以理解的是,第一圖案化光阻層210可以依據製程設計的需求而圖案化成不同的形狀,然而本發明不以此為限。在本實施例中,半導體材料層SM的材料例如包括非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如:銦鋅氧化物、銦鍺鋅氧化物、或是其它合適的材料、或上述之組合)、或其它合適的材料、或含有摻雜物(dopant)於上述材料中、或上述之組合。FIG. 4A and FIG. 5A follow the steps of FIG. 2D and FIG. 3B, for example. Please refer to FIG. 4A and FIG. 5A. A part of the semiconductor material layer SM outside the OP, and another part of the semiconductor material layer SM outside the opening OP is exposed. For example, when viewed in the normal direction N of the substrate 100, the first patterned photoresist layer 210 is, for example, circular. It can be understood that the first patterned photoresist layer 210 can be patterned into different shapes according to the requirements of process design, but the present invention is not limited thereto. In this embodiment, the material of the semiconductor material layer SM includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium germanium zinc oxide, Or other suitable materials, or combinations thereof), or other suitable materials, or containing dopants in the above materials, or combinations thereof.
請參考圖4B與圖5B,以第一圖案化光阻層210為遮罩,移除部分的半導體材料層SM,以形成半導體層220。半導體層220藉由開口OP與源極S電性連接。Referring to FIG. 4B and FIG. 5B, a portion of the semiconductor material layer SM is removed using the first patterned photoresist layer 210 as a mask to form a semiconductor layer 220. The semiconductor layer 220 is electrically connected to the source S through the opening OP.
請參考圖4C及圖5C,移除第一圖案化光阻層210。Please refer to FIGS. 4C and 5C to remove the first patterned photoresist layer 210.
請參考圖4D及圖5D,形成畫素電極材料層PEM於開口OP、半導體層220及輔助絕緣層110上,並與半導體層220電性連接。Referring to FIG. 4D and FIG. 5D, a pixel electrode material layer PEM is formed on the opening OP, the semiconductor layer 220 and the auxiliary insulating layer 110, and is electrically connected to the semiconductor layer 220.
請參考圖4E及圖5E,形成第二圖案化光阻層230。在本實施例中,第二圖案化光阻層230位於半導體層220、畫素電極材料層PEM及輔助絕緣層110上。在本實施例中,在沿基板100的法線方向N上觀察,第二圖案化光阻層230與開口OP相距水平距離W,其中水平距離W例如是大於0微米且小於或等於3微米,使得第二圖案化光阻層230不重疊於開口OP,但不以此為限。Please refer to FIGS. 4E and 5E to form a second patterned photoresist layer 230. In this embodiment, the second patterned photoresist layer 230 is located on the semiconductor layer 220, the pixel electrode material layer PEM, and the auxiliary insulating layer 110. In this embodiment, when viewed along the normal direction N of the substrate 100, the second patterned photoresist layer 230 is horizontally separated from the opening OP by a horizontal distance W, where the horizontal distance W is, for example, greater than 0 μm and less than or equal to 3 μm, The second patterned photoresist layer 230 is not overlapped with the opening OP, but is not limited thereto.
請參考圖4F及圖5F,以第二圖案化光阻層230為遮罩,移除部份的畫素電極材料層PEM,以同時形成汲極D以及畫素電極PE1,其中汲極D係與半導體層220接觸,汲極D與畫素電極PE1電性連接,汲極D舉例係與畫素電極PE1直接連接且具有相同的材料。Referring to FIG. 4F and FIG. 5F, the second patterned photoresist layer 230 is used as a mask, and a part of the pixel electrode material layer PEM is removed to form a drain electrode D and a pixel electrode PE1 at the same time, wherein the drain electrode D is In contact with the semiconductor layer 220, the drain electrode D is electrically connected to the pixel electrode PE1. For example, the drain electrode D is directly connected to the pixel electrode PE1 and has the same material.
請參考圖4G及圖5G,移除第二圖案化光阻層230,以暴露出汲極D以及畫素電極PE1。移除第二圖案化光阻層230的方法例如為進行光阻剝離製程或灰化製程,但本發明不以此為限。Referring to FIG. 4G and FIG. 5G, the second patterned photoresist layer 230 is removed to expose the drain electrode D and the pixel electrode PE1. The method for removing the second patterned photoresist layer 230 is, for example, a photoresist peeling process or an ashing process, but the invention is not limited thereto.
請參考圖4H,形成閘極絕緣層GI於開口OP、半導體層220以及輔助絕緣層110上。閘極絕緣層GI覆蓋畫素電極PE1。Referring to FIG. 4H, a gate insulating layer GI is formed on the opening OP, the semiconductor layer 220, and the auxiliary insulating layer 110. The gate insulating layer GI covers the pixel electrode PE1.
請參考圖4I及圖5H,形成閘極G於開口OP、半導體層220以及閘極絕緣層GI上。在一些實施例中,閘極G與掃描線SL是於同一道圖案化製程中所形成。閘極G與掃描線SL電性連接,此時已完成主動元件T’之製作,主動元件T’係為頂部閘極型薄膜電晶體。Referring to FIG. 4I and FIG. 5H, a gate G is formed on the opening OP, the semiconductor layer 220, and the gate insulating layer GI. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scanning line SL. At this time, the production of the active element T 'has been completed. The active element T' is a top gate thin film transistor.
請參考圖4J,形成層間絕緣層150於閘極G上。在一些實施例中,層間絕緣層150還形成於掃描線SL上。Referring to FIG. 4J, an interlayer insulation layer 150 is formed on the gate electrode G. In some embodiments, the interlayer insulating layer 150 is also formed on the scan lines SL.
請參考圖4K及圖5I,形成共用電極COM於層間絕緣層150上,至此,已大致上完成主動元件基板20的製造過程。在本實施例中,共用電極COM在沿基板100的法線方向N上,重疊於畫素電極PE1。主動元件基板20與主動元件基板10的主要差別在於主動元件基板20的畫素電極PE1是藉由圖案化畫素電極材料層PEM而形成,且覆蓋於部份的半導體層220上。Referring to FIG. 4K and FIG. 5I, a common electrode COM is formed on the interlayer insulating layer 150. So far, the manufacturing process of the active device substrate 20 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE1 in the normal direction N along the substrate 100. The main difference between the active device substrate 20 and the active device substrate 10 is that the pixel electrode PE1 of the active device substrate 20 is formed by patterning the pixel electrode material layer PEM and covers a part of the semiconductor layer 220.
在本實施例中,可藉由輔助絕緣層110的設置及水平距離W控制半導體通道CH的長度L來提升主動元件的啟動電流,進一步縮小主動元件面積來提升顯示區AR的開口率,而獲得較佳的主動元件基板20。In this embodiment, the activation current of the active device can be increased by controlling the length L of the semiconductor channel CH by the setting of the auxiliary insulating layer 110 and the horizontal distance W to further reduce the area of the active device to increase the aperture ratio of the display area AR. A preferred active device substrate 20.
圖6A~圖6H是依照本發明的一實施例的一種主動元件基板的製造方法的局部剖面示意圖。圖7A~圖7H是依照本發明的一實施例的一種主動元件基板的製造方法的局部上視示意圖。在此必須說明的是,圖6A~圖6H是分別沿圖7A~圖7H之線CC’的剖面示意圖,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。為方便說明,圖7A~圖7H省略絕緣層的繪示,並以虛線表示開口OP的位置。6A-6H are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 7A-7H are partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. It must be noted here that FIGS. 6A to 6H are schematic cross-sectional views taken along lines CC ′ of FIGS. 7A to 7H, respectively, in which the same or similar reference numerals are used to indicate the same or similar elements, and the same technical content is omitted Instructions. For convenience of explanation, the drawing of the insulating layer is omitted in FIGS. 7A to 7H, and the position of the opening OP is indicated by a dotted line.
圖6A~圖6H以及圖7A~圖7H例如為主動元件基板30之顯示區AR的製造方法之局部放大示意圖。在此必須說明的是,圖6A~圖6H以及圖7A~圖7H的實施例沿用圖4A~圖4K以及圖5A~圖5I的實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。FIG. 6A to FIG. 6H and FIG. 7A to FIG. 7H are partially enlarged schematic diagrams of a method for manufacturing the display area AR of the active device substrate 30, for example. It must be explained here that the embodiments of FIGS. 6A to 6H and FIGS. 7A to 7H follow the component numbers and parts of the embodiments of FIGS. 4A to 4K and 5A to 5I, and the same reference numerals are used to indicate them. The same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.
請參考圖6A及圖7A,在本實施例中,源極S上還具有歐姆接觸層310,且半導體材料層SM上還具有歐姆接觸層320。舉例而言,在形成第一圖案化光阻層330之前,對半導體材料層SM進行離子摻雜製程,以於半導體材料層SM之表面形成歐姆接觸層320。Please refer to FIGS. 6A and 7A. In this embodiment, the source electrode S further includes an ohmic contact layer 310, and the semiconductor material layer SM further includes an ohmic contact layer 320. For example, before the first patterned photoresist layer 330 is formed, an ion doping process is performed on the semiconductor material layer SM to form an ohmic contact layer 320 on the surface of the semiconductor material layer SM.
請參考圖6B與圖7B,以第一圖案化光阻層330為遮罩,移除部分的半導體材料層SM及歐姆接觸層320,以形成半導體層340以及歐姆接觸層320’。半導體層340藉由開口OP與源極S電性連接。在本實施例中,半導體層340的材料例如包括非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如:銦鋅氧化物、銦鍺鋅氧化物、或是其它合適的材料、或上述之組合)、或其它合適的材料、或含有摻雜物(dopant)於上述材料中、或上述之組合。Referring to FIG. 6B and FIG. 7B, using the first patterned photoresist layer 330 as a mask, a part of the semiconductor material layer SM and the ohmic contact layer 320 are removed to form a semiconductor layer 340 and an ohmic contact layer 320 '. The semiconductor layer 340 is electrically connected to the source S through the opening OP. In this embodiment, the material of the semiconductor layer 340 includes, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium germanium zinc oxide, or Is another suitable material, or a combination thereof, or another suitable material, or contains a dopant in the above materials, or a combination thereof.
請參考圖6C及圖7C,對第一圖案化光阻層330進行灰化製程,以形成第二圖案化光阻層350。在本實施例中,第二圖案化光阻層350位於開口OP內,且實質上暴露出不位於開口OP內之部分的半導體層340以及部份的歐姆接觸層320’。Referring to FIGS. 6C and 7C, an ashing process is performed on the first patterned photoresist layer 330 to form a second patterned photoresist layer 350. In this embodiment, the second patterned photoresist layer 350 is located in the opening OP, and a portion of the semiconductor layer 340 and a portion of the ohmic contact layer 320 'that are not located in the opening OP are substantially exposed.
請參考圖6D及圖7D,形成畫素電極材料層PEM於半導體層340、第二圖案化光阻層350及輔助絕緣層110上。形成第三圖案化光阻層360於半導體層340、畫素電極材料層PEM及輔助絕緣層110上,並暴露出畫素電極材料層PEM的第一部分PEM1。畫素電極材料層PEM的第二部分PEM2位於第三圖案化光阻層360與第二圖案化光阻層350之間。畫素電極材料層PEM的第三部分PEM3位於第一部分PEM1與第二部分PEM2之間。換句話說,在沿基板100的法線方向N上,畫素電極材料層PEM的第一部分PEM1不重疊於第三圖案化光阻層360。在本實施例中,第三圖案化光阻層360具有通孔370,且在沿基板100的法線方向N上重疊於開口OP,以暴露出部份的畫素電極材料層PEM的第一部分PEM1。Referring to FIGS. 6D and 7D, a pixel electrode material layer PEM is formed on the semiconductor layer 340, the second patterned photoresist layer 350, and the auxiliary insulating layer 110. A third patterned photoresist layer 360 is formed on the semiconductor layer 340, the pixel electrode material layer PEM, and the auxiliary insulating layer 110, and a first portion PEM1 of the pixel electrode material layer PEM is exposed. The second portion PEM2 of the pixel electrode material layer PEM is located between the third patterned photoresist layer 360 and the second patterned photoresist layer 350. The third part PEM3 of the pixel electrode material layer PEM is located between the first part PEM1 and the second part PEM2. In other words, in the direction N along the normal direction of the substrate 100, the first portion PEM1 of the pixel electrode material layer PEM does not overlap the third patterned photoresist layer 360. In this embodiment, the third patterned photoresist layer 360 has a through hole 370 and overlaps the opening OP in the normal direction N along the substrate 100 to expose a portion of the first pixel electrode material layer PEM PEM1.
請參考圖6E及圖7E,以第三圖案化光阻層360為遮罩,移除畫素電極材料層PEM的第一部分PEM1以暴露出部分第二圖案化光阻層350之一部分以及輔助絕緣層110之一部分。Please refer to FIG. 6E and FIG. 7E, using the third patterned photoresist layer 360 as a mask, removing the first part PEM1 of the pixel electrode material layer PEM to expose a part of the second patterned photoresist layer 350 and auxiliary insulation. Part of layer 110.
請參考圖6F及圖7F,移除第二圖案化光阻層350、第三圖案化光阻層360,以形成畫素電極PE2。在本實施例中,畫素電極材料層PEM的第二部分PEM2會隨著第二圖案化光阻層350、第三圖案化光阻層360的光阻剝離製程被一併移除,畫素電極PE2約等於畫素電極材料層PEM的第三部分PEM3。在本實施例中,畫素電極PE2之一部分係作為汲極D,畫素電極PE2之材料舉例係為金屬或透明金屬氧化物,但不以此為限。在本實施例中,請同時參考圖6E及圖6F,通孔370的寬度小於開口OP之寬度,以利於在第二圖案化光阻層350的移除製程中,能夠更精準的將畫素電極PE2的邊界設置於開口OP的邊緣。接著,利用輔助絕緣層110及畫素電極PE2作為遮罩,並利用例如蝕刻製程移除未被遮蔽的歐姆接觸層320’,留下歐姆接觸層320’’。半導體通道CH例如為半導體層340覆蓋開口OP側壁的部分。Referring to FIG. 6F and FIG. 7F, the second patterned photoresist layer 350 and the third patterned photoresist layer 360 are removed to form a pixel electrode PE2. In this embodiment, the second portion PEM2 of the pixel electrode material layer PEM will be removed along with the photoresist stripping process of the second patterned photoresist layer 350 and the third patterned photoresist layer 360. The electrode PE2 is approximately equal to the third portion PEM3 of the pixel electrode material layer PEM. In this embodiment, a part of the pixel electrode PE2 is used as the drain electrode D, and the material of the pixel electrode PE2 is exemplified by a metal or a transparent metal oxide, but not limited thereto. In this embodiment, please refer to FIG. 6E and FIG. 6F at the same time. The width of the through hole 370 is smaller than the width of the opening OP. The boundary of the electrode PE2 is provided at the edge of the opening OP. Next, the auxiliary insulating layer 110 and the pixel electrode PE2 are used as a mask, and the unshielded ohmic contact layer 320 'is removed using, for example, an etching process, leaving the ohmic contact layer 320' '. The semiconductor channel CH is, for example, a portion of the semiconductor layer 340 that covers the sidewall of the opening OP.
請參考圖6G及圖7G,形成閘極絕緣層GI於開口OP、半導體層340以及輔助絕緣層110上。閘極絕緣層GI覆蓋畫素電極PE2。形成閘極G於開口OP、半導體層340以及閘極絕緣層GI上。在一些實施例中,閘極G與掃描線SL是於同一道圖案化製程中所形成。閘極G與掃描線SL電性連接,此時已完成主動元件T’’之製作,主動元件T’’係為頂部閘極型薄膜電晶體。Referring to FIGS. 6G and 7G, a gate insulating layer GI is formed on the opening OP, the semiconductor layer 340, and the auxiliary insulating layer 110. The gate insulating layer GI covers the pixel electrode PE2. A gate G is formed on the opening OP, the semiconductor layer 340 and the gate insulating layer GI. In some embodiments, the gate G and the scan line SL are formed in the same patterning process. The gate G is electrically connected to the scanning line SL. At this time, the production of the active element T '' has been completed, and the active element T '' is a top gate thin film transistor.
請參考圖6H及圖7H,形成層間絕緣層150於閘極G上。在一些實施例中,層間絕緣層150還形成於掃描線SL上。形成共用電極COM於層間絕緣層150上,至此,已大致上完成主動元件基板30的製造過程。在本實施例中,共用電極COM在沿基板100的法線方向N上,重疊於畫素電極PE2。Referring to FIGS. 6H and 7H, an interlayer insulating layer 150 is formed on the gate electrode G. In some embodiments, the interlayer insulating layer 150 is also formed on the scan lines SL. The common electrode COM is formed on the interlayer insulating layer 150. So far, the manufacturing process of the active device substrate 30 has been substantially completed. In this embodiment, the common electrode COM overlaps the pixel electrode PE2 in the normal direction N along the substrate 100.
主動元件基板30與主動元件基板20的主要差別在於主動元件基板30的畫素電極PE2是藉由第三圖案化光阻層360圖案化移除畫素電極材料層PEM的第一部分PEM1,並藉由移除第二圖案化光阻層350、第三圖案化光阻層360的同時一併移除畫素電極材料層PEM的第二部分PEM2而形成,且部份的畫素電極PE2覆蓋於半導體層340的歐姆接觸層320’’上。The main difference between the active device substrate 30 and the active device substrate 20 is that the pixel electrode PE2 of the active device substrate 30 is patterned to remove the first portion PEM1 of the pixel electrode material layer PEM by the third patterned photoresist layer 360, and borrows It is formed by removing the second patterned photoresist layer 350 and the third patterned photoresist layer 360 while removing the second part PEM2 of the pixel electrode material layer PEM, and a part of the pixel electrode PE2 is covered on On the ohmic contact layer 320 "of the semiconductor layer 340.
在本實施例中,藉由第一圖案化光阻層330、第二圖案化光阻層350及第三圖案化光阻層360,可使半導體層340、半導體通道CH、畫素電極PE2以及閘極G能更精準的設置於製程設計的位置上,且能節省製程所需的光罩數量,並在主動元件基板30的製造過程中,藉由輔助絕緣層110的設置控制半導體通道CH的長度L來提升主動元件的啟動電流,進一步縮小主動元件面積來提升顯示區AR的開口率,而獲得較佳的主動元件基板30。In this embodiment, by using the first patterned photoresist layer 330, the second patterned photoresist layer 350, and the third patterned photoresist layer 360, the semiconductor layer 340, the semiconductor channel CH, the pixel electrode PE2, and The gate G can be more accurately set at the position of the process design, and can save the number of photomasks required for the process. In the manufacturing process of the active element substrate 30, the semiconductor channel CH is controlled by the setting of the auxiliary insulating layer 110. The length L is used to increase the startup current of the active device, further reduce the area of the active device to increase the aperture ratio of the display area AR, and obtain a better active device substrate 30.
圖8是依照本發明的一實施例的一種主動元件基板的剖面示意圖。在此必須說明的是,圖8的實施例沿用圖2A~圖2M的實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and parts of the embodiments of FIGS. 2A to 2M, wherein the same reference numerals are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.
請參考圖8,形成第一導線層M1於基板100的周邊區BR上。在本實施例中,第一導線層M1與源極S可由相同膜層圖案化形成。在其他替代性的實施例中,第一導線層M1與源極S可由不同膜層圖案化形成,但本發明不以此為限。Referring to FIG. 8, a first wiring layer M1 is formed on the peripheral region BR of the substrate 100. In this embodiment, the first wiring layer M1 and the source electrode S can be formed by patterning the same film layer. In other alternative embodiments, the first wiring layer M1 and the source electrode S may be formed by patterning different film layers, but the present invention is not limited thereto.
形成第二導線層M2於閘極絕緣層GI上。第二導線層M2位於基板100的周邊區BR上。在本實施例中,第二導線層M2與閘極G可由相同膜層圖案化形成。在其他替代性的實施例中,第二導線層M2與閘極G可由不同膜層圖案化形成,但本發明不以此為限。A second wire layer M2 is formed on the gate insulating layer GI. The second wire layer M2 is located on the peripheral region BR of the substrate 100. In this embodiment, the second wire layer M2 and the gate electrode G may be formed by patterning the same film layer. In other alternative embodiments, the second wire layer M2 and the gate electrode G may be formed by patterning different film layers, but the present invention is not limited thereto.
形成導通結構400於閘極絕緣層GI的接觸窗C1內,接觸窗C1重疊於第一導線層M1且不重疊於第二導線層M2。導通結構400電性連接第一導線層M1與第二導線層M2。The conductive structure 400 is formed in the contact window C1 of the gate insulating layer GI. The contact window C1 overlaps the first wire layer M1 and does not overlap the second wire layer M2. The conducting structure 400 is electrically connected to the first wire layer M1 and the second wire layer M2.
在本實施例中,層間絕緣層150形成於第二導線層M2上,層間絕緣層150具有接處窗C2以及接處窗C3,接處窗C2重疊於接處窗C1以暴露出第一導線層M1,接處窗C3暴露出第二導線層M2。導通結構400更形成於接處窗C2以及接處窗C3內,以電性連接第一導線層M1與第二導線層M2。第一導線層M1與第二導線層M2互相堆疊以構成扇出線102,藉此可以降低扇出線102的阻抗。In this embodiment, the interlayer insulation layer 150 is formed on the second wire layer M2. The interlayer insulation layer 150 has a junction window C2 and a junction window C3. The junction window C2 overlaps the junction window C1 to expose the first wire. Layer M1, and the contact window C3 exposes the second wire layer M2. The conducting structure 400 is further formed in the junction window C2 and the junction window C3 to electrically connect the first wire layer M1 and the second wire layer M2. The first wire layer M1 and the second wire layer M2 are stacked on each other to form a fan-out line 102, thereby reducing the impedance of the fan-out line 102.
在本實施例中,導通結構400與共用電極COM可由相同膜層圖案化形成。在其他替代性的實施例中,導通結構400與共用電極COM可由不同膜層圖案化形成,但本發明不以此為限。此外,上述之扇出線102是以雙層導線結構為例來說明,但本發明不限於此。在其他實施例中,上述之扇出線102也可以是單層導線結構。In this embodiment, the conductive structure 400 and the common electrode COM can be formed by patterning the same film layer. In other alternative embodiments, the conductive structure 400 and the common electrode COM may be formed by patterning different film layers, but the present invention is not limited thereto. In addition, the above-mentioned fan-out line 102 is described by taking a double-layer wire structure as an example, but the present invention is not limited thereto. In other embodiments, the fan-out line 102 described above may also be a single-layer wire structure.
綜上所述,本發明的主動元件基板藉由在輔助絕緣層中形成開口,可使半導體層、閘極絕緣層以及閘極能更精準的設置於製程設計的位置上,且能節省製程所需的光罩數量,並藉由輔助絕緣層110的設置控制半導體通道CH的長度L來提升主動元件的啟動電流,進一步縮小主動元件面積來提升顯示區AR的開口率,而獲得開口率較佳的主動元件基板。In summary, by forming an opening in the auxiliary insulating layer of the active device substrate of the present invention, the semiconductor layer, the gate insulating layer, and the gate can be more accurately set at the position of the process design, and the manufacturing process can be saved. The required number of photomasks, and the length L of the semiconductor channel CH is controlled by the setting of the auxiliary insulating layer 110 to increase the startup current of the active device, further reducing the area of the active device to increase the aperture ratio of the display area AR, and the aperture ratio is better Active component substrate.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
10、20、30‧‧‧主動元件基板10, 20, 30‧‧‧‧ Active component substrate
100‧‧‧基板 100‧‧‧ substrate
102‧‧‧扇出線 102‧‧‧fanout line
104‧‧‧軟性電路板 104‧‧‧flexible circuit board
110‧‧‧輔助絕緣層 110‧‧‧ auxiliary insulation
120、210、330‧‧‧第一圖案化光阻層 120, 210, 330‧‧‧‧ the first patterned photoresist layer
130、130’、220、340‧‧‧半導體層 130, 130 ’, 220, 340‧‧‧ semiconductor layer
140、230、350‧‧‧第二圖案化光阻層 140, 230, 350‧‧‧‧ Second patterned photoresist layer
150‧‧‧層間絕緣層 150‧‧‧ interlayer insulation
310、320、320’、320’’‧‧‧歐姆接觸層 310, 320, 320 ’, 320’’‧‧‧ohm contact layer
360‧‧‧第三圖案化光阻層 360‧‧‧ The third patterned photoresist layer
370‧‧‧通孔 370‧‧‧through hole
400‧‧‧導通結構 400‧‧‧Conduction structure
AA’、BB’、CC’‧‧‧線 AA ’, BB’, CC’‧‧‧ line
AR‧‧‧顯示區 AR‧‧‧Display Area
BR‧‧‧周邊區 BR‧‧‧Peripheral area
C1、C2、C3‧‧‧接觸窗 C1, C2, C3‧‧‧ contact windows
CH‧‧‧半導體通道 CH‧‧‧Semiconductor Channel
COM‧‧‧共用電極 COM‧‧‧Common electrode
D‧‧‧汲極 D‧‧‧ Drain
DL‧‧‧資料線 DL‧‧‧Data Line
G‧‧‧閘極 G‧‧‧Gate
GI‧‧‧閘極絕緣層 GI‧‧‧Gate insulation
L‧‧‧長度 L‧‧‧ length
M1‧‧‧第一導線層 M1‧‧‧First wire layer
M2‧‧‧第二導線層 M2‧‧‧Second wire layer
N‧‧‧法線方向 N‧‧‧normal direction
OP、OP1‧‧‧開口 OP, OP1‧‧‧ opening
PE、PE1、PE2‧‧‧畫素電極 PE, PE1, PE2 ‧‧‧ pixel electrodes
PEM‧‧‧畫素電極材料層 PEM‧‧‧Pixel electrode material layer
PEM1‧‧‧第一部分 PEM1‧‧‧Part I
PEM2‧‧‧第二部分 PEM2‧‧‧ Part Two
PEM3‧‧‧第三部分 PEM3‧‧‧ Part III
S‧‧‧源極 S‧‧‧Source
SL‧‧‧掃描線 SL‧‧‧scan line
SLI‧‧‧狹縫 SLI‧‧‧Slit
SM‧‧‧半導體材料層 SM‧‧‧Semiconductor material layer
T、T’、T’’‧‧‧主動元件 T, T ’, T’’‧‧‧ active element
W‧‧‧水平距離 W‧‧‧Horizontal distance
圖1是依照本發明的一實施例的一種主動元件基板的上視示意圖。 圖2A~圖2M是依照本發明的一實施例的一種主動元件基板的製造方法的局部剖面示意圖。 圖3A~圖3I是依照本發明的一實施例的一種主動元件基板的製造方法的局部上視示意圖。 圖4A~圖4K是依照本發明的一實施例的一種主動元件基板的製造方法的局部剖面示意圖。 圖5A~圖5I是依照本發明的一實施例的一種主動元件基板的製造方法的局部上視示意圖。 圖6A~圖6H是依照本發明的一實施例的一種主動元件基板的製造方法的局部剖面示意圖。 圖7A~圖7H是依照本發明的一實施例的一種主動元件基板的製造方法的局部上視示意圖。 圖8是依照本發明的一實施例的一種主動元件基板的剖面示意圖。FIG. 1 is a schematic top view of an active device substrate according to an embodiment of the present invention. 2A to 2M are schematic partial cross-sectional views of a method for manufacturing an active element substrate according to an embodiment of the present invention. 3A to 3I are schematic partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 4A-4K are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 5A to 5I are schematic partial top views of a method for manufacturing an active element substrate according to an embodiment of the present invention. 6A-6H are schematic partial cross-sectional views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 7A-7H are partial top views of a method for manufacturing an active device substrate according to an embodiment of the present invention. 8 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.
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TW201523106A (en) * | 2013-12-02 | 2015-06-16 | Innolux Corp | Display panel and display device using the same |
TW201601317A (en) * | 2014-06-30 | 2016-01-01 | 台灣積體電路製造股份有限公司 | Vertical transistor device and method for manufacturing the same |
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