CN101385144B - 用于标准正交电路的混合取向方案 - Google Patents
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Abstract
本发明的实施例的一种集成电路包括混合取向衬底(600),其包括具有第一晶体取向的第一区域和具有第二晶体取向的第二区域。所述第一区域的所述第一晶体取向不平行或垂直于所述第二区域的所述第二晶体取向。所述集成电路还包括在所述第一区域上的第一类型器件(620)和在所述第二区域上的第二类型器件(630),其中所述第一类型器件(620)平行或垂直于所述第二类型器件(630),并且所述第一类型器件(620)包括彼此正交的第一电流流动(621)和第二电流流动(622),其中所述第一电流流动(621)和第二电流流动(622)的载流子迁移率彼此相等。具体而言,所述第一类型器件包括p型场效应晶体管(PFET)以及所述第二类型器件包括n型场效应晶体管(NFET)。
Description
技术领域
这里的实施例提出了一种用于标准正交电路的混合取向方案的器件、方法等等。
背景技术
众所周知,在电流流动方向沿<110>方向的(110)硅衬底的空穴迁移率大于常规(100)衬底的两倍,或等价地、大于任何具有沿<001>族取向的衬底的两倍。然而电子迁移率在(100)衬底上是最高的。为充分利用取决于表面取向的载流子迁移率的优点,已在具有不同晶体取向的混合衬底上制备CMOS器件,NFET在(100)表面取向的硅上以及PFET在(110)表面取向上NFET和PFET电流流动都被选择为沿<110>方向。已经验证了使用90nm技术的物理栅极氧化物厚度薄至1.2nm的高性能CMOS器件。已获得了显著的PFET的增强。然而,当集成电路需要具有多个取向的PFET时,例如在集成电路中一些PFET定向为正交于其它的PFET,当使用常规<001>衬底时,具有不同的取向的PFET将具有基本上不同的性能特性。
因此,需要一种包括具有多个取向的PFET的集成电路,其中该多个取向的PFET具有等价的高性能。
发明内容
这里的实施例提供了一种器件、方法等用于标准正交电路的混合取向方案。本发明的实施例的一种集成电路包括混合取向衬底,其包括具有第一晶体取向的第一区域和具有第二晶体取向的第二区域。所述第一晶体取向为(110)表面,其中多晶硅栅极对准为使其源极-漏极方向为(-11sqrt(2))或(1-1sqrt(2))方向。这里,所述两个栅极取向彼此正交并具有相同的电流流动方向。所述第二晶体取向为具有(110)和(1-10)多晶硅栅极取向的(001)表面。所述第一区域的所述第一晶体取向不平行或垂直于所述第二区域的所述第二晶体取向。所述集成电路还包括在所述第一区域上的第一类型器件和在所述第二区域上的第二类型器件(每一个都包括多晶硅栅极),其中所述第一类型器件平行或垂直于所述第二类型器件。具体而言,所述第一类型器件包括p型场效应晶体管(PFET)以及所述第二类型器件包括n型场效应晶体管(NFET)。
在所述第一区域内,构建所述正交的栅极以便所述第一类型器件包括第一方向电流流动和第二方向电流流动,其中所述第一电流流动正交于所述第二电流流动。所述第一电流流动的第一载流子迁移率等于所述第二电流流动的第二载流子迁移率。构建所述第二区域正交栅极以便所述第二类型器件同样包括具有相同的载流子迁移率的第一方向电流流动和第二方向电流流动。
这里的实施例还包括一种形成集成电路的方法,其中所述方法将具有第一晶体取向的第一晶片附着到具有第二晶体取向的第二晶片以便所述第一晶体取向不平行或垂直于所述第二晶体取向。接下来,所述方法在所述第一晶片内刻蚀开口并通过所述开口生长所述第二晶片以在所述第一晶片内构建第二晶片区域。然后,所述方法在所述第一晶片区域上形成第一类型器件并在所述第二晶片区域上形成第二类型器件。具体而言,所述第一和第二类型器件的形成包括形成PFET和NFET。
此外,将所述第二类型器件形成为平行或垂直于所述第一类型器件。当附着所述第一晶片时,以使所述第一类型器件包括第一电流流动和第二电流流动的角度将所述第一晶片附着到所述第二晶片,其中所述第一电流流动正交于所述第二电流流动。此外,所述方法形成具有第一和第二电流流动的所述第一类型器件,所述第一和第二电流流动分别具有第一载流子迁移率和第二载流子迁移率,其中所述第一载流子迁移率等于所述第二载流子迁移率。此外,所述方法形成了同样具有第一和第二电流流动的所述第二类型器件,所述第一和第二电流流动具有相同的载流子迁移率。
因此,所述两个面内正交方向具有相同的迁移率。它们沿(11sqrt(2))和(11-sqrt(2))方向。虽然不能直接测量沿(11sqrt(2))方向的电流流动的迁移率,合理的提议为空穴迁移率值将在<110>(100)与<110>(110)方向的值之间。因此,取代用于现有技术的两个正交方向的大偏斜的157%和70%的获益,这里的实施例沿两个方向都得到了约110%的获益。这给出了集成正交设计的电路的主要结构机会。
当结合下列描述和附图考虑时,将更好地了解和理解本发明的这些、和其它的方面和目的。然而,应该理解,以示例而不是限制的方式给出了下列描述,虽然其指出了本发明的实施例和多个具体细节。可以在本发明的范围内做出多种改变和修改而在不背离其精神,并且本发明包括所有这样的修改。
附图说明
通过下列详细的描述并参考附图,将更好的理解本发明,其中:
图1A和1B是示例了依赖于表面取向的载流子迁移率的图;
图2A和2B是示例了使用混合取向技术的半导体器件的图;
图3A、3B、3C、4A、4B、以及4C示例了用于形成使用了混合取向技术的半导体器件的方法步骤的图;
图5A、5B、5C和5D示例了使用了混合取向技术的半导体器件的表面和电流流动方向的图;
图6是示例了集成电路的图;以及
图7是示例了本发明的方法的流程图。
具体实施方式
通过参考附图和下列的描述中详述的非限制性实施例,更充分地解释了本发明及其各种特征和有利的细节。应该注意,在附图中示例的特征不必按比例绘制。略去了对公知的组件和处理技术的描述以免不必要地模糊本发明。这里使用的实例仅仅旨在有助于理解实践本发明的方法和进一步使本领域的技术人员能够实践本发明。因此,不应将实例解释为限制本发明的范围。
本发明的实施例提出了具有相同的迁移率的两个面内正交电流流动。虽然不能直接测量电流流动的迁移率,合理的提议为空穴迁移率值在<110>(100)和<110>(110)的空穴迁移率值之间。因此,取代用于现有技术的两个正交方向的高偏斜的157%和70%的获益,这里的实施例沿两个方向都得到约110%的获益。这给出了集成正交设计的电路的主要结构机会。主要关注为了集成而需要最优化的多个工艺节点。对于NFET和PFET,如果退回到常规<001>表面器件,那么两个正交器件的比率将根本上改变并且电路设计会失败。
已经提出混合取向方案(Yang等,IEDM 2002)以平衡最好的空穴和电子迁移率优点。在(100)晶片表面上电子迁移率最高,而在(110)表面上空穴迁移率最高,如图1A-1B所示。
更具体而言,实线表示在(110)晶片表面上的载流子迁移率;点线表示在(111)晶片表面上的载流子迁移率;以及虚线表示在(100)晶片表面上的载流子迁移率。因此,Yang提出了图2A-2B中的结构,其中n型场效应晶体管(NFET)在(100)表面而p型场效应晶体管(PFET)在(110)表面,以及在图3和4中示出用于该结构的工艺。具体而言,图2A示例了在(110)绝缘体上硅24上的PFET 20和在(100)硅处理晶片25上的NFET 21,其中STI构件28在(100)硅处理晶片25的上部。此外,图2B示例了在(100)绝缘体上硅26上的NFET 22和在(110)硅处理晶片27上的PFET 23,其中STI构件28在(110)硅处理晶片27的上部。
关键工艺步骤 | 类型A(图2A) | 类型B(图2B) |
层转移@接合 | 在(110)硅中 | 在(100)硅中 |
选择性外延 | 生长(100)硅 | 生长(110)硅 |
图3A示例了薄氧化物和氮化物淀积,其中在硅处理晶片300上形成掩埋氧化物层(BOX)302,在BOX 302上形成绝缘体上硅304并在绝缘体上硅304上形成氮化物层306。接下来,将氮化物层306、绝缘体上硅304、以及BOX 302的中间部分去除以形成空隙307,其中在空隙307中形成隔离物308(图3B)。通过空隙307外延生长上硅处理晶片300,然后化学机械抛光(图3C)。如图4A中所示例的,去除氮化物层306。
接下来,在绝缘体上硅304与硅处理晶片300的外延生长部分之间构建标准浅沟道隔离。还去除了隔离物308(图4B)。将栅极和隔离物器件310形成在绝缘体上硅304和硅处理晶片300的外延生长部分之上(图4C)。
图5A和5B示出了(100)表面的NFET和(110)表面的PFET的栅极的取向。图5C示例了栅极、源极以及漏极区域的顶视图。在用于NFET的(100)表面上,电流流动为<110>方向。在(110)表面上,空穴迁移率沿<110>方向最高(图5D)。Yang提出沿(110)方向对准栅极以获得最大获益。然而,虽然其具有最好的迁移率获益,但其使得电路设计复杂。这是因为正交于<110>方向的PFET器件具有沟道电流流动<100>方向。这会使两个器件不同。在SRAM和其它逻辑电路中,这会造成电路设计中的复杂的附加的层并限制栅极取向。
现在参考图6,本发明的实施例包括具有凹口610、PFET 620、以及NFET 630的混合取向衬底600。衬底600可以表示类型A结构,其中PFET620在(110)绝缘体上硅(即,(110)晶体取向的表面)上并且NFET 630在(100)硅外延层(即,(100)晶体取向的表面)上;或类型B结构,其中NFET 630在(100)绝缘体上硅上并且PFET 620在(110)硅外延层之上(参见图2)。
每一个PFET 620和每一个NFET 630包括源极、漏极、沟道、以及栅极(未示出)。可以可选地使用扩展。源极和漏极是衬底600中的重掺杂的区域,其中多数载流子通过源极流动到沟道中并通过漏极流出。沟道是连接源极和漏极的高导电性区域,其中通过栅极控制沟道的导电性。
PFET 620包括不同的栅极取向并包括电流流动621和622;以及NFET 630包括不同的栅极取向并包括电流流动631和632。具体而言,将电流流动621定向为沿<1-1sqrt(2)>方向并将电流流动622定向为沿<-11sqrt(2)>方向。电流流动621正交于电流流动622。
通过层转移技术采用晶片接合形成衬底600。首先将氢注入到用于类型A的具有(110)取向或用于类型B的具有(100)取向的氧化的硅衬底中。然后将晶片倒装接合至具有不同表面取向的处理晶片。然后进行两阶段(phase)热处理以分离注入氢的晶片并增强接合。最终抛光顶SOI(绝缘体上硅)层并减薄至希望的厚度例如约50nm。
在图3和4中示出了在混合衬底上的CMOS制造的工艺流程。增加了一个附加的光刻层至标准CMOS工艺,使用该附加的光刻层以蚀刻通过SOI和掩埋的氧化物层从而暴露处理晶片的表面。在类型A衬底的情况下开口的区域用于NFET 630或对于类型B则用于PFET 620。在隔离物形成之后,利用快速热化学气相淀积通过开口选择性生长外延硅。由于外延的特性,该外延硅的晶体取向将与处理晶片相同。获得了来自(100)和(110)处理晶片的无缺陷硅外延层。在隔离物缺失的情况下,会产生在从SOI层生长的外延硅与处理晶片之间的缺陷界面,这可以通过改进的工艺来去除。为了避免来自归因于选择性外延的刻面(facet)的潜在的问题,将外延硅厚度调整到这样的程度,其中外延层的整个面完全在薄氮化物的顶表面之上。利用化学机械抛光(CMP)抛光掉过量的硅至薄氮化物并回蚀刻以与SOI表面齐平。用于在NFET(或PFET)区域中的硅外延的附加的光刻层为大阻挡层(几倍于临界尺寸),并可以按比例缩放超过45nm技术节点。
在去除薄氮化物和氧化物之后,继续CMOS制造(包括两种类型的器件),包括浅沟隔离、井注入、栅极氧化物和多晶硅栅极形成、隔离物(氧化物或氮化物或其多个的组合)形成、用于结形成的注入(晕圈、扩展、源极/漏极等等)硅化物形成(可以为Ni、Co、Pt、NiPt、NiPtRe、Pd、Ti、以及其它是2或3相硅化物)以及金属接触(W、Cu等等)。构图栅极叠层用于多重取向PFET以具有沿<1-1sqrt(2)>方向的第一电流流动(即,电流流动621)和沿<-11sqrt(2)>方向的第二电流流动(即,电流流动622)。
因此,这里的实施例提出了包括混合取向衬底600的集成电路,包括具有第一晶体取向的第一区域和具有第二晶体取向的第二区域。第一区域的第一晶体取向不平行或不垂直于第二区域的第二晶体取向。例如,如上所述,第一区域在(110)绝缘体上硅(类型A)上或在(110)硅外延层(类型B)上。此外,第二区域在(100)硅外延层(类型A)上或在(100)绝缘体上硅(类型B)上。本发明的实施例涵盖上述具有双SOI和用于体的直接硅接合的HOT组合。
集成电路还包括在第一区域上的第一类型器件和在第二区域上的第二类型器件,其中第一类型器件平行或垂直于第二类型器件。更具体而言,第一类型器件包括PFET 620以及第二类型器件包括NFET 630。如上所述,每一个PFET 620和每一个NFET 630包括源极、漏极、沟道、以及栅极。源极和漏极是在衬底600内的重掺杂的区域,其中多数载流子通过源极流动到沟道中并通过漏极流出。沟道是连接源极和漏极的高导电性区域,其中通过栅极控制沟道的导电性。
因而,这里的实施例平衡了最佳的空穴和电子迁移率的优点。如上所述,在<001>晶片表面上电子迁移率最高而在<110>表面上空穴迁移率最高,如图1所示。本发明的实施例包括在<110>表面上的PFET 620和在<001>表面上的NFET 630。
此外,第一类型器件包括第一电流流动和第二电流流动,其中第一电流流动正交于第二电流流动,并且其中第一电流流动的第一载流子迁移率等于第二电流流动的第二载流子迁移率。
这里的实施例还包括一种形成集成电路的方法,其中该方法将具有第一晶体取向的第一晶片(例如(110)绝缘体上硅)附着到具有第二晶体取向的第二晶片(例如(100)硅外延层)使得第一晶体取向不平行或垂直于第二晶体取向。如上所述,进行两阶段热处理以分离注入氢的晶片(即第一晶片)并增强接合。由于不同的活化能,(110)晶片需要较高的分离温度。将顶SOI(绝缘体上硅)层抛光并减薄到希望的厚度例如约50nm。
接下来,该方法在第一晶片内蚀刻开口并通过开口生长第二晶片以在第一晶片内构建第二晶片区域。如上所述,为了避免来自归因于选择性外延的刻面的潜在的问题,将外延硅厚度调整到这样的程度,其中外延层的整个面完全在薄氮化物的顶表面之上。利用化学机械抛光(CMP)抛光掉过量的硅至薄氮化物并回蚀刻以与SOI表面齐平。用于在NFET(或PFET)区域中的硅外延的附加的光刻层为大阻挡层(几倍于临界尺寸),并可按比例缩放超过45nm技术节点。
然后,该方法在第一晶片上形成第一类型器件并在第二晶片区域上形成第二类型器件,其中将第二类型器件形成为平行或垂直于第一类型器件。具体而言,第一和第二类型器件的形成包括形成PFET 620和NFET 630。如上所述,每一个PFET 620和每一个NFET 630包括源极、漏极、沟道、以及栅极。
此外,当附着第一晶片时,以使第一类型器件包括第一电流流动和第二电流流动的角度将第一晶片附着到第二晶片,其中第一电流流动正交于第二电流流动。例如,将电流流动621形成为沿<1-1sqrt(2)>方向定向并将电流流动622形成为沿<-11sqrt(2)>方向定向。此外,第一电流流动的第一载流子迁移率等于第二电流流动的第二载流子迁移率。因此,如上所述,这里的实施例平衡了最佳的空穴和电子迁移率优点,其中在<001>晶片表面上电子迁移率最高而在<110>表面上空穴迁移率最高。
图7示例了一种形成集成电路的方法的流程图。在项目800中,该方法通过将具有第一晶体取向的第一晶片附着到具有第二晶体取向的第二晶片以使第一晶体取向不平行和垂直于第二晶体取向而开始,具有第一晶体取向的第一晶片到具有第二晶体取向的第二晶片以便第一晶体取向不平行或垂直于第二晶体取向。如上所述,将氢注入到具有用于类型A的(110)晶体取向或具有用于类型B的(100)晶体取向的氧化的硅衬底。然后将晶片(即,第一晶片)倒装-接合到具有不同表面取向的处理晶片(即,第二晶片)。
接下来,该方法在第一晶片内蚀刻开口(项目810)并通过开口生长第二晶片以在第一晶片内构建第二晶片(项目820)。如上所述,为标准CMOS工艺增加附加的光刻层,使用该附加的光刻层以蚀刻通过SOI和掩埋的氧化物层从而暴露处理晶片的表面。在类型A衬底的情况下,开口的区域用于NFET 630或对于类型B则用于PFET 620。在隔离物形成之后,利用快速热化学气相淀积通过开口选择性生长外延硅。由于外延的特性,该外延硅的晶体取向将与处理晶片相同。(110)硅的生长速率比(100)硅小。在隔离物缺失的情况下,会产生在从SOI层生长的外延硅与处理晶片之间的缺陷界面,这可以通过改进的工艺来去除。
在这之后,在第一晶片上形成第一类型器件(项目830)并在第二晶片区域上形成第二类型器件(项目840),其中将第二类型器件形成为平行或垂直于第一类型器件(项目842)。第一类型器件的形成和第二类型器件的形成包括形成晶体管,特别地PFET 620和NFET 630。如上所述,每一个PFET 620和每一个NFET 630包括源极、漏极、沟道、以及栅极。源极和漏极是在衬底600内的重掺杂区域,其中多数载流子通过源极流动到沟道中并通过漏极流出。沟道是连接源极和漏极的高电导性区域,其中通过栅极控制沟道的导电性。
此外,在附着第一晶片的步骤期间,以使第一类型器件包括第一电流流动和第二电流流动的角度将第一晶片附着到第二晶片,其中第一电流流动正交于第二电流流动。例如,将电流流动621形成为沿<1-1sqrt(2)>方向定向并将电流流动622形成为沿<-11sqrt(2)>方向定向。此外,第一电流流动等于第二电流流动。
因此,两个面内正交方向具有相同的迁移率。虽然不能直接测量该电流流动的迁移率,合理的提议为空穴迁移率值将在<110>(100)和<110>(110)方向的空穴迁移率值之间。因此,取代用于现有技术的两个正交方向的高偏斜的157%和70%的获益,这里的实施例沿两个方向都得到约110%的获益。这给出了集成正交设计的电路的主要结构机会。主要关注为了集成而需要最优化的多个工艺节点。对于NFET和PFET,如果退回到常规<001>表面器件,那么两个正交器件的比率将根本上改变并且电路设计会失败。
上述特定的实施例的描述将全面揭示本发明的一般本质,使得其他技术人员可以通过应用电流知识容易地修改这样的特定的实施例和/或使其适应各种应用而不脱离一般概念,因此,应该并旨在在公开的实施例的等价物的意义和范围内理解这样的适应和修改。应该理解,这里采用的措辞或术语用于描述而不是限制。因此,虽然关于优选的实施例描述了本发明,但本领域的技术人员将认识到可以在所附权利要求的精神和范围内的修改地实践本发明。
Claims (19)
1.一种集成电路包括:
混合取向衬底(600),包括具有第一晶体取向的第一区域和具有第二晶体取向的第二区域;
第一类型器件(620),在所述第一区域上;以及
第二类型器件(630),在所述第二区域上;
其中所述第一类型器件(620)包括具有第一电流流动(621)的器件和具有第二电流流动(622)的器件,其中所述第一电流流动(621)正交于所述第二电流流动(622),以及其中所述第一电流流动(621)的第一载流子迁移率等于所述第二电流流动(622)的第二载流子迁移率,
其中所述第一晶体取向不平行且不垂直于所述第二晶体取向。
2.根据权利要求1的集成电路,其中所述第一类型器件(620)和所述第二类型器件(630)包括晶体管。
3.根据权利要求2的集成电路,其中所述第一类型器件(620)包括p型场效应晶体管,以及其中所述第二类型器件(630)包括n型场效应晶体管。
4.一种集成电路,包括:
混合取向衬底,包括具有第一晶体取向的第一区域和具有第二晶体取向的第二区域;
第一类型器件(620),在所述第一区域上;以及
第二类型器件(630),在所述第二区域上;
其中所述第一晶体取向不平行且不垂直于所述第二晶体取向。
5.根据权利要求4的集成电路,其中所述第一类型器件(620)和所述第二类型器件(630)包括晶体管。
6.根据权利要求5的集成电路,其中所述第一类型器件(620)包括p型场效应晶体管,以及其中所述第二类型器件(630)包括n型场效应晶体管。
7.根据权利要求4的集成电路,其中所述第一类型器件(620)平行或垂直于所述第二类型器件(630)。
8.根据权利要求4的集成电路,其中所述第一晶体取向与所述第二晶体取向之间的角度使得所述第一类型器件(620)包括具有第一电流流动(621)的器件和具有第二电流流动(622)的器件,其中所述第一电流流动(621)正交于所述第二电流流动(622)。
9.根据权利要求4的集成电路,其中所述第一类型器件(620)包括具有第一电流流动(621)的器件和具有第二电流流动(622)的器件,其中所述第一电流流动(621)的第一载流子迁移率等于所述第二电流流动(622)的第二载流子迁移率。
10.一种形成集成电路的方法,包括以下步骤:
将具有第一晶体取向的第一晶片(304)附着到具有第二晶体取向的第二晶片(300)使得所述第一晶体取向不平行且不垂直于所述第二晶体取向;
在所述第一晶片(304)内刻蚀开口(307)以暴露所述第二晶片(300);
通过所述开口(307)生长所述第二晶片(300)以在所述第一晶片(304)内构建第二晶片区域;
在所述第一晶片(304)上形成所述第一类型器件(620);以及
在所述第二晶片区域上形成第二类型器件(630)。
11.根据权利要求10的方法,其中形成所述第一类型器件(620)和形成所述第二类型器件(630)包括形成晶体管。
12.根据权利要求11的方法,其中形成所述第一类型器件(620)和形成所述第二类型器件(630)包括形成p型场效应晶体管和n型场效应晶体管。
13.根据权利要求10的方法,其中形成所述第二类型器件(630)包括形成平行或垂直于所述第一类型器件(620)的所述第二类型器件(630)。
14.根据权利要求10的方法,其中附着所述第一晶片(304)包括以使所述第一类型器件(620)包括具有第一电流流动(621)的器件和具有第二电流流动(622)的器件的角度将所述第一晶片(304)附着到所述第二晶片(300),其中所述第一电流流动(621)正交于所述第二电流流动(622)。
15.根据权利要求10的方法,其中形成所述第一类型器件(620)包括形成具有第一电流流动(621)的器件和具有第二电流流动(622)的器件,其中所述第一电流流动(621)的第一载流子迁移率等于所述第二电流流动(622)的第二载流子迁移率。
16.一种形成集成电路的方法,包括以下步骤:
将具有第一晶体取向的第一晶片(304)附着到具有第二晶体取向的第二晶片(300)使所述第一晶体取向不平行且不垂直于所述第二晶体取向;
在所述第一晶片(304)内刻蚀开口(307)以暴露所述第二晶片(300);
通过所述开口(307)生长所述第二晶片(300)以在所述第一晶片(304)内构建第二晶片区域;
在所述第一晶片(304)上形成所述第一类型器件(620);以及
在所述第二晶片区域上形成第二类型器件(630),
其中附着所述第一晶片(304)包括以使所述第一类型器件(620)包括具有第一电流流动(621)的器件和具有第二电流流动(622)的器件的角度将所述第一晶片(304)附着到所述第二晶片(300),其中所述第一电流流动(621)正交于所述第二电流流动(622)。
17.根据权利要求16的方法,其中形成所述第一类型器件(620)和形成所述第二类型器件(630)包括形成p型场效应晶体管和n型场效应晶体管。
18.根据权利要求16的方法,其中形成所述第二类型器件(630)包括形成平行或垂直于所述第一类型器件(620)的所述第二类型器件(630)。
19.根据权利要求16的方法,其中形成所述第一类型器件(620)包括形成具有第一电流流动(621)的器件和具有第二电流流动(622)的器件,其中所述第一电流流动(621)的第一载流子迁移率等于所述第二电流流动(622)的第二载流子迁移率。
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US11/308,085 US7573104B2 (en) | 2006-03-06 | 2006-03-06 | CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type |
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PCT/US2007/063275 WO2007103854A2 (en) | 2006-03-06 | 2007-03-05 | Hybrid orientation scheme for standard orthogonal circuits |
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US7432174B1 (en) * | 2007-03-30 | 2008-10-07 | Advanced Micro Devices, Inc. | Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations |
US7696573B2 (en) * | 2007-10-31 | 2010-04-13 | International Business Machines Corporation | Multiple crystallographic orientation semiconductor structures |
US8395216B2 (en) | 2009-10-16 | 2013-03-12 | Texas Instruments Incorporated | Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus |
US8415718B2 (en) | 2009-10-30 | 2013-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming epi film in substrate trench |
US9275911B2 (en) | 2012-10-12 | 2016-03-01 | Globalfoundries Inc. | Hybrid orientation fin field effect transistor and planar field effect transistor |
US20150263040A1 (en) * | 2014-03-17 | 2015-09-17 | Silicon Storage Technology, Inc. | Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same |
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EP1997145A2 (en) | 2008-12-03 |
EP1997145A4 (en) | 2011-07-06 |
US7573104B2 (en) | 2009-08-11 |
CN101385144A (zh) | 2009-03-11 |
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US20090206412A1 (en) | 2009-08-20 |
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