CN101383632B - TD-SCDMA terminal receiver chip - Google Patents
TD-SCDMA terminal receiver chip Download PDFInfo
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Abstract
The invention provides a time division duplex and synchronous CDMA terminal receiver chip structure of a mobile communication system, which integrates the treatment of a physical layer and a protocol stack. The physical layer comprises a synchronous module, a joint detection module and a Viterbi/Turbo code decoding module. The joint detection module also comprises a square root decomposition module and a forward/backward iterative module. At the same time, the structure integrates into an FFT controller, and can utilize FFT to perform the single user detection.
Description
Technical field
The invention belongs to wireless communication technology field, relate to particularly the framework of a kind of TD-SCDMA (time division duplex-synchonism CDMA mobile communication system) terminal receiver chip.
Background technology
TD-SCDMA (time division duplex-synchonism CDMA mobile communication system) is a kind of 3G (Third Generation) Moblie standard that is proposed by China, is one of the world's three large standards.At present, TD-SCDMA will soon move towards to use in China, and the research of relevant TD-SCDMA is just like a raging fire.
TD-SCDMA is owing to adopt joint detection algorithm, and algorithm complex is high, and terminal realizes complicated.Now, domestic have four companies to develop the TD-SCDMA terminal chip.They are: the Shanghai spreadtrum, Shanghai is triumphant bright, Beijing T3G and Chongqing CYIT.Because digital signal processor (DSP) and joint detection algorithm that each company adopts are not quite similar, each company's chip architecture is also different.But generally speaking, these chips all be that area is large, power consumption is high, expensive.
Summary of the invention
The object of the present invention is to provide a kind of TD-SCDMA (time division duplex-synchonism CDMA mobile communication system) terminal receiver chip, the defective that exists to overcome the known technology chips.
For achieving the above object, TD-SCDMA terminal receiver chip provided by the invention comprises:
One arm processor;
One digital signal processor;
One synchronous module;
One joint-detection module; And
One Viterbi/Turbo decoder module; Wherein
Synchronization module is connected respectively on the local bus by static memory m3 by static memory m2, Viterbi/Turbo decoder module by static memory m1, joint-detection module; And
Be respectively applied to exchanges data between synchronization module, joint-detection module, Viterbi/Turbo decoder module and the digital signal processor by static memory;
Local bus is by DSP CONTROL;
Digital signal processor is connected on the arm processor by ahb bus;
Synchronization module, joint-detection module and Viterbi/Turbo decoder module is by the digital signal processor centralized control;
The exchange of the control information between synchronization module, joint-detection module and Viterbi/Turbo decoder module and the digital signal processor is finished by the IO bus of digital signal processor.
Described chip, wherein, the constituting of synchronization module:
Sampling error detection, loop filter, hits controlled oscillator and interpolater consist of a sampling timing loop;
Frequency deviation estimation, carrier number controlled oscillator and multiplier consist of a frequency deviation and estimate and compensation loop;
Frequency deviation is estimated to be finished by the software in the digital signal processor.
Described chip, wherein, the data between synchronization module and the local bus transmit and give digital signal processor via static memory m1.Wherein, static memory m1 comprises static memory SRAM1 and SRAM2 particularly, and synchronization module alternately is sent to data these two static memories, thereby alternately is sent to digital signal processor DSP.
Described chip, wherein, the data between synchronization module and the local bus transmit through partial matched filter and give digital signal processor via static memory SRAM1 or SRAM2.
Described chip, wherein, static memory m2 and joint-detection module comprise static memory SRAM3, SRAM4, SRAM5, SRAM6, Chol decomposing module and forward direction/backward iteration module particularly, its interconnected relationship is:
Within the time of processing the first time slot, digital signal processor is crossed static memory SRAM3 with data communication device and is given the processing of Chol decomposing module;
Within the time of processing the second time slot, digital signal processor is crossed static memory SRAM4 with data communication device and is given the processing of Chol decomposing module;
The Chol decomposing module of storing in the static memory SRAM3 simultaneously, is delivered to forward direction/backward iteration module to the decomposition result of a upper time slot and is read;
Digital signal processor is given static memory SRAM5 and static memory SRAM6 with first data simultaneously, processes for forward direction/backward iteration module;
After forward direction/backward iteration module is processed, by static memory SRAM5 and static memory SRAM6 with result feedback to digital signal processor;
Forward direction/backward iteration module is processed and is continued by static memory SRAM5 and static memory SRAM6 receive data and processing, by static memory SRAM5 and static memory SRAM6 with result feedback to digital signal processor, until all pieces in this time slot are handled;
Next time slot, forward direction/backward iteration module is by the data of static memory SRAM5 and static memory SRAM6 receiving digital signals processor, receive the data that the Chol decomposing module is sent here by static memory SRAM4, two modules form streamline together, handle one data in every time.
Described chip, wherein, the Chol decomposing module comprises ALU, multiply accumulating unit, FFT controller and Chol controller; Wherein FFT controller and Chol controller shared arithmetic logic unit and multiply accumulating unit; When being operated in single user mode, the FFT controller is controlled these two computing units and is finished FFT and ask work reciprocal.
Described chip, wherein, forward direction/backward iteration module comprises two CMs add up unit, a forward direction/backward iteration control device and a FFT/IFFT controller; Forward direction/backward iteration control device and FFT/IFFT controller share the cumulative unit of two CMs, and the FFT/IFFT controller is used in alone family detecting pattern.
From the description of above-mentioned framework as seen, this framework is corresponding a kind of new, is referred to as the joint detection algorithm of " piece decision-feedback ".Compare with traditional joint detection algorithm based on " approximate Cholesky decomposes ", this algorithm amount of calculation is little, realizes simple.Therefore, this with it chip architecture of correspondence of the present invention has little, the low in energy consumption characteristics of area.
Description of drawings
Figure 1 shows that the receiver chip general frame.
Figure 2 shows that the detailed diagram of synchronization module among Fig. 1.
Fig. 3 is the detailed diagram of synchronization module among Fig. 1, static memory m1 and local bus.
Fig. 4 is the detailed block diagram of static memory m2 and joint-detection module among Fig. 1.
Fig. 5 is the detailed diagram of Chol decomposing module among Fig. 4.
Fig. 6 is the detailed diagram of forward direction among Fig. 4/backward iteration module.
Embodiment
Chip general frame provided by the invention comprises an arm processor 1, digital signal processor DSP2, synchronization module 3, joint-detection module 4 and a Viterbi/Turbo (turbine) decoder module 5 as shown in Figure 1.Wherein synchronization module 3 is connected respectively on the local bus B1 by static memory m3 by static memory m2, Viterbi/Turbo decoder module 5 by static memory m1, joint-detection module 4.Local bus B1 is controlled by DSP2.DSP2 is connected on the arm processor 1 by ahb bus B2.Static memory m1, static memory m2 and static memory m3 are respectively applied to the exchanges data between synchronization module 3, joint-detection module 4, Viterbi/Turbo decoder module 5 and the digital signal processor DSP module 2.The exchange of the control information between synchronization module 3, joint-detection module 4 and Viterbi/Turbo decoder module 5 and the digital signal processor DSP 2 is finished by the IO bus of DSP2.These modules all are by the DSP2 centralized control.
Wherein the synchronization module structure comprises an interpolater 21, hits controlled oscillator 22, carrier number controlled oscillator 23, raised cosine filter 24, loop filter 25, sampling error detection 26, frequency deviation estimation 27, segmented matched filter 28 and multiplier 29 as shown in Figure 2.Its frequency deviation estimates that 27 are finished by the software in the DSP2 among Fig. 1.Sampling error detection 26, loop filter 25, hits controlled oscillator 22 and interpolater 21 consist of a sampling timing loop.Frequency deviation estimation 27, carrier number controlled oscillator 23 and multiplier 29 consist of a frequency deviation and estimate and compensation loop.
See also Fig. 3, wherein, static memory m1 is made of static memory SRAM1 and static memory SRAM2 particularly.Data between synchronization module and the local bus B1 transmit minute two kinds of patterns: through partial matched filter with without partial matched filter.These two kinds of patterns are selected by Port Multiplier MUX1 and MUX2.The data communication device of exporting under two kinds of patterns crosses static memory SRAM1 and static memory SRAM2 alternately gives DSP2.Under the pattern that is operated in through partial matched filter, two sections matching result is given SRAM1 by MUX1, and SRAM1 completely then gives SRAM2.Digital signal processor DSP 2 among Fig. 1 reads this two SRAM in turn by local bus B1.When partial matched filter was filled in SRAM1, DSP2 read SRAM2, and when partial matched filter was filled in SRAM2, DSP2 read SRAM1.
See also Fig. 4, the static memory m2 among Fig. 1 and joint-detection module 4 comprise static memory SRAM3, static memory SRAM4, static memory SRAM5, static memory SRAM6, Chol decomposing module 41 and forward direction/backward iteration module 42 particularly.Its course of work is as follows: within the time of the first time slot, digital signal processor DSP 2 is crossed SRAM3 with data communication device, gives Chol decomposing module 41 and processes.Within the time of the second time slot, digital signal processor DSP 2 is crossed SRAM4 with data communication device, gives Chol decomposing module 41 and processes.Simultaneously, the result of a time slot on the Chol decomposing module 41 of storage will be sent to forward direction/backward iteration module 42 and read in the SRAM3.DSP2 gives SRAM5 and SRAM6 with the data of the first time slot simultaneously, processes for forward direction/backward iteration module 42.After forward direction/backward iteration module 42 is handled, by SRAM5 and SRAM6 with result feedback to DSP2.At next time slot, forward direction/backward iteration module 42 will still receive the data that DSP sends here by SRAM5, SRAM6, but receive the data that Chol decomposing module 41 is sent here by SRAM4.Continue like this, two modules form streamline together, handle the data of a time slot in the time of every time slot.
As shown in Figure 5, the Chol decomposing module among Fig. 4 comprises arithmetic logic unit ALU51, multiply accumulating unit MAC52, FFT controller 53 and Chol controller 54.Because FFT controller 53 and Chol controller 54 can only have a job simultaneously, so they share computing unit ALU51 and multiply accumulating unit 52.When being operated in single user mode, the FFT controller is controlled these two computing units and is finished FFT and ask work reciprocal.
As shown in Figure 6, the forward direction among Fig. 4/backward iteration module 42 comprises the cumulative unit Complex MAC1 of two CMs and Complex MAC2, a forward direction/backward iteration control device 63 and a FFT/IFFT controller 64.Forward direction/backward iteration control device 63 and FFT/IFFT controller 64 share the cumulative unit of two CMs.The FFT/IFFT controller is used in alone family detecting pattern.
Claims (6)
1. TD-SCDMA terminal receiver chip comprises:
One arm processor;
One digital signal processor;
One synchronous module;
One joint-detection module; And
One Viterbi/Turbo decoder module; Wherein
Synchronization module is connected respectively on the local bus by static memory m3 by static memory m2, Viterbi/Turbo decoder module by static memory m1, joint-detection module; And
Be respectively applied to exchanges data between synchronization module, joint-detection module, Viterbi/Turbo decoder module and the digital signal processor by static memory m1, m2, m3;
Local bus is by DSP CONTROL;
Digital signal processor is connected on the arm processor by ahb bus;
Synchronization module, joint-detection module and Viterbi/Turbo decoder module is by the digital signal processor centralized control;
The exchange of the control information between synchronization module, joint-detection module and Viterbi/Turbo decoder module and the digital signal processor is finished by the IO bus of digital signal processor;
Wherein, static memory m2 and joint-detection module comprise static memory SRAM3, SRAM4, SRAM5, SRAM6, Chol decomposing module and forward direction/backward iteration module particularly, and its interconnected relationship is:
Within the time of processing the first time slot, digital signal processor is crossed static memory SRAM3 with data communication device and is given the processing of Chol decomposing module;
Within the time of processing the second time slot, digital signal processor is crossed static memory SRAM4 with data communication device and is given the processing of Chol decomposing module;
The Chol decomposing module of storing in the static memory SRAM3 simultaneously, is delivered to forward direction/backward iteration module to the decomposition result of a upper time slot and is read;
Digital signal processor is given static memory SRAM5 and static memory SRAM6 with the data of the first time slot simultaneously, processes for forward direction/backward iteration module;
After forward direction/backward iteration module is processed, by static memory SRAM5 and static memory SRAM6 with result feedback to digital signal processor;
Forward direction/backward iteration module continues by static memory SRAM5 and static memory SRAM6 receive data and processes, by static memory SRAM5 and static memory SRAM6 with result feedback to digital signal processor, until all data in this time slot are handled;
Next time slot, forward direction/backward iteration module is by the data of static memory SRAM5 and static memory SRAM6 receiving digital signals processor, receive the data that the Chol decomposing module is sent here by static memory SRAM4, two modules form streamline together, handle the data of a time slot in the time of each time slot.
2. chip according to claim 1, wherein, the constituting of synchronization module:
Sampling error detection, loop filter, hits controlled oscillator and interpolater consist of a sampling timing loop;
Frequency deviation estimation, carrier number controlled oscillator and multiplier consist of a frequency deviation and estimate and compensation loop;
Frequency deviation is estimated to be finished by the software in the digital signal processor.
3. chip according to claim 1, wherein, data between synchronization module and the local bus transmit and give digital signal processor via static memory m1, wherein, static memory m1 comprises static memory SRAM1 and SRAM2 particularly, synchronization module alternately is sent to data these two static memories, thereby alternately is sent to digital signal processor DSP.
4. chip according to claim 3, wherein, the data between synchronization module and the local bus transmit through partial matched filter and give digital signal processor via static memory SRAM1 or SRAM2.
5. chip according to claim 1, wherein, the Chol decomposing module comprises ALU, multiply accumulating unit, FFT controller and Chol controller; Wherein FFT controller and Chol controller shared arithmetic logic unit and multiply accumulating unit; When being operated in single user mode, the FFT controller is controlled these two computing units and is finished FFT and ask work reciprocal.
6. chip according to claim 1, wherein, forward direction/backward iteration module comprises two CMs add up unit, a forward direction/backward iteration control device and a FFT/IFFT controller; Forward direction/backward iteration control device and FFT/IFFT controller share the cumulative unit of two CMs, and the FFT/IFFT controller is used in alone family detecting pattern.
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| CN200710121372XA CN101383632B (en) | 2007-09-05 | 2007-09-05 | TD-SCDMA terminal receiver chip |
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| CN200710121372XA CN101383632B (en) | 2007-09-05 | 2007-09-05 | TD-SCDMA terminal receiver chip |
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| CN101383632A CN101383632A (en) | 2009-03-11 |
| CN101383632B true CN101383632B (en) | 2013-04-24 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1777076A (en) * | 2004-11-16 | 2006-05-24 | 深圳安凯微电子技术有限公司 | Baseband chip with access of time-division synchronous CDMA |
| CN1811740A (en) * | 2006-02-28 | 2006-08-02 | 重庆重邮信科股份有限公司 | Method for achieving multiprocessor share peripheral circuit and its circuit |
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- 2007-09-05 CN CN200710121372XA patent/CN101383632B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1777076A (en) * | 2004-11-16 | 2006-05-24 | 深圳安凯微电子技术有限公司 | Baseband chip with access of time-division synchronous CDMA |
| CN1811740A (en) * | 2006-02-28 | 2006-08-02 | 重庆重邮信科股份有限公司 | Method for achieving multiprocessor share peripheral circuit and its circuit |
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| CN101383632A (en) | 2009-03-11 |
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Effective date of registration: 20220223 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
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