CN1811740A - Method for achieving multiprocessor share peripheral circuit and its circuit - Google Patents

Abstract

Present invention discloses a multiprocessor shared peripheral equipment circuit implementation method and circuit. It contains Each hardware accelerator peripheral equipment connected with a bus switch for switching bus from different processor, processor sending bus applying in using hardware accelerator, bus switch determining whether allowing said processor visiting according to said modular work state, when hardware accelerator completing once data processing, processor sending bus release command for allowing next uses of said accelerator, multiprocessor bus adopting synchronous circuit mergence for frequent visited control register peripheral equipment, so realizing shared peripheral equipment data processing with simple circuit and reasonable design.

Description

Multiprocessor share peripheral circuit implementation method and circuit thereof

Technical field

The present invention relates to the technology of TD-SCDMA hand-set digit baseband processing chip, be specifically related to a kind of multiprocessor share peripheral circuit implementation method and circuit thereof; Belong to the communications electronics technical field.

Background technology

The realization key of TD-SCDMA mobile phone is the digital baseband process chip, and it is a core of finishing TD-SCDMA baseband digital signal processing capacity and physical layer software, communication protocol stack, application layer MMI running software.This chip normally adopts multi-processor structure, cooperating hardware accelerator to finish physical layer signal with two DSP handles, finish the processing of application layer and protocol layer with ARM, therefore design a kind of succinctly, system architecture becomes a key issue of TD-SCDMA mobile phone base band chip efficiently.In existing multi core chip designing technique, the communication of each intermodule realizes by an AMBA bus.Owing to have multiprocessor and shared peripheral module, therefore need special bus arbiter to decide a certain moment to allow which processor to use bus, can cause the decline of communication efficiency.How improving the problem of the communication efficiency decline of multiprocessor and shared peripheral hardware, is that one of ordinary skill in the art have problem to be solved.

Summary of the invention

There is the not high deficiency of communication efficiency at existing multiprocessor share peripheral technology, the purpose of this invention is to provide a kind of effective multiprocessor share peripheral circuit implementation method of improving communication efficiency.

Another object of the present invention provides a kind of multiprocessor share peripheral circuit reasonable in design, simple for structure.

The object of the present invention is achieved like this: multiprocessor share peripheral circuit implementation method, each hardware accelerator peripheral hardware all is connected to a bus switch bus from different processor is switched, processor sends the bus application earlier when using hardware accelerator, whether bus switch allows the visit of this processor according to the duty decision of this module; After a data processing of hardware accelerator and carrying were finished, processor sent the bus release command to allow the use next time of this accelerator; For the frequent control register peripheral hardware of visit, the bus of multiprocessor adopts synchronizing circuit to merge, and has also simplified system design like this when having realized shared peripheral hardware.

Simultaneously, merge according to the priority sequencing and become a bus peripheral hardware is conducted interviews.

Multiprocessor share peripheral circuit by the inventive method realization, comprise the multiprocessor that constitutes by an ARM9 processor and DSP1, DSP2 storer, the DSP subsystem of the hardware accelerator that constitutes by FIR module, JD computing, Viterbi decoding, Turbo code translator and system's timing and control circuits; ARM and peripheral hardware thereof constitute the ARM subsystem; The inner AMBA of employing of ARM subsystem bus connects, by the dual port RAM communication between internal storage interface module IMIF realization ARM subsystem and the DSP subsystem; Adopt bus switch circuit that the bus from different processor is switched; Perhaps adopt the bus synchronous circuit that the bus from different processor is merged, realize multiprocessor share peripheral.

Described DSP1 sends the bus request for utilization by write control register to Viterbi code translator bus switch module, if the Viterbi module is in idle condition, and then bus application success, DSP1 can normally visit and read and write data; If this module is in use, promptly carrying out data processing or taking by DSP2, then refuse the visit of DSP1;

When this Viterbi decoding computing end, DSP1 reads the result data of Viterbi code translator, and the release bus of giving an order.

Compared to existing technology, the present invention has following advantage:

1, adopts the bus switch of design uniqueness between accelerator module and the multiprocessor and the method for bus synchronous circuit, realized sharing peripheral hardware between the multiprocessor, have higher communication efficiency;

2, can guarantee that hardware accelerator is carrying out can not interrupted by another processor in a data handling procedure,, before bus discharges, not have new bus arbitration and change action in case bus is taken by a processor.And present common bussing technique such as individual layer AMBA bus, any moment only allows a main frame and takies bus, and frequent bus arbitration and change action are arranged in the time of multiprocessor share peripheral, has seriously reduced communication efficiency.Though multilayer AMBA bus has solved this problem, the bus structure complexity, the checking workload is big, and can not guarantee the exclusivity of processor to hardware accelerator.

3, circuit of the present invention is used for the digital baseband process chip of TD-SCDMA mobile phone, adopts an arm processor and two dsp processors and TD-SCDMA special circuit and hardware accelerator to constitute, and is simple for structure, reasonable in design.

Description of drawings

Fig. 1 is a system block diagram of the present invention;

Fig. 2 stores the expansion bus block scheme;

Fig. 3 is the structure principle chart of bus switch;

Fig. 4 is the processing elementary diagram of bus synchronous.

Embodiment

Multiprocessor share peripheral circuit implementation method, each hardware accelerator peripheral hardware all is connected to a bus switch bus from different processor is switched, processor sends the bus application earlier when using hardware accelerator, whether bus switch allows the visit of this processor according to the duty decision of this module; After a data processing of hardware accelerator and carrying were finished, processor sent the bus release command to allow the use next time of this accelerator;

For the frequent control register peripheral hardware of visit, the bus of multiprocessor adopts synchronizing circuit to merge.

Simultaneously, merge according to the priority sequencing and become a bus peripheral hardware is conducted interviews.

As shown in Figure 1, by the multiprocessor share peripheral circuit that the inventive method realizes, chip comprises an ARM9 processor, two dsp processors; Hardware accelerator has: FIR wave filter, JD computing, Viterbi decoding, Turbo code translator and system's timing and control circuits and necessary peripheral circuit.

According to the task division of labor of processor, determine that system architecture is as follows: JD, Viterbi, Turbo, FIR module link to each other with the memory expansion bus of DSP1, DSP2, constitute the DSP subsystem; ARM and peripheral hardware thereof constitute the ARM subsystem, the inner AMBA of employing of ARM subsystem bus connects, by the dual port RAM communication between internal storage interface module (IMIF) realization ARM subsystem and the DSP subsystem, adopt bus switch circuit that the bus from different processor is switched; The bus switch of design uniqueness and the method for bus synchronous circuit between accelerator module and the multiprocessor have realized sharing peripheral hardware between the multiprocessor, have higher communication efficiency.

Described DSP1 sends the bus request for utilization by write control register to Viterbi code translator bus switch module, if the Viterbi module is in idle condition, and then bus application success, DSP1 can normally visit and read and write data; If this module is in use, promptly carrying out data processing or taking by DSP2, then refuse the visit of DSP1;

When this Viterbi decoding computing end, DSP1 reads the result data of Viterbi code translator, and the release bus of giving an order.

Adopt the bus synchronous circuit that the bus from different processor is merged, realize multiprocessor share peripheral.

Referring to Fig. 2, the memory expansion bus is made of 32 position datawires, 24 bit address lines, read signal, write signal.Carry out the chip selection signal that address decoding obtains all peripheral modules with the high address line, can carry out the read-write and the control of corresponding module by different address spaces like this.

The switching of bus:, therefore designed bus switch circuit and bus synchronous circuit owing to there is the same peripheral hardware of multiprocessor common access.Mode of operation difference according to peripheral circuit can be divided into two kinds of situations:

1. for hardware accelerator, write a blocks of data by processor earlier, wait until after the startup that computing finishes to read the result again, whole process can only be by some processor control.

2. for control circuit, whenever all may carry out read-write operation by certain processor.

See Fig. 3, for first kind of situation, each accelerator design bus switch switch.The operating process of processor following (is example with DSP1 visit Viterbi code translator): at first, DSP1 sends the bus request for utilization by write control register to Viterbi code translator bus switch circuit, if the Viterbi module is in idle condition, then bus application success, DSP1 can normally visit and read and write data, if this module is in use, (carrying out data processing or taken by DSP2) then refuses the visit of DSP1.When this Viterbi decoding computing end, DSP1 reads the result data of Viterbi code translator, and the release bus of giving an order.Can guarantee that in this way hardware accelerator is carrying out can not interrupted by another processor in a data handling procedure, in case bus is taken by a processor, before bus discharges, do not have new bus arbitration and change action, improved communication efficiency.

Referring to Fig. 4, for second kind of situation, because the clock difference of each processor need be carried out the processing of bus synchronous, to same clock zone, merging according to the priority sequencing becomes a bus peripheral hardware is conducted interviews with the bus synchronous of each processor.Simultaneously need to guarantee that processor can not visit same peripheral hardware at synchronization on the software, therefore this mode is fit to a spot of register data of read-write, as the TD-SCDMA control module.

Claims (4)

1, multiprocessor share peripheral circuit implementation method, be characterised in that: each hardware accelerator peripheral hardware all is connected to a bus switch bus from different processor is switched, processor sends the bus application earlier when using hardware accelerator, whether bus switch allows the visit of this processor according to the duty decision of this module; After a data processing of hardware accelerator and carrying were finished, processor sent the bus release command to allow the use next time of this accelerator;

For the frequent control register peripheral hardware of visit, the bus of multiprocessor adopts synchronizing circuit to merge.

2, multiprocessor share peripheral circuit implementation method according to claim 1 is characterized in that: merging according to the priority sequencing becomes a bus peripheral hardware is conducted interviews.

3, the multiprocessor share peripheral circuit of realizing according to claim 1 or 2 described methods, it is characterized in that: comprise the multiprocessor that constitutes by an ARM9 processor and DSP1, DSP2 storer, the DSP subsystem of the hardware accelerator that constitutes by FIR module, JD computing, Viterbi decoding, Turbo code translator and system's timing and control circuits; ARM and peripheral hardware thereof constitute the ARM subsystem; The inner AMBA of employing of ARM subsystem bus connects, by the dual port RAM communication between internal storage interface module IMIF realization ARM subsystem and the DSP subsystem; Adopt bus switch circuit that the bus from different processor is switched;

Described DSP1 sends the bus request for utilization by write control register to Viterbi code translator bus switch module, if the Viterbi module is in idle condition, and then bus application success, DSP1 can normally visit and read and write data; If this module is in use, promptly carrying out data processing or taking by DSP2, then refuse the visit of DSP1;

When this Viterbi decoding computing end, DSP1 reads the result data of Viterbi code translator, and the release bus of giving an order.

4, multiprocessor share peripheral circuit according to claim 3 is characterized in that: adopt the bus synchronous circuit that the bus from different processor is merged, realize multiprocessor share peripheral.

Images