CN116303169A

CN116303169A - DMA control device and method and chip

Info

Publication number: CN116303169A
Application number: CN202310224280.3A
Authority: CN
Inventors: 刘子威; 刘雨; 苏培源; 陈勇全
Original assignee: Ruixin Micro Beijing Integrated Circuit Co ltd
Current assignee: Ruixin Micro Beijing Integrated Circuit Co ltd
Priority date: 2023-03-09
Filing date: 2023-03-09
Publication date: 2023-06-23

Abstract

The application provides a DMA control device, a method and a chip. The device comprises: a plurality of logic channels configured to receive transmission requests, respectively; a plurality of physical channels configured to perform data transmission based on the transmission requests, respectively; a channel selection module electrically coupled between the plurality of logical channels and the plurality of physical channels and configured to bind a selected logical channel of the plurality of logical channels to an idle physical channel of the plurality of physical channels; and a bus selection module electrically coupled between the plurality of physical channels and a bus and configured to cause a selected physical channel of the plurality of physical channels to access the bus to perform the data transfer. The utility model provides a multichannel, multiplexing DMA controller structure of timesharing can reduce DMA controller area, is favorable to channel quantity extension.

Description

DMA control device and method and chip

Technical Field

The application belongs to the technical field of DMA control, and relates to a control device, in particular to a DMA control device, a DMA control method and a chip.

Background

In general, low-speed peripherals in an SoC (System on Chip) all perform data transmission through a DMA (Direct Memory Access ) controller. As shown in fig. 1, a high-speed module such as a processor, a memory, a DMA controller, etc. is connected to a high-speed system bus, and a low-speed peripheral is connected to a low-speed local bus, which interacts with the system bus through a bus bridge. The DMA controller can read and write the memory and the low-speed peripheral through the bus, so that data transmission from the memory to the memory, from the memory to the peripheral and from the peripheral to the memory is realized. Each peripheral occupies a DMA channel, and initiates a transmission request to the DMA channel through a DMA request signal. The software firstly configures the peripheral and the DMA controller, then the peripheral initiates a DMA request to the DMA channel, then the DMA channel performs data transmission, and finally the DMA channel returns a DMA response to the peripheral.

Because the traditional DMA channels comprise a data processing module and a data buffer zone, the occupied areas of the two parts are larger, and the current SoC system comprises a large number of low-speed peripherals, the number of the needed DMA channels is large, and the occupied areas of the data processing modules and the data buffer zones of a plurality of DMA channels are also larger, so that the hardware cost required by the DMA controller is larger. Therefore, the number of channels of the conventional DMA controller is small, and each channel area is large, which is disadvantageous for the expansion of the number of channels. To meet the requirements, multiple sets of DMA controllers must be used, which undoubtedly increases chip area and power consumption, as well as software and hardware complexity.

Disclosure of Invention

The invention aims to provide a DMA control device, a DMA control method and a DMA control chip, which are used for solving the problem that the increase of the number of channels and the reduction of the channel area cannot be considered.

An embodiment of the present application provides a DMA control apparatus in a first aspect. The device comprises: a plurality of logic channels configured to receive transmission requests, respectively; a plurality of physical channels configured to perform data transmission based on the transmission requests, respectively; a channel selection module electrically coupled between the plurality of logical channels and the plurality of physical channels and configured to bind a selected logical channel of the plurality of logical channels to an idle physical channel of the plurality of physical channels; and a bus selection module electrically coupled between the plurality of physical channels and a bus and configured to cause a selected physical channel of the plurality of physical channels to access the bus to perform the data transfer.

In the method, the DMA channel is split into two parts, namely a logic channel and a physical channel, the area of the logic channel is small, and the number of the logic channels can be configured according to the number of the low-speed peripheral devices; the physical channels have large areas, and the number of the physical channels can be configured according to performance requirements.

In an implementation manner of the first aspect, the plurality of logical channels are each further configured to send a channel allocation request to the channel selection module based on the transmission request, and the channel selection module is configured to select one logical channel from the plurality of logical channels at a time based on the channel allocation request, and allocate an idle physical channel from the plurality of physical channels to the selected logical channel.

In an implementation manner of the first aspect, the plurality of physical channels are each further configured to send a bus read-write request to the bus selection module based on the transmission request, and the bus selection module is configured to select one physical channel among the plurality of physical channels at a time based on the bus read-write request to allow the selected physical channel to perform data reading or data writing with respect to the bus.

In one implementation of the first aspect, the number of the plurality of logical channels and the number of the plurality of physical channels are set independently of each other.

In an implementation manner of the first aspect, the apparatus further includes: a bus interface module electrically coupled between the bus selection module and the bus and configured to electrically couple the selected physical channel to the bus via a bus read interface or a bus write interface.

In an implementation manner of the first aspect, the channel selection module includes: a channel arbiter configured to allocate the free physical channel to at least one logical channel of the plurality of logical channels according to a first allocation principle in response to a channel allocation request initiated by the at least one logical channel, the first allocation principle comprising a polling or priority principle; and a channel multiplexer configured to electrically couple a selected logical channel of the at least one logical channel to the free physical channel.

In one implementation manner of the first aspect, the bus selection module includes: a bus arbiter configured to grant access to the bus by a selected physical channel in accordance with a second allocation principle in response to a bus read-write request initiated by a bonded physical channel of the plurality of physical channels, the second allocation principle comprising a polling or priority principle; and a bus multiplexer configured to electrically couple the selected physical channel of grant to the bus.

In one implementation of the first aspect, the plurality of logical channels each include a first configuration register, a first control module, and a DMA request interface; the first configuration register comprises a configuration unit for channel enabling reset, binding state and priority, descriptor address, transmission command and interrupt state; the first control module comprises a DMA transmission progress control unit and a first DMA error processing unit.

In the implementation mode, the logic channel removes the data transmission function and does not directly access the bus interface module any more; the bus interface module is converted to be accessed by a smaller number of physical channels, thereby reducing the size of the bus arbiter and bus multiplexer.

In an implementation manner of the first aspect, each of the plurality of physical channels includes a second configuration register, a second control module, a data buffer, a data processing module, and a bus request interface; the second configuration register comprises a configuration unit for channel enabling reset, binding state, descriptor address and data transmission parameters; the second control module comprises a descriptor and data transmission control unit and a second DMA error processing unit; the data buffer is configured to temporarily store data; the data processing module is configured to perform data packing and unpacking operations; the bus request interface is configured to generate bus read-write requests for physical channels.

In an implementation manner of the first aspect, the plurality of physical channels are respectively further configured to: and initiating a channel release for the selected physical channel to enter an idle state in response to the selected physical channel interacting with the bus to complete the data transfer.

In an implementation manner of the first aspect, the plurality of logic channels are respectively further configured to: in response to the selected physical channel interacting with the bus to complete the data transfer, the selected logical channel again receives another transfer request.

In an implementation manner of the first aspect, the bus interface module is configured to: and caching the read-write request information, the read-write data information and the read-write response information through the data buffer.

In an implementation manner of the first aspect, the channel selection module is configured to: binding the selected logical channel to the idle physical channel through dynamic binding or static binding, wherein the dynamic binding refers to applying and distributing corresponding physical channels according to the received transmission request, the static binding refers to binding a certain physical channel to a certain logical channel through a software register, and the transmission request received on the logical channel is immediately executed through the static bound physical channel.

In the implementation mode, through dynamic binding and static binding, the requirements of channel number increase and channel area reduction are considered, and meanwhile, the data transmission occasion with higher real-time requirement is also considered.

A second aspect of the embodiments of the present application provides a DMA control method. The method comprises the following steps: receiving, by the logical channel, a DMA request; initiating a channel allocation request to a channel selection module by the logic channel to apply for a physical channel; binding, by the channel selection module, the physical channel with the logical channel that initiated the channel allocation request; initiating a bus read-write request to a bus selection module by the bound physical channel to access a bus; and authorizing, by the bus selection module, access to the bus for the physical channel that initiated the bus read-write request, such that the authorized physical channel performs a data transfer based on the DMA request.

A third aspect of embodiments of the present application provides a chip. The chip comprises a DMA control device as described above.

In the DMA control device, the DMA control method and the DMA control chip, the area of the logic channel is reduced, the number of the logic channels can be configured according to the number of the low-speed peripherals, the physical channels are related to the performance, and the number of the logic channels can be configured according to the performance requirement. The number of the two components is not in constraint relation, and the two components can be flexibly configured to adapt to the system requirements of high number of low-speed peripherals and high performance requirements, and meanwhile, the effects of reducing the chip area and the power consumption and reducing the complexity of software and hardware are achieved. The logic channel removes the data transmission function, and does not directly access the bus interface module any more, and the bus interface module is converted into the physical channels with less quantity for access, so that the scale of the bus arbiter and the bus multiplexer is reduced. Through dynamic binding and static binding, the requirements of channel quantity increase and channel area reduction are considered, and meanwhile, the data transmission occasion with higher real-time requirement is also considered.

Drawings

Fig. 1 shows a diagram of the interconnection structure between DMA and peripheral in a SoC system.

Fig. 2 is a schematic structural diagram of a DMA control device according to an embodiment of the present application.

Fig. 3 shows a control structure diagram of the DMA control apparatus according to the embodiment of the present application.

Fig. 4 is a schematic diagram of channel splitting principle of a DMA control device according to an embodiment of the present application.

Fig. 5 is a diagram showing a channel selection module of a DMA control apparatus according to an embodiment of the present application.

Fig. 6 is a diagram showing a bus selection module structure of the DMA control apparatus according to the embodiment of the present application based on a read operation.

Fig. 7 is a diagram showing a bus selection module based on a write operation of the DMA control apparatus according to the embodiment of the present application.

Fig. 8 shows a flowchart of the DMA control apparatus according to the embodiment of the present application.

Fig. 9 is a timing chart showing the operation of the DMA control apparatus according to the embodiment of the present application.

Fig. 10 is a schematic flow chart of a DMA control method according to an embodiment of the present application.

Fig. 11 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that, the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The DMA channel may include configuration registers, DMA request interfaces, control modules, data processing modules, data buffers, bus request interfaces, and the like. The configuration registers include descriptor addresses, transfer commands, interrupt status, data transfer parameters. The DMA request interface is for processing a peripheral DMA request. The control module is used for descriptor and data transmission control and DMA error processing. The data processing module performs format conversion according to the bus data format and the data width of the internal buffer area, and reads and writes the data buffer area. The data buffer is responsible for temporarily storing source address data returned by the bus. The bus request interface is responsible for generating channel bus read-write requests.

The data transfer process of the DMA channel can be divided into two phases, instruction fetch and data transfer. The instruction acquisition process is as follows: reading the descriptor from the memory, and obtaining a source address, a destination address, a data length and a transmission mode of data transmission from the descriptor; the DMA channel then updates the internal registers and control module to initiate the data transfer process. The data transmission process is as follows: the DMA channel reads data from the source address in a specified transmission mode, and the data is temporarily stored in a data buffer area after being processed by the data processing module; then the data is output from the data buffer area, and after being processed by the data processing module, the data is written into the destination address in a designated transmission mode; if there are more descriptors to process, the above process is repeated.

In the DMA control apparatus of the present application, a DMA channel is split into two parts, namely a logical channel and a physical channel, which indirectly interact through a channel arbiter and a channel multiplexer. The logical channel is responsible for receiving the low-speed peripheral transfer request and the software transfer request and applying for allocation of the physical channel to the channel arbiter after the transfer request is valid. After being authorized, the physical channel is bound to the logical channel, and the physical channel begins to perform data transfer. The physical channel initiates a read-write request to the bus arbiter and interacts with the bus interface module to complete data transmission. The physical channel then initiates a channel release and enters an idle state. If the low-speed peripheral or software has a transmission requirement, the above process is repeated. If a plurality of logic channels initiate transmission requests at the same time, the channel arbiter allocates physical channels in sequence according to the allocation principle. If multiple physical channels initiate bus read-write requests at the same time, the bus arbiter grants the physical channels access to the bus interface module in sequence according to the allocation principle.

The terms logical channel, physical channel in this application are not meant to be exclusive of logical and physical channels in the terminology sense. In the prior art, the logic channel and the physical channel can respectively respond to the moving request of the software scheduling and the moving request of the internal engine, and the two terms of logic and physical are used for distinguishing the initiating source of the moving request or distinguishing whether the software scheduling participates. In addition, in the prior art, both the logical channel and the physical channel are complete DMA channels, that is, all include configuration registers, DMA request interfaces, control modules, data processing modules, data buffers, and bus request interfaces. In contrast, in the present application, the complete DMA channel is split into a logical channel and a physical channel, which respectively include part of the functional modules of the original DMA channel, and the specific structure of the two will be described below.

The following describes the technical solutions in the embodiments of the present application in detail with reference to the drawings in the embodiments of the present application.

Fig. 2 is a schematic structural diagram of a DMA control device according to an embodiment of the present application. As shown in fig. 2, the present embodiment provides a DMA control apparatus 2 including: a plurality of logical channels 21, a channel selection module 22, a plurality of physical channels 23, and a bus selection module 24.

The plurality of logical channels 21 are each configured to receive a transmission request. In some embodiments, the transfer request includes a low speed peripheral transfer request and a software transfer request.

In some embodiments, a portion of the logical channels are used for dynamic binding, where the portion of the logical channels are configured to receive a transmission request for flexible binding with the physical channels. In addition, the other part of logic channels are used for static binding, and a certain logic channel and a certain physical channel are required to be bound in advance mainly aiming at the data transmission request with higher real-time requirements so as to execute the data transmission request at any time.

The channel selection module 22 is electrically coupled between the plurality of logical channels and the plurality of physical channels and is configured to bind a selected logical channel of the plurality of logical channels to an idle physical channel of the plurality of physical channels.

The plurality of physical channels 23 are each configured to perform data transmission based on the transmission request.

The bus selection module 24 is electrically coupled between the plurality of physical channels and a bus and is configured to cause a selected physical channel of the plurality of physical channels to access the bus to perform the data transfer.

In an embodiment, the plurality of logical channels 21 are each further configured to send a channel allocation request to the channel selection module 22 based on the transmission request. The channel selection module 22 is configured to select one logical channel among the plurality of logical channels 21 at a time based on the channel allocation request, and allocate an empty physical channel among the plurality of physical channels 23 to the selected logical channel.

In an embodiment, the plurality of physical channels 23 are each further configured to send a bus read-write request to the bus selection module 24 based on the transfer request. The bus selection module 24 is configured to select one of the plurality of physical channels 23 at a time based on the bus read-write request to allow the selected physical channel to perform data reading or data writing with respect to the bus.

In one embodiment, the number of the plurality of logical channels 21 and the number of the plurality of physical channels 23 are set independently of each other.

According to the embodiment of the application, the number of the logic channels can be configured according to the number of the low-speed peripheral devices by arranging the logic channels and the physical channels respectively, so that the area of the logic channels is reduced, the physical channels are related to the performance, and the number of the physical channels can be configured according to the performance requirement. In this way, the system requirements of high number of low-speed peripherals and high performance requirements are met, and meanwhile, the effects of reducing the chip area and the power consumption and reducing the complexity of software and hardware are achieved. In addition, the data transmission function is removed from the logic channels, the buses are not accessed any more, and the buses are accessed by a small number of physical channels, so that the size of the bus arbiter and the bus multiplexer is reduced. In addition, through dynamic binding and static binding, the requirements of channel quantity increase and channel area reduction are considered, and meanwhile, the data transmission occasion with higher real-time requirement is also considered.

Fig. 3 shows a control structure diagram of the DMA control apparatus according to the embodiment of the present application. In one embodiment, as shown in fig. 3, the DMA control apparatus further comprises a bus interface module 25. The bus interface module 25 is electrically coupled between the bus selection module 24 and the bus and is configured to electrically couple the selected physical channel to the bus via a bus read interface or a bus write interface.

In one embodiment, the bus interface module 25 is configured to buffer read/write request information, read/write data information, and read/write response information through a data buffer. Specifically, the bus interface module 25 interfaces with a plurality of physical channels on one side and a system bus on one side for accessing low-speed peripherals and memory. The bus interface module 25 internally uses a data buffer FIFO (First In First Out, first-in first-out) to buffer read-write request information, read-write data information, and read-write response information. The data is firstly read into a data FIFO from a source address to the inside of the bus interface module, then the data is temporarily stored into a physical channel data buffer area, then the data is output from the buffer area to the data FIFO from the inside of the bus interface module, and finally the data is transmitted to a destination address.

In some embodiments, the channel selection module 22 includes a channel arbiter 221 and a channel multiplexer 222.

The channel arbiter 221 is configured to allocate the free physical channel to at least one logical channel of the plurality of logical channels 21 according to a first allocation principle in response to a channel allocation request initiated by the at least one logical channel, the first allocation principle comprising a polling or priority principle.

The channel multiplexer 222 is configured to electrically couple a selected logical channel of the at least one logical channel to the free physical channel.

In the embodiment of the present application, the channel arbiter 221 is responsible for allocating physical channels to logical channels according to the logical channel request information, and the allocation principle may be according to polling or priority. The channel arbiter 221 selects one from among a plurality of logical channel requests, selects one from among a plurality of free physical channels, and binds the two. The particular physical channel to which the logical channel is bound is determined by the logical channel priority and the hardware. When there is no free physical channel, the channel arbiter 221 stops the allocation work.

Therefore, the channel arbiter 221 and the channel multiplexer 222 separate the plurality of logic channels 21 from the plurality of physical channels 23, the number of the two channels is not dependent any more, the number of the logic channels can be configured according to the number of the low-speed peripherals, the number of the physical channels can be configured according to the performance requirement, and therefore the chip area and the performance can be ensured.

With continued reference to FIG. 3, in some embodiments, the bus selection module 24 includes a bus arbiter 241 and a bus multiplexer 242. The operation request may include a bus read-write request.

The bus arbiter 241 is configured to grant access to the bus to the selected physical channel in accordance with a second allocation principle, including a polling or priority principle, in response to a bus read-write request initiated by a bound physical channel of the plurality of physical channels.

The bus multiplexer 242 is configured to electrically couple the selected physical channels of grant to the bus.

In the embodiment of the application, the logical channel descriptor address is sent to the physical channel in the channel binding stage, and the physical channel reads-analyzes-writes back the descriptor, so that the realization mode of multiplexing the transmission request information from all the logical channels is avoided, and the size of the channel multiplexer is reduced. Where logical channel descriptor addresses may be aligned to larger address boundaries to reduce descriptor address width. The transmission request information of the logic channel includes a data transmission source address, a destination address, a data length, a transmission mode, and a total signal bit width is larger.

Furthermore, in an embodiment, the plurality of physical channels are each further configured to: and initiating a channel release for the selected physical channel to enter an idle state in response to the selected physical channel interacting with the bus to complete the data transfer. Additionally, in an embodiment, the plurality of logic channels are each further configured to: in response to the selected physical channel interacting with the bus to complete the data transfer, the selected logical channel again receives another transfer request.

Fig. 4 is a schematic diagram of channel splitting principle of a DMA control device according to an embodiment of the present application. As shown in fig. 4, in one embodiment, the plurality of logic channels 21 includes a first configuration register 211, a DMA request interface 212, and a first control module 213.

The first configuration register 211 comprises configuration elements of channel enable reset, binding state and priority, descriptor address, transfer command and interrupt state.

Therefore, compared with the traditional DMA channel, the logic channel removes the parameter register of data transmission, and further does not access the bus interface module; the bus interface module translates to access by a fewer number of physical channels, which reduces the size of the bus arbiter and bus multiplexer. The parameter registers of the data transmission comprise in particular a data source address, a data destination address, a data length, a data transfer mode.

The first control module 213 includes a DMA transfer progress control unit and a first DMA error processing unit. Thus, the first control module of the present application removes descriptors and data transfer control compared to conventional DMA channels.

With continued reference to fig. 4, in one embodiment, the physical channel 23 includes a second configuration register 231, a second control module 232, a data processing module 233, a data buffer 234, and a bus request interface 235.

The second configuration register 231 includes configuration units of channel enable reset, binding state, descriptor address, and data transfer parameters.

Specifically, the configuration unit of the data transmission parameter refers to a parameter register of data transmission, and specifically includes a data source address, a data destination address, a data length and a data transmission mode; the second configuration register eliminates the transfer command, priority, and interrupt status registers compared to conventional DMA channels.

The second control module 232 includes a descriptor and data transfer control unit and a second DMA error handling unit. Thus, compared with the traditional DMA channel, the second control module removes the DMA transmission progress control.

The data buffer 234 is configured to temporarily store data. Specifically, a bus request interface of a physical channel initiates a read request, and after data return, the read request is processed by a data processing module and stored in a data buffer area; then, the data is output from the data buffer area, processed by the data processing module and written into the destination address through the bus; the data width of the data buffer may be different from the data width of the read-write request, and the format conversion work is responsible for the data processing module.

The data processing module 233 is configured to perform data packing and unpacking operations. Specifically, the data packaging is responsible for converting the data returned by the bus according to the bus format read by the data and the data width of the data buffer area, and storing the data into the internal buffer area in a continuous byte stream form; the data unpacking is in charge of reading data from the internal buffer area and performing format conversion according to the data width of the internal buffer area and the bus format of data output.

The bus request interface 235 is configured to generate an operation request for a physical channel, which is sent to the bus interface module via the bus selection module.

Thus, the traditional DMA channel is split into two parts, namely a logical channel and a physical channel: the logic channel is responsible for processing DMA requests, DMA transmission progress control and DMA error processing, and the physical channel is responsible for descriptor and data transmission control, data processing and data temporary storage and DMA error processing; the former has small area and can be configured according to the number of the low-speed peripheral devices; the latter is large and its number can be configured according to performance requirements.

Fig. 5 is a diagram showing a channel selection module of a DMA control apparatus according to an embodiment of the present application. As shown in fig. 5, the input signal includes m logical channel request information and n physical channel idle state signals, and the output signal includes m logical channel grant signals, n physical channel grant signals, a logical channel index signal and a physical channel index signal. The logical channel request information here includes a channel binding request signal, a peripheral request type, and a descriptor address.

Fig. 6 is a diagram showing a bus selection module structure of the DMA control apparatus according to the embodiment of the present application based on a read operation. As shown in fig. 6, for a read request, the bus arbiter selects one of the plurality of physical channel read request messages, generates a select signal for the bus multiplexer, and causes it to access the bus read interface. The physical channel read request information comprises a read request, a read address and a read mode.

Fig. 7 is a diagram showing a bus selection module based on a write operation of the DMA control apparatus according to the embodiment of the present application. As shown in fig. 7, for a write request, the bus arbiter selects one of the plurality of physical channel write request information, generates a selection signal of the bus multiplexer, and makes it access the bus write interface. The physical channel write request information comprises a write request, a write address and a write mode.

Fig. 8 shows a flowchart of the DMA control apparatus according to the embodiment of the present application. The DMA control apparatus specifically refers to a DMA controller having the apparatus structure described in the present application. As shown in fig. 8, the operation flow of the DMA control apparatus is as follows.

In step S81, the software configures the low-speed peripheral and the DMA controller.

In step S82, the low speed peripheral or software initiates a DMA request to the DMA controller.

In step S83, the logical channel applies for the physical channel to the channel arbiter.

In step S84, the logical channel is bound to the physical channel.

In step S85, the physical channel performs data transmission.

In step S86, after the data transmission is completed, the physical channel initiates a channel release, and enters an idle state.

In step S87, it is determined whether the low-speed peripheral or the software has a data transmission requirement, i.e. a DMA request, if yes, returning to step S82; if not, finishing the DMA control process.

Fig. 9 is a timing chart showing the operation of the DMA control apparatus according to the embodiment of the present application. As shown in fig. 9, an operational timing diagram is shown, taking 4 logical channels and 2 physical channels as examples.

The 4 logical channels include: LCH_REQ [0] -logic channel 0, LCH_REQ [1] -logic channel 1, LCH_REQ [2] -logic channel 2, LCH_REQ [3] -logic channel 3.

The grant signals corresponding to the 4 logic channels include: LCH_GNT [0] -logic channel 0 grant signal, LCH_GNT [1] -logic channel 1 grant signal, LCH_GNT [2] -logic channel 2 grant signal, LCH_GNT [3] -logic channel 3 grant signal.

The logical channel index is lch_idx_gnt.

The 2 physical channels include PCH_AVAIL [0] -physical channel 0, PCH_AVAIL [1] -physical channel 1.

The grant signals corresponding to the 2 physical channels comprise PCH_GNT0-physical channel 0 grant signals and PCH_GNT1-physical channel 1 grant signals. The physical channel index is pch_idx_gnt.

At different times, the states of the various channels are as follows:

t0: all logic channels do not initiate application, and all physical channels are in idle state;

t1: initiating an application by a logic channel 0;

t2: physical lane 0 is assigned to logical lane 0 and is no longer in an idle state; simultaneously, a logical channel 0 and a physical channel 0 authorization signal become valid, and the indexes of the logical channel and the physical channel are respectively 0 and 0;

t3: initiating an application by a logic channel 1;

t4: physical channel 1 is assigned to logical channel 1 and is no longer in an idle state; simultaneously, the authorization signals of the logic channel 1 and the physical channel 1 become effective, and the indexes of the logic channel and the physical channel are respectively 1 and 1; all physical channels are in busy state;

t5: the logic channel 2 initiates application, at the moment, no idle physical channel exists, and the application signal is kept valid all the time;

t6: the idle physical channel still does not exist, and the logic channel 2 application signal is always kept valid;

t7: the logic channel 3 initiates application, at the moment, no idle physical channel exists, and the application signal is kept valid all the time;

t10: physical channel 0 enters an idle state;

t11: physical channel 0 is allocated to logical channel 2 and is no longer in an idle state; simultaneously, the authorization signals of the logic channel 2 and the physical channel 0 become valid, and the indexes of the logic channel and the physical channel are respectively 2 and 0; all physical channels are in busy state;

t12: the physical channel 1 enters an idle state;

t13: physical channel 1 is allocated to logical channel 3 and is no longer in an idle state; simultaneously, the authorization signals of the logic channel 3 and the physical channel 1 become effective, and the indexes of the logic channel and the physical channel are respectively 3 and 1; all physical channels are in busy state;

t16: physical channel 0 enters an idle state;

t18: the physical channel 1 enters an idle state;

t19: all logical channels do not initiate applications and all physical channels are in idle state.

In some embodiments, when the physical channels are fewer, part of the logical channels cannot be applied to the physical channels immediately, and the data transmission request cannot be executed immediately, so that instantaneity is affected. Therefore, in addition to dynamic binding, static binding can also be realized.

In an embodiment, the channel selection module is configured to bind the selected logical channel to the free physical channel by dynamic binding or static binding. The dynamic binding refers to applying and allocating corresponding physical channels according to the received transmission request. The static binding refers to binding a certain physical channel to a certain logic channel through a software register, and a transmission request received on the logic channel is immediately executed through the static bound physical channel.

Further, the physical channels and logical channels that participate in the static binding are no longer involved in the hardware dynamic binding. The static binding logic channel does not need to apply for a physical channel to the channel arbiter, and the data transmission request can be immediately executed by the static binding physical channel, so that the situation is suitable for the data transmission occasion with higher real-time requirement.

Fig. 10 is a schematic flow chart of a DMA control method according to an embodiment of the present application. As shown in fig. 10, the DMA control method provided in this embodiment specifically includes the following steps S11 to S15.

In step S11, a DMA request is received by the logical channel.

In step S12, a channel allocation request is initiated by the logical channel to the channel selection module to apply for a physical channel.

In step S13, the physical channel is bound by the channel selection module to the logical channel that originated the channel allocation request.

In step S14, a bus read-write request is initiated by the bound physical channel to the bus selection module to access the bus.

In step S15, the bus selection module grants access to the bus for the physical channel that initiated the bus read-write request, such that the granted physical channel performs a data transfer based on the DMA request.

The protection scope of the DMA control method according to the embodiments of the present application is not limited to the execution sequence of the steps listed in the embodiments, and all the schemes implemented by adding or removing steps and replacing steps according to the principles of the present application in the prior art are included in the protection scope of the present application.

The DMA control device according to the embodiment of the present application may implement the DMA control method according to the present application, but the implementation device of the DMA control method according to the present application includes, but is not limited to, the structure of the DMA control device listed in the present embodiment, and all structural modifications and substitutions made according to the principles of the present application in the prior art are included in the protection scope of the present application.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus or method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules/units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.

The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the purposes of the embodiments of the present application. For example, functional modules/units in various embodiments of the present application may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.

Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Fig. 11 is a schematic structural diagram of a chip according to an embodiment of the present application. As shown in fig. 11, the chip according to the present embodiment includes the DMA control apparatus described above.

In the chip, a plurality of logic channels are respectively configured to receive transmission requests; the plurality of physical channels are respectively configured to perform data transmission based on the transmission request; a channel selection module is electrically coupled between the plurality of logical channels and the plurality of physical channels and is configured to bind a selected logical channel of the plurality of logical channels to an idle physical channel of the plurality of physical channels; a bus selection module is electrically coupled between the plurality of physical channels and the bus and is configured to cause a selected physical channel of the plurality of physical channels to access the bus to perform the data transfer.

The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.

The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims

1. A DMA control apparatus, characterized by comprising:

a plurality of logic channels configured to receive transmission requests, respectively;

a plurality of physical channels configured to perform data transmission based on the transmission requests, respectively;

a channel selection module electrically coupled between the plurality of logical channels and the plurality of physical channels and configured to bind a selected logical channel of the plurality of logical channels to an idle physical channel of the plurality of physical channels; and

a bus selection module is electrically coupled between the plurality of physical channels and the bus and is configured to cause a selected physical channel of the plurality of physical channels to access the bus to perform the data transfer.

2. The apparatus of claim 1, wherein each of the plurality of logical channels is further configured to send a channel allocation request to the channel selection module based on the transmission request,

the channel selection module is configured to select one logical channel from the plurality of logical channels at a time based on the channel allocation request, and allocate an idle physical channel from the plurality of physical channels to the selected logical channel.

3. The apparatus of claim 1, wherein the plurality of physical channels are each further configured to send a bus read-write request to the bus selection module based on the transfer request,

the bus selection module is configured to select one of the plurality of physical channels at a time based on the bus read-write request to allow the selected physical channel to perform a data read or a data write with respect to the bus.

4. The apparatus of claim 1, wherein a number of the plurality of logical channels and a number of the plurality of physical channels are set independently of each other.

5. The apparatus as recited in claim 1, further comprising:

a bus interface module electrically coupled between the bus selection module and the bus and configured to electrically couple the selected physical channel to the bus via a bus read interface or a bus write interface.

6. The apparatus of claim 1, wherein the channel selection module comprises:

a channel arbiter configured to allocate the free physical channel to at least one logical channel of the plurality of logical channels according to a first allocation principle in response to a channel allocation request initiated by the at least one logical channel, the first allocation principle comprising a polling or priority principle; and

a channel multiplexer configured to electrically couple a selected logical channel of the at least one logical channel to the free physical channel.

7. The apparatus of claim 1, wherein the bus selection module comprises:

a bus arbiter configured to grant access to the bus by a selected physical channel in accordance with a second allocation principle in response to a bus read-write request initiated by a bonded physical channel of the plurality of physical channels, the second allocation principle comprising a polling or priority principle; and

a bus multiplexer configured to electrically couple the selected physical channel of grant to the bus.

8. The apparatus of claim 1, wherein the plurality of logical channels each comprise a first configuration register, a first control module, and a DMA request interface;

the first configuration register comprises a configuration unit for channel enabling reset, binding state and priority, descriptor address, transmission command and interrupt state;

the first control module comprises a DMA transmission progress control unit and a first DMA error processing unit.

9. The apparatus of claim 1, wherein the plurality of physical channels each comprise a second configuration register, a second control module, a data buffer, a data processing module, and a bus request interface;

the second configuration register comprises a configuration unit for channel enabling reset, binding state, descriptor address and data transmission parameters;

the second control module comprises a descriptor and data transmission control unit and a second DMA error processing unit;

the data buffer is configured to temporarily store data;

the data processing module is configured to perform data packing and unpacking operations;

the bus request interface is configured to generate bus read-write requests for physical channels.

10. The apparatus of claim 1, wherein the plurality of physical channels are each further configured to:

and initiating a channel release for the selected physical channel to enter an idle state in response to the selected physical channel interacting with the bus to complete the data transfer.

11. The apparatus of claim 1, wherein the plurality of logical channels are each further configured to:

in response to the selected physical channel interacting with the bus to complete the data transfer, the selected logical channel again receives another transfer request.

12. The apparatus of claim 5, wherein the bus interface module is configured to:

and caching the read-write request information, the read-write data information and the read-write response information through the data buffer.

13. The apparatus of claim 1, wherein the channel selection module is configured to:

binding the selected logical channel to the idle physical channel by dynamic binding or static binding;

the dynamic binding refers to applying and distributing corresponding physical channels according to the received transmission request;

the static binding refers to binding a certain physical channel to a certain logic channel through a software register, and a transmission request received on the logic channel is immediately executed through the static bound physical channel.

14. A DMA control method, characterized by comprising:

receiving, by the logical channel, a DMA request;

initiating a channel allocation request to a channel selection module by the logic channel to apply for a physical channel;

binding, by the channel selection module, the physical channel with the logical channel that initiated the channel allocation request;

initiating a bus read-write request to a bus selection module by the bound physical channel to access a bus; and

and authorizing, by the bus selection module, access to the bus for the physical channel that initiated the bus read-write request, such that the authorized physical channel performs a data transfer based on the DMA request.

15. A chip, comprising: the DMA control apparatus according to any one of claims 1 to 13.