CN102724035B - Encryption and decryption method for encrypt card - Google Patents
Encryption and decryption method for encrypt card Download PDFInfo
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- CN102724035B CN102724035B CN201210203893.0A CN201210203893A CN102724035B CN 102724035 B CN102724035 B CN 102724035B CN 201210203893 A CN201210203893 A CN 201210203893A CN 102724035 B CN102724035 B CN 102724035B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000007717 exclusion Effects 0.000 claims abstract description 7
- 238000012545 processing Methods 0.000 claims abstract description 7
- 230000003139 buffering effect Effects 0.000 claims description 16
- 239000000872 buffer Substances 0.000 claims description 9
- 238000012546 transfer Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Abstract
The invention provides an encryption and a decryption method for an encrypt card. The encrypt card comprises encryption chips, DSP (digital signal sensor) processors, interface control circuits and a PCI (programmable communication interface) circuit; the number of the DSP processors, the number of the interface control circuits and the number of the encryption chips are equal and are at least two, one DSP processor controls and is connected with one encryption chip by one corresponding interface control circuit; and at least two DSP processors are connected with the PCI circuit to achieve the data transmission of the encrypt card between computers. A non-preemption interruption mutual exclusion mechanism is adopted to avoid interruption emption based on interruption priority, reduce the phenomenon of packet loss and guarantee the correctness and order of the data packet processing procedure.
Description
Technical field
The present invention relates to electronic information security field, be specifically related to a kind of encipher-decipher method of encrypted card.
Background technology
Along with developing rapidly and extensive use of information and network technology, bank, oil, the business datum of the pillar trade such as electric power has extensively adopted all kinds of computer equipment to carry out communication, due to importance and the particularity of industry, the encryption safe transmission of data must be considered, so, the server apparatus exploitation be encrypted in industry extensively is carried out, server apparatus can data from the data expressly becoming encryption, destination is transferred data to again by the network equipment, in the main flow encryption server equipment of information security industry, bear pci interface encrypted card integrated in the mainly equipment of data encryption task, the encryption chip that the integrated national Password Management office of encrypted card is authorized, there is constrained input unit, when the driver of encrypted card transfers data to input unit, these data of encrypted card process, put it into output unit, give the driver of encrypted card, data after encryption are given the upper application software needing cryptographic services by driver again.
In the encrypted card being integrated with identical performance deciphering chip, the efficient logical processing method that the multiple deciphering chip of design con-trol works simultaneously, and the high-efficiency appliance driver of encrypted card is called in design, thus farthest utilizing the handling property of deciphering chip, the cost performance improving encrypted card is on the whole just very important.
In prior art, encrypted card is form data packet group being made into applicable encryption chip process, encryption chip control circuit is sent into by driver, then after waiting for encryption chip process, data after process are delivered to driver again through control circuit, then is given the user program called on upper strata by driver.Publication number is the design that the Chinese patent of CN1996321A discloses a kind of encrypted card, and this design employs 2 pieces of dsp chips and 1 block encryption chip carries out interaction process.Exchanges data between DSP, between DSP and encryption chip devises extra dual port RAM and does data buffering, on data flow, 1 piece of DSP computing doing master control terminates, and is encrypted the computing of chip, send into another 1 piece of DSP after computing again, finally give user by PCI-E interface.Wait for when encryption chip process, the stand-by period, the continuous wait pattern of " take-wait pending-abandon taking " wasted chip section divisional processing performance so this greatly more than the speed of encrypted card deal with data always.
Summary of the invention
The encipher-decipher method of a kind of encrypted card provided by the invention, described encrypted card comprises encryption chip, dsp processor, interface control circuit and one piece of P CI interface circuit;
The quantity of described dsp processor, interface control circuit and encryption chip is equal and be at least two, and one piece of dsp processor is by one piece of corresponding interface control circuit control connection one block encryption chip;
The dsp processor of described at least two connects described pci interface circuit, realize described encrypted card and described encrypted card transfer of data between the computers;
Described encipher-decipher method comprises:
Step S1, receives the dispatch command that user side comprises packet, and when described dispatch command is write operation, what perform step S2 writes thread process; When described dispatch command is read operation, what perform step S3 reads thread process;
Step S2, write thread and search idle encryption chip, the data of write operation are put into described idle encryption chip, after described idle encryption chip processes the packet of described user side, described packet is write encryption and decryption queue by interrupt routine by described dsp processor, and does mark to be read to described packet;
Step S3, reads thread and continues to check described encryption and decryption queue, read and be labeled as packet to be read and send into user side.
In first optimal technical scheme provided by the invention: the dsp processor of described at least two interrupts mutual exclusion each other, the same time only has an interruption carrying out.
2, in the second optimal technical scheme provided by the invention: described dsp processor has been provided with packet and will have sent or will send 2 flag bits without packet, and the described flag bit that interrupt circuit analyzes each dsp processor carries out interrupt processing to the dsp processor having packet to send;
When there being two or more dsp processor to have packet to send simultaneously, a random selected dsp processor sends packet, and described not have selected dsp processor to block wait in row.
In 3rd optimal technical scheme provided by the invention: described encryption and decryption queue is provided with semaphore, have 100 memory locations, described in read thread or write after thread monopolizes described semaphore to carry out read-write operation to encryption and decryption queue.
In 4th optimal technical scheme provided by the invention: the quantity of described dsp processor, interface control circuit and encryption chip is 4;
Describedly read thread and to write thread be asynchronous parallel work.
In 5th optimal technical scheme provided by the invention: the internal memory of described computer and dsp processor are provided with 5 buffering areas in internal data store district, 5 buffering areas that described dsp processor is arranged in internal data store district are the shared buffer with corresponding described encryption chip, the size of described buffering area and the equal and opposite in direction of the maximum data packet of feeding encryption chip.
In 6th optimal technical scheme provided by the invention: described step S2 comprises:
Described step S2 comprises:
Step S201, writes after thread receives described packet, and searching whether available free encryption chip, is perform step S202; No, return, wait for that next time sends;
Step S202, sends into described packet in dsp processor corresponding to described idle encryption chip, searches the described the shared buffer whether dsp processor of described correspondence is available free, be, perform step S203; No, return, wait for that next time sends;
Step S203, described idle encryption chip processes described packet;
Step S204, triggers the interrupt routine of described dsp processor, and described interrupt routine searches the free time in described encryption and decryption queue;
Step S205, described in write the semaphore that thread occupies encryption and decryption queue, mark to be read is done in the queue of described packet write encryption and decryption, waits the thread that continues to read.
In 7th optimal technical scheme provided by the invention: the processing procedure of encryption chip to described packet idle described in described step 203 comprises:
Described dsp processor does untreated mark to described packet, described encrypted card inquires about the state of 5 described shared buffers at one's leisure by circular order, process there being the packet of untreated mark, processed mark is done to the packet after having processed, and covers the packet of described untreated mark with the packet of described processed mark.
In 8th optimal technical scheme provided by the invention: described step S3 comprises:
Whether step S301, search in encryption and decryption queue to have and be labeled as packet to be read, is, performs step S302, no, waits for;
Step S302, described in read the semaphore that thread occupies encryption and decryption queue, be labeled as packet to be read described in reading and send into user side.
The beneficial effect of the encipher-decipher method of a kind of encrypted card provided by the invention comprises:
1, the encipher-decipher method of a kind of encrypted card provided by the invention, reading thread and writing thread in encryption and decryption process separates asynchronous parallel operation, two thread independence continuous services, driver program is high, and effectively make use of the encryption and decryption performance that PCI encryption clamp carries encryption chip;
2, the data packet group after deciphering chip process is made into data packet queue, and keeps packet sequence number, reads for upper strata caller;
3, take to interrupt mutual exclusion mechanism.When calling 4 block encryption chip, the interruption avoided based on interrupt priority level is seized, and eliminates the loss disruption usually when interruption frequency is high, has stopped packet loss phenomenon, ensure that processing data packets is correctly orderly;
4, take CPU mutual exclusion mechanism, avoid when running on multi-CPU server platform, the possible a certain CPU caused due to multiple CPU hardware interrupt controller seizes the phenomenon that another CPU interrupts, and has stopped to seize the packet loss brought;
5, atom is taked to read and write mechanism, read and write two kinds is had to the operation of encryption and decryption queue, for encryption and decryption queue operation arranges a semaphore, any operation to queue just can operate after only obtaining semaphore, avoids reading and writing the data corruption simultaneously carrying out bringing;
6 and encryption chip carries out computing carries corresponding dsp processor primarily of plate and control separately, dsp processor completes that packet is sent into, read, arbitration work, saves computer resource.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of a kind of encrypted card provided by the invention;
Fig. 2 is the relation structure diagram between dsp processor provided by the invention and corresponding encryption chip;
Fig. 3 is the encipher-decipher method flow chart of a kind of encrypted card provided by the invention;
Fig. 4 is the embodiment operational flowchart reading thread provided by the invention;
Fig. 5 is the embodiment operational flowchart writing thread provided by the invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
Be illustrated in figure 1 the structural representation of the embodiment of a kind of encrypted card provided by the invention, as shown in Figure 1, this encrypted card comprises encryption chip, dsp processor, interface control circuit and one piece of pci interface circuit.The quantity of dsp processor, interface control circuit and encryption chip is equal but unrestricted, be at least two, one piece of dsp processor controls separately a block encryption chip, and the dsp processor of correspondence and encryption chip are connected communication by one piece of corresponding interface control circuit, dsp processor receives the packet from driver, sends into encryption chip process by interface control circuit.Dsp processor connects pci interface circuit, this pci interface circuit be realize encrypted card with the passage of transfer of data between the computers.
The quantity of what Fig. 1 of the present invention provided is dsp processor, interface control circuit and encryption chip is the situation of 4, dsp processor opens up 5 buffering areas of sharing with corresponding encryption chip in internal data store district, and the relational structure between dsp processor and corresponding encryption chip as shown in Figure 2.
As shown in Figure 3, as shown in Figure 3, this encryption process comprises the flow chart of steps of the embodiment of a kind of encryption process based on encrypted card provided by the invention:
Step S1, receives the dispatch command that user side comprises packet, and when this dispatch command is write operation, what perform step S2 writes thread process; When this dispatch command is read operation, what perform step S3 reads thread process.
Preferably, this reads thread and to write thread be asynchronous parallel work, 2 thread independence continuous services, and efficiency is high and effectively utilize the encryption and decryption performance of the encryption chip of PCI encrypted card.
Step S2, writes thread and searches idle encryption chip, the packet of write operation is put into this idle encryption chip, after encryption chip processes this packet, writes the data packet encryption and decryption queue by interrupt routine, and does mark to be read to this packet.
Step S3, reads thread and continues to check this encryption and decryption queue, read and be labeled as packet to be read and send into user side.
Preferably, encryption and decryption queue is provided with semaphore, before carrying out read-write operation to encryption and decryption queue, needs exclusive semaphore just can operate, if semaphore is taken by other operations, then in queue, blocks wait-semaphore be released.
Concrete, write thread receive from the packet of user operating process as shown in Figure 4, this is write thread and comprises:
Step S201, writes thread and receives from after the packet of user side, and searching whether available free encryption chip, is perform step S202; No, return, wait for that next time sends.
Step S202, sends the packet from user side into dsp processor corresponding to idle encryption chip, searches the shared buffer whether this dsp processor encryption chip corresponding with it be available free, be, perform step S203; No, return, wait for that next time sends.
The internal data store district of 64000 bytes is had in dsp processor, the CPU of encrypted card place computer can access this internal data store district by pci bus interface, open up between 5 buffer empties in the internal memory of computer, each buffer size equals the size of the maximum data packet sending into encryption chip, meanwhile, in dsp processor internal data store district, also open up 5 onesize buffering areas.
Step S203, this idle encryption chip processes this packet.
4 pieces of dsp processor independent operating work, every block dsp processor controls separately an encryption chip, receives the packet from driver, and send into encryption chip process, the packet after having processed returns dsp processor by encryption chip.
The packet that user side sends puts into a freebuf of 5 buffering areas, dsp processor can copy the buffering area in internal data store district in the mode of direct access memory to buffering area in the internal memory of data form computer automatically, and do untreated mark, the state of 5 buffering areas can be inquired about by circular order when encrypted card is idle, if there is the packet of untreated mark just to will begin in a minute process to this packet, processed mark is done after having processed, and the buffering area that the packet that the packet of processed mark is covered original untreated mark takies.Dsp processor does can write mark to buffering area after being read by reduced data bag, accordingly, arrive in the process of encryption chip process at packet slave driver, the state of 5 buffering areas that DSP and encryption chip are shared untreated, processed, can write between 3 states and change.
Step S204, trigger the interrupt routine of dsp processor, interrupt routine searches the free time in encryption and decryption queue.
Preferably, each dsp processor adopts and interrupts mutual exclusion mechanism.
1 interrupt line that PCI board takies shares to 4 dsp processors, the working condition of this circuit analysis each piece of dsp processor, there is packet to send to dsp processor definition and 2 flag bits will be sent without packet, if there is two or more dsp processor to have the packet that will process simultaneously, then the selected dsp processor of randomized arbitration sends packet, blocking in queue is in addition waited for, interrupts the interrupt signal serial on control line like this, can not clash.
Under multiprocessor architecture, each CPU respectively has an interrupt control unit, when some interruptions are occurent, likely occur that in multiprocessor, ongoing interruption is seized in the interruption of another CPU, causes packet loss phenomenon, if have interruption to occur so current, take non-preemption scheduling mechanism in invention, close interruption and seize, make to interrupt mutual exclusion, namely the same time only has an interruption to carry out, and stops packet loss phenomenon.
Step S205, occupies the semaphore of encryption and decryption queue, writes the data packet encryption and decryption queue, and does mark to be read to these data, waits the thread that continues to read.
Read the operating process of thread read data packet as shown in Figure 5, this is read thread and comprises:
Whether step S301, search in encryption and decryption queue to have and be labeled as packet to be read, is, performs step S302, no, waits for.
Step S302, occupies the semaphore of encryption and decryption queue, reads this and is labeled as packet to be read and sends into user side.
Although be described in detail example of the present invention with reference to the accompanying drawings above, be not limited only to this embodiment, various equivalent, the deformation process that those skilled in the art carries out according to this concrete technical scheme, also within protection scope of the present invention.
Claims (2)
1. an encipher-decipher method for encrypted card, is characterized in that, described encrypted card comprises encryption chip, dsp processor, interface control circuit and one piece of pci interface circuit;
The quantity of described dsp processor, interface control circuit and encryption chip is equal and be at least two, and one piece of dsp processor is by one piece of corresponding interface control circuit control connection one block encryption chip;
The dsp processor of described at least two connects described pci interface circuit, realize described encrypted card and described encrypted card transfer of data between the computers;
Described encipher-decipher method comprises:
Step S1, receives the dispatch command that user side comprises packet, and when described dispatch command is write operation, what perform step S2 writes thread process; When described dispatch command is read operation, what perform step S3 reads thread process;
Step S2, write thread and search idle encryption chip, the data of write operation are put into described idle encryption chip, after described idle encryption chip processes the packet of described user side, described packet is write encryption and decryption queue by interrupt routine by described dsp processor, and does mark to be read to described packet;
Step S3, reads thread and continues to check described encryption and decryption queue, read and be labeled as packet to be read and send into user side;
The internal memory of described computer and dsp processor are provided with 5 buffering areas in internal data store district, 5 buffering areas that described dsp processor is arranged in internal data store district are the shared buffer with corresponding described encryption chip, the size of described buffering area and the equal and opposite in direction of the maximum data packet of feeding encryption chip;
Described step S2 comprises:
Step S201, writes after thread receives described packet, and searching whether available free encryption chip, is perform step S202; No, return, wait for that next time sends;
Step S202, sends into described packet in dsp processor corresponding to described idle encryption chip, searches the described the shared buffer whether dsp processor of described correspondence is available free, be, perform step S203; No, return, wait for that next time sends;
Step S203, described idle encryption chip processes described packet;
Step S204, triggers the interrupt routine of described dsp processor, and described interrupt routine searches the free time in described encryption and decryption queue;
Step S205, described in write the semaphore that thread occupies encryption and decryption queue, mark to be read is done in the queue of described packet write encryption and decryption, waits the thread that continues to read;
Described step S3 comprises:
Whether step S301, search in encryption and decryption queue to have and be labeled as packet to be read, is, performs step S302, no, waits for;
Step S302, described in read the semaphore that thread occupies encryption and decryption queue, be labeled as packet to be read described in reading and send into user side;
The dsp processor of described at least two interrupts mutual exclusion each other, and the same time only has an interruption carrying out;
Described dsp processor is provided with packet and will sends or will send 2 flag bits without packet, and the described flag bit that interrupt circuit analyzes each dsp processor carries out interrupt processing to the dsp processor having packet to send;
When there being two or more dsp processor to have packet to send simultaneously, a random selected dsp processor sends packet, and described not have selected dsp processor to block wait in row;
The quantity of described dsp processor, interface control circuit and encryption chip is 4;
Describedly read thread and to write thread be asynchronous parallel work;
The processing procedure of encryption chip to described packet idle described in described step 203 comprises:
Described dsp processor does untreated mark to described packet, described encrypted card inquires about the state of 5 described shared buffers at one's leisure by circular order, process there being the packet of untreated mark, processed mark is done to the packet after having processed, and covers the packet of described untreated mark with the packet of described processed mark.
2. the encipher-decipher method of a kind of encrypted card as claimed in claim 1, is characterized in that, described encryption and decryption queue is provided with semaphore, has 100 memory locations, described in read thread or write after thread monopolizes described semaphore to carry out read-write operation to encryption and decryption queue.
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| CN201210203893.0A CN102724035B (en) | 2012-06-15 | 2012-06-15 | Encryption and decryption method for encrypt card |
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| CN201210203893.0A CN102724035B (en) | 2012-06-15 | 2012-06-15 | Encryption and decryption method for encrypt card |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107247625A (en) * | 2017-06-14 | 2017-10-13 | 湖南麒麟信安科技有限公司 | A kind of data encrypting and deciphering dispatching method verified based on many card redundancys |
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| CN103986571B (en) * | 2014-01-15 | 2018-04-20 | 上海新储集成电路有限公司 | A kind of smart card multi-core processor system and its method for defending differential power consumption analysis |
| CN105207816A (en) * | 2015-09-16 | 2015-12-30 | 国网智能电网研究院 | Software scheduling method for multi-buffer parallel encryption |
| CN106302699B (en) * | 2016-08-11 | 2019-12-27 | 广州慧睿思通信息科技有限公司 | Method for processing decryption tasks of PC (personal computer) ends of multiple decryptors |
| CN107220551B (en) * | 2017-04-21 | 2020-12-25 | 上海海加网络科技有限公司 | Multithreading group encryption and decryption scheduling method and system based on double-card verification |
| CN107256363B (en) * | 2017-06-13 | 2020-03-06 | 杭州华澜微电子股份有限公司 | High-speed encryption and decryption device composed of encryption and decryption module array |
| CN109766713B (en) * | 2018-12-15 | 2021-01-12 | 中国大唐集团科学技术研究院有限公司 | Method for realizing dynamic rapid desensitization of data based on proxy |
| CN109766268B (en) * | 2018-12-17 | 2019-10-25 | 南瑞集团有限公司 | A kind of sequence assembly instruction program verification method and system |
| CN112104650A (en) * | 2020-09-15 | 2020-12-18 | 南方电网科学研究院有限责任公司 | Protection system of server |
| CN114500052B (en) * | 2022-01-24 | 2023-12-19 | 南京南瑞信息通信科技有限公司 | Event-driven-based efficient data encryption forwarding method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101000584A (en) * | 2007-01-08 | 2007-07-18 | 熊江 | Fingerprint encipher hard disc |
| CN101290569A (en) * | 2008-05-06 | 2008-10-22 | 国网南京自动化研究院 | Method for parallel data processing adopting multi- password chip |
| CN101854353B (en) * | 2010-04-28 | 2013-01-16 | 国网电力科学研究院 | Multi-chip parallel encryption method based on FPGA |
| CN101924766A (en) * | 2010-08-20 | 2010-12-22 | 河南省电力公司 | Double-network communication method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107247625A (en) * | 2017-06-14 | 2017-10-13 | 湖南麒麟信安科技有限公司 | A kind of data encrypting and deciphering dispatching method verified based on many card redundancys |
| CN107247625B (en) * | 2017-06-14 | 2019-08-09 | 湖南麒麟信安科技有限公司 | A kind of data encrypting and deciphering dispatching method based on the verification of more card redundancies |
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