CN101375505A - 分频器电路 - Google Patents

分频器电路 Download PDF

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CN101375505A
CN101375505A CNA2007800034345A CN200780003434A CN101375505A CN 101375505 A CN101375505 A CN 101375505A CN A2007800034345 A CNA2007800034345 A CN A2007800034345A CN 200780003434 A CN200780003434 A CN 200780003434A CN 101375505 A CN101375505 A CN 101375505A
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clock signal
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罗宾·詹姆士·米勒
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Future Waves UK Ltd
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    • H—ELECTRICITY
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    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
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    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
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    • H03F3/45—Differential amplifiers
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    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
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    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
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    • H03K23/544—Ring counters, i.e. feedback shift register counters with a base which is an odd number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/372—Noise reduction and elimination in amplifier
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    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/489—A coil being added in the source circuit of a common source stage, e.g. as degeneration means
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    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
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Abstract

一种用于从输入时钟信号获取输出时钟信号的电路，所述输出时钟5具有所述输入时钟信号频率的1/N的频率，其中N是奇数。所述电路包括：以锁存器环而配置的多个锁存器，所述锁存器以连续对的形式而设置，每一对锁存器包括第一锁存器和第二锁存器，所述第一锁存器在所述输入时钟信号的上升沿或下降沿之一的时刻接通，而所述第二锁存器在所述输入时钟信号的上升沿或下降沿中另一个的时刻接通。RS触发器被耦合，以在其置位和复位输入端中的一端处接收来自在所述输入时钟信号的上升沿时接通的锁存器环的输出，而在其置位和复位输入端中的另一端处接收来自在所述输入时钟信号的下降沿时接通的锁存器环的输出。在所述RS触发器的输出端提供所述输出时钟信号。

Description

分频器电路
技术领域
本发明涉及一种分频器电路，具体但非必然地涉及一种基于johnson环结构的分频器电路。
背景技术
数字处理电路需要一个或更多个时钟信号而工作。时钟信号通常从由晶振提供的基础时钟信号中获得。例如，可通过对基础时钟信号进行适当量的分频而获得具有小于基础时钟信号频率的频率的时钟信号。在需要多个时钟信号的电路中，这可通过把一组分频器链接在一起而有效地实现。例如，如果基础频率是f0，则可以使基础时钟信号通过2分频电路并使该电路的输出通过另一个2分频电路，从而得到频率f0/2和f0/4。
图1示意性地示出了典型的基于johnson环的6分频电路。该电路包括由3个D型触发器组成的链。每一个触发器包括一对D型锁存器(图中未示出)，其中每一个对的第一成员接收待分频的时钟信号，而每一个对中的第二成员接收反相时钟信号。这个时钟控制设置致使每一个锁存器对中的第一成员在时钟脉冲的上升沿改变状态，而每一个对中的第二成员在下降沿改变状态，从而确保给定锁存器的输入在该锁存器被时钟控制时保持稳定状态。来自最后的触发器的反相输出反馈到第一锁存器作为D输入。这个设置导致由0和1组成的序列在时钟的控制下依次通过该链。该电路的输出由最后的触发器的Q或/Q来提供。
当需要获得作为基础时钟信号频率的奇数分频的时钟信号时，即当需要N为奇数的N分频电路时，出现问题。图2示意性示出了5分频电路(基于图1中的6分频电路)。对图1中的电路进行修改，使之包括与门(“&”)，该与门在其输入端接收第二和第三触发器的反相输出。与门的输出提供给第一触发器的输入。该配置使得“0”在时钟控制下输入第一触发器的输入端，比原先的情况早一个时钟脉冲。因此，通过该计数器的脉冲序列将会是三个“0”随后两个“1”。然而，可以理解的是该电路的占空比为40％。这对于多数应用来说是不适合的。
为了说明，图3示出了图1和2中的6分频和5分频计数器的状态表。图4示出了相应的状态图。
发明内容
本发明的目的是提供一种N分频计数器，其能够产生占空比为50％的输出信号，其中N为奇数。
根据本发明的第一方面，提供了一种用于从输入时钟信号获取输出时钟信号的电路，所述输出时钟信号具有所述输入时钟信号频率的1/N的频率，其中N是奇数，所述电路包括：
以锁存器环而配置的多个锁存器，所述锁存器以连续对的形式而设置，每一对锁存器包括第一锁存器和第二锁存器，所述第一锁存器在所述输入时钟信号的上升沿或下降沿之一的时刻接通，而所述第二锁存器在所述输入时钟信号的上升沿或下降沿中另一个的时刻接通；以及
具有置位和复位输入端的存储器元件，所述置位和复位输入端用于对所述元件的输出进行置位和复位，所述元件被耦合，以在其置位和复位输入端中的一端处接收来自在所述输入时钟信号的上升沿时接通的锁存器环的输出，而在其置位和复位输入端中的另一端处接收来自在所述输入时钟信号的下降沿时接通的锁存器环的输出，
在所述存储器元件的输出端提供所述输出时钟信号。
在本发明的实施例中，所述锁存器是D型锁存器。所述每一对锁存器提供D型触发器。所述锁存器环中锁存器的个数是N+1。
在本发明的实施例中，所述存储器元件的置位输入耦合到与门的输出。所述与门的输入耦合到均由所述输入时钟信号的上升沿或下降沿而触发的两个锁存器的各个输出。更优选地，所述两个锁存器是所述环中连续锁存器对中的第二锁存器。优选地，所述存储器元件的复位输入耦合到一个锁存器对的第一锁存器的输出。
在本发明的实施例中，所述电路可编程为把N的值设置为包括奇数和偶数值的多个值。所述电路可包括第一复用器，所述第一复用器的一个输入耦合到所述与门的输出，而且所述第一复用器的其他输入耦合到锁存器对的各个输出。所述电路可包括第二复用器，所述第二复用器的第一输入耦合到所述存储器元件的输出，而所述第二复用器的第二输入耦合到一个锁存器对的输出。所述复用器被控制为在其输出端处提供在其输入端处提供的信号之一。
优选地，所述存储器元件是边沿触发器件。更优选地，所述存储器元件是RS触发器。
根据本发明的第二方面，提供了一种产生具有输入时钟信号频率的1/N的频率的时钟信号的方法，其中N是奇数，使用以锁存器环而配置的多个锁存器，所述锁存器以连续对的形式而设置，每一对锁存器包括第一锁存器和第二锁存器，所述第一锁存器在所述输入时钟信号的上升沿或下降沿之一的时刻接通，而所述第二锁存器在所述输入时钟信号的上升沿或下降沿中另一个的时刻接通，所述方法包括：
使用来自在所述输入时钟信号的上升沿或下降沿之一的时刻接通的锁存器环的输出，对存储器的输出置位；而在所述输入时钟信号的上升沿或下降沿中另一个的时刻，对所述存储器元件的输出复位，
在RS触发器的输出端提供所述输出时钟信号。
附图说明
图1示意性地示出了传统的具有johnson环形式的6分频电路；
图2示意性地示出了传统的具有johnson环形式的5分频电路；
图3是图1和2中的电路的状态表；
图4示出了图1和2中的电路的状态图；
图5是当图5中的电路被编制为5分频电路时的状态表；以及
图6示意性地示出了根据本发明实施例的可编制为2、4或5分频的电路。
具体实施方式
图5示出了图2中的5分频电路的状态表，但此时示出了每一个触发器内的状态，即针对单独的D型锁存器的状态。左手列“N”表示分为半个时钟脉冲的计数。为了获得具有50％占空比的输出，该暑促必须在计数(即时钟脉冲)4和0之间切换，并且中途经过计数2。需要确定状态表中可用于产生适当的切换信号的边沿。针对此示例，使用第一锁存器的输入D0从0到1的转变，以及第二锁存器的输入D0i从1到0的转变。
图6示出了可编程以提供具有输入时钟信号(Clock)频率的1/N的时钟频率的输出时钟信号(DIV_N out)的分频器电路。根据该结构，N可以是2、4或5。
图5中的电路包括一组以链的形式而设置的6个D型锁存器。如上文参考图1所述，这些锁存器成对地设置。来自最后的锁存器(D Latch 6)输出Q2向与门(AND)提供一个输入。第四锁存器(D Latch 4)的输出(Q1)向与门提供了另一输入。与门的输出Qx反馈作为可编程复用器(MUX1)的一个输入(c)。复用器(MUX1)的其他输入(b)和(c)分别是第四锁存器(D Latch 4)的输出(Q1)和第二锁存器的输出(Q0)。RS触发器(RS FF)在其Set输入端(S)处接收与门的输出(Qx)，并在其Reset输入端(R)处接收第一锁存器(D Latch 1)的输出(Q0’)。第二可编程复用器(MUX2)在其第一输入端(a)接收RS触发器的输出Q，并在第二输入端(b)接收第二锁存器(D Latch 2)的输出Q0。
图6中的电路按如下方式操作。
2分频
复用器MUX1切换至输入(a)且复用器MUX2切换至输入(b)。锁存器D(Latch 3)至D(Latch 6)掉电，RS触发器和输出与门也一样。该电路实际上成为双锁存器计数器，在MUX2的输出端提供具有50％占空比的2分频时钟信号。
4分频
复用器MUX1切换至输入(b)且复用器MUX2切换至输入(b)。锁存器D(Latch 5)至D(Latch 6)掉电，RS触发器和输出与门也一样。该电路实际上成为四锁存器计数器，在MUX2的输出端提供具有50％占空比的4分频时钟信号。
5分频
在该电路配置中，所有组件均上电。复用器MUX1切换至输入(c)，而复用器MUX2切换至输入(a)。针对该配置的状态表在图6的表中示出。该配置为，从0切换至1的输出Qx将SR触发器的输出从0切换至1，而从0切换至1的输出Q0’将SR触发器的输出从1切换至0。前者在下降时钟脉冲时出现，而后者在上升时钟脉冲时出现。基于Q0’的切换导致RS触发器的复位与基于Qx的复位相比延迟了半个时钟周期。(参考图5中的状态表，可注意到在特定状态中Qx和Q0’均为“0”。而这在SR触发器中通常是禁止的，对该电路的定时进行配置以使该问题不会出现)。
图5中的状态表还示出了在针对该电路被配置为5分频电路的情况下，与门的输出Qx、RS触发器的置位和复位输入(S和R)、以及该电路的最终时钟输出(Out)。
本领域的技术人员可以理解，在不背离本发明的范围的前提下，可以对上述实施例进行各种修改。例如，虽然上述实施例使用D型触发器，然而也可以使用JK触发器的设置。

Claims (14)

1.一种用于从输入时钟信号获取输出时钟信号的电路，所述输出时钟信号具有所述输入时钟信号频率的1/N的频率，其中N是奇数，所述电路包括：
以锁存器环而配置的多个锁存器，所述锁存器以连续对的形式而设置，每一对锁存器包括第一锁存器和第二锁存器，所述第一锁存器在所述输入时钟信号的上升沿或下降沿之一的时刻接通，而所述第二锁存器在所述输入时钟信号的上升沿或下降沿中另一个的时刻接通；以及
具有置位和复位输入端的存储器元件，所述置位和复位输入端用于对所述元件的输出进行置位和复位，所述元件被耦合，以在其置位和复位输入端中的一端处接收来自在所述输入时钟信号的上升沿时接通的锁存器环的输出，而在其置位和复位输入端中的另一端处接收来自在所述输入时钟信号的下降沿时接通的锁存器环的输出，
在所述存储器元件的输出端提供所述输出时钟信号。
2.根据权利要求1所述的电路，其中，所述锁存器环中锁存器的个数是N+1。
3.根据权利要求1或2所述的电路，其中，所述锁存器是D型锁存器。
4.根据权利要求3所述的电路，其中，所述每一对锁存器提供D型触发器。
5.根据上述任意一项权利要求所述的电路，其中，所述存储器元件的置位输入耦合到与门的输出。
6.根据权利要求5所述的电路，其中，所述与门的输入耦合到均由所述输入时钟信号的上升沿或下降沿而触发的两个锁存器的各个输出。
7.根据权利要求6所述的电路，其中，所述两个锁存器是所述环中连续锁存器对中的第二锁存器。
8.根据上述任意一项权利要求所述的电路，其中，所述存储器元件的复位输入耦合到一个锁存器对的第一锁存器的输出。
9.根据上述任意一项权利要求所述的电路，其中，所述电路可编程为把N的值设置为包括奇数和偶数值的多个值。
10.当权利要求9从属于权利要求5时，根据权利要求9所述的电路，所述电路包括复用器，所述复用器的一个输入耦合到所述与门的输出，而且所述复用器的一个或更多个其他输入耦合到锁存器对的各个输出。
11.根据上述任意一项权利要求所述的电路，其中，所述电路包括复用器，所述复用器的第一输入耦合到所述存储器元件的输出，而所述复用器的第二输入耦合到一个锁存器对的输出。
12.根据上述任意一项权利要求所述的电路，其中，所述存储器元件是边沿触发器件。
13.根据上述任意一项权利要求所述的电路，其中，所述存储器元件是RS触发器。
14.一种产生具有输入时钟信号频率的1/N的频率的时钟信号的方法，其中N是奇数，使用以锁存器环而配置的多个锁存器，所述锁存器以连续对的形式而设置，每一对锁存器包括第一锁存器和第二锁存器，所述第一锁存器在所述输入时钟信号的上升沿或下降沿之一的时刻接通，而所述第二锁存器在所述输入时钟信号的上升沿或下降沿中另一个的时刻接通，所述方法包括：
使用来自在所述输入时钟信号的上升沿或下降沿之一的时刻接通的锁存器环的输出，对存储器的输出置位；而在所述输入时钟信号的上升沿或下降沿中另一个的时刻，对所述存储器元件的输出复位，
在所述存储器元件的输出端提供所述输出时钟信号。
CNA2007800034345A 2006-01-24 2007-01-15 分频器电路 Pending CN101375505A (zh)

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