CN101371336B - 鳍结构成形 - Google Patents
鳍结构成形 Download PDFInfo
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Abstract
提供一种形成鳍结构的方法。在基片上提供牺牲结构。鳍结构形成在该牺牲结构的侧面。鳍结构的形成包括多个循环,其中每个循环包括鳍沉积阶段和鳍形貌成形阶段。去除该牺牲结构。
Description
技术领域
本发明涉及半导体器件的形成。更具体地,本发明涉及具有鳍(fin)结构的半导体器件的形成。背景技术
背景技术
在基于半导体的器件中(例如,集成电路或平板显示器),可在各种不同的器件中使用鳍结构。例如,鳍式场效应晶体管(finFET)是建立在SOI基片上的MOSFET,在该基片上将硅蚀刻为晶体管的鳍状体。门电路被包裹在该鳍结构的周围和上方。
间隔光刻是建立鳍的一种方法。在一种做这个的方法中,提供牺牲层然后蚀刻该牺牲层以形成牺牲结构。然后共形的CVD用来形成在该牺牲结构周围和之上的共形层。回蚀用来蚀刻该共形层的水平层。然后去除牺牲结构以形成鳍结构。这些鳍的厚度可以为10nm或更小。为了提供所需的共形层,传统的CVD沉积要求高温CVD。这种高温对于半导体器件是有害的。高温会导致工艺超出器件的热预算。另外,如果之前完成了掺杂,高温可能对掺杂区域有害。
另外,这种CVD鳍处理受到牺牲层和鳍的限制。通常,硅氧化物牺牲层将提供硅氮化物鳍。硅氮化物牺牲层将提供硅氧化物牺牲层。
此外,利用共形的CVD工艺形成鳍结构对于牺牲结构的形貌有非常严格的要求。需要形貌角度非常接近垂直。形貌稍许偏离垂直会导致鳍结构倾斜,导致潜在缺陷问题和CD改变。
发明内容
为了实现前面所述的以及按照本发明的目的,提供一种形成鳍结构的方法。在基片上提供牺牲结构。鳍结构形成在牺牲结构的侧面。鳍结构的形成包括多个循环,其中每个循环包括鳍沉积阶段和鳍形貌成形阶段。去除该牺牲结构。
在本发明的另一表现形式中,提供一种在基片上形成多个垂直鳍的方法。在该基片上提供牺牲结构。鳍结构形成在该牺牲结构的侧面,包括多个循环。每个循环包括鳍沉积阶段,其沉积鳍材料和鳍形貌成形阶段,其成形所沉积的鳍材料的形貌。该鳍沉积阶段包括提供沉积气体,由该沉积气体形成等离子,沉积沉积材料以形成鳍和停止该沉积气体流。该鳍形貌成形阶段包括提供不同于该沉积气体的形貌成形气体,由该形貌成形气体形成等离子,成形沉积的沉积材料的形貌和停止该形貌成形气体的流。去除该牺牲结构。
在本发明的另一表现形式中,提供一种形成鳍结构的设备。提供等离子处理室,其包括:形成等离子处理室外壳的室壁;用于在该等离子处理室外壳内支撑基片的基片支撑件;用于调节该等离子处理室外壳内压力的压力调节器;至少一个电极,用于向该等离子处理室外壳提供功率以保持等离子;气体入口,用于向该等离子处理室外壳内提供气体;和气体出口,用于从该等离子处理室外壳排出气体。气体源与该气体入口流体连通。该气体源包括牺牲层蚀刻剂源、鳍沉积气体源和鳍形貌成形气体源。控制器可控地连接到该气体源和该至少一个电极。该控制器包括至少一个处理器和 计算机可读介质。该计算机可读介质包括:用于在该基片上提供牺牲结构的计算机可读代码;用于在该牺牲结构的侧面形成鳍结构的计算机可读代码,包括多个循环;和用于去除该牺牲结构的计算机可读代码。该形成鳍结构的计算机可读代码包括提供多个循环的计算机可读代码,其中每个循环包括:鳍沉积阶段,其沉积鳍材料,包括提供沉积气体的计算机可读代码、由该沉积气体形成等离子的计算机可读代码、用于沉积沉积材料以形成鳍的计算机可读代码和用于停止该沉积气体流的计算机可读代码;和鳍形貌成形阶段,这个阶段形成沉积的鳍材料的形貌,包括提供不同于该沉积气体的形貌成形气体的计算机可读代码、由该形貌成形气体形成等离子的计算机可读代码、形成所沉积的沉积材料的形貌的计算机可读代码和用于停止该形貌成形气体流的计算机可读代码。
本发明的这些和其他特征将在下面的具体描述中结合附图更详细地说明。
附图说明
在附图中,本发明作为实施例而不是作为限制来说明,其中类似的参考标号指出相似的元件,其中:
图1是可用在本发明的实施方式中的工艺的高级流程图。
图2是形成牺牲结构的更详细的流程图。
图3A-F是按照本发明的实施方式处理的堆的示意性剖视图和俯视图。
图4是可用来实施本发明的等离子处理室的示意图。
图5A-B说明一个计算机系统,其适于实现用于本发明的控制器。
图6是形成鳍的步骤的更详细的流程。
具体实施方式
现在将根据其如在附图中说明的几个实施方式来具体描述本发明。在下面的描述中,阐述许多具体细节以提供对本发明的彻底理解。然而,对于本领域技术人员,显然,本发明可不利用这些具体细节的一些或者全部而实施。在有的情况下,公知的工艺步骤和/或结构没有说明,以避免不必要的混淆本发明。
为了便于理解,图1是可用在本发明的实施方式中的工艺的高级流程图。形成牺牲结构(步骤104)。在该牺牲结构的侧面形成鳍(步骤108)。图6是在该牺牲结构的侧面形成鳍的更详细的流程图,其包括多个循环,其中每个循环包括鳍沉积阶段(步骤604)和鳍形貌成形阶段(步骤608)。去除该牺牲结构(步骤112)。
实施例1
在本发明的实施方式的实施例中,形成该牺牲结构(步骤104)。图2是形成该牺牲结构的更详细的流程图。形成牺牲层(步骤204)。图3A是具有形成在基片304上的牺牲层312的堆300的剖视图。一个或多个层如中间层308可位于该牺牲层312和该基片304之间。在这个例子中,该基片304是硅晶片。该牺牲层可以是许多种类的材料,如氮化硅(SiN)、光刻胶、二氧化硅(SiO2)、无定形碳、硅或有机材料。该牺牲层是硅碳化物。在其他实施方式中,该牺牲层是SiC、SiN、SiOC、H掺杂SiOC、TiN、TaN、Ti、Ta、Si 和SiO2中的至少一个。更一般地,该牺牲层是可以相对鳍材料和任何下面的层有选择地蚀刻的任何材料。
掩模314形成在该牺牲层312之上(步骤208),如图3B所示。特征316蚀刻入该牺牲层312(步骤212),如图3C所示。在该牺牲层中蚀刻特征之后,去除该掩模314(步骤216),如图3D所示。优选的是这些特征侧面具有稍微凹入的形貌从而该蚀刻的特征在底部比在顶部宽,以使得到的鳍结构具有稍许锥形的形貌。优选地,该蚀刻的特征316的侧面具有89到95度的形貌角度。最优选地,该蚀刻的特征的侧面的形貌角度范围从90到93度。
在由剩余的牺牲层312形成的牺牲结构的侧面形成鳍324(步骤108),如图3E所示。
图4是可用来形成鳍的处理室400的示意图。该等离子处理室400包括限制环402、上部电极404、下部电极408,气体源410和排气泵420。该气体源410包括鳍沉积气体源412和鳍形貌成形气体源416。该气体源可包括额外的气体源,如蚀刻气体源418以允许在同一处理室的原处蚀刻该牺牲层。在等离子处理室400内,该基片304位于该下部电极408上。该下部电极408结合合适的基片夹紧机构(例如,静电、机械夹具等),用于把持该基片304。该反应器顶部428结合该上部电极404,其正对该下部电极408设置。该上部电极404、下部电极408和限制环402形成受限制的等离子容积440。通过气体源410向该受限制的等离子容积提供气体并且通过排气泵420经过该限制环402和排气口从该受限制的等离子容积排出气体。该第一RF源444电连接至该上部电极404。第二RF源448电连接至该下部电极408。室壁452围绕该限制环402、上部电极404和下部电极408。该第一RF源444和该第二RF源448均可包括27MHz电源和2MHz电源。将RF功率连接到电极的不同组合是可能的。在LamResearch Corporation的双频电容性(DFC)系统中,由LAM Research Corporation,Fremont,California制造,其可用于本发明的优选实施方式中,27MHz和2MHz电源两者构成连接至的下部电极第二RF电源448,并且上部电极接地。在其他实施方式中,RF电源可具有高达300MHz的频率。控制器435可控地连接到RF源444、448、排气泵420和该气体源410。
图5A和5B说明了一个计算机系统1300,其适于实现用于本发明的实施方式的控制器435。图5A示出该计算机系统一种可能的物理形式。当然,该计算机系统可以具有从集成电路、印刷电路板和小型手持设备到巨型超级计算机的范围内的许多物理形式。计算机系统1300包括监视器1302、显示器1304、机箱1306、磁盘驱动器1308、键盘1310和鼠标1312。磁盘1314是用来与计算机系统1300传入和传出数据的计算机可读介质。
图5B是计算机系统1300的框图的一个例子。连接到系统总线1320的是各种各样的子系统。处理器1322(也称为中央处理单元,CPU)连接到存储设备,包括存储器1324。存储器1324包括随机访问存储器(RAM)和只读存储器(ROM)。如本领域所公知的,ROM用作向CPU单向传输数据和指令,而RAM通常用来以双向的方式传输数据和指令。这两种类型的存储器可包括下面描述的任何合适的计算机可读介质。固定磁盘1326也是双向连接到CPU 1322;其提供额外的数据存储并且也包括下面描述的任何计算机可读介质。固定磁盘1326可用来存储程序、数据等,并且通常是次级存储介质(如硬盘),其比主存储器慢。可以理解的是保留在固定磁盘1326内的信息可以在适当的情况下作为虚拟存储器以标准的方式结合在存储器1324中。可移动磁盘1314可以采用下面描述的任何计算机可读介质的形式。
CPU 1322还连接到各种输入/输出设备,如显示器1304、键盘1310、鼠标1312和扬声器1330。通常,输入/输出设备可以是下 面的任何一种:视频显示器、轨迹球、鼠标、键盘、麦克风、触摸显示器、转换器读卡器、磁带或纸带阅读器、书写板、触针、语音或手写识别器、生物阅读器或其他计算机。CPU 1322可选地可使用网络接口1340连接到另一台计算机或者电信网络。利用这样的网络接口,打算在执行上述方法步骤地过程中,CPU可从网络接收信息或者向网络输出信息。此外,本发明的方法实施方式可在CPU 1322上单独执行或者可在如Internet的网络上与共享该处理一部分的远程CPU一起执行。
另外,本发明的实施方式进一步涉及具有计算机可读介质的计算机存储产品,在计算机可读介质上有用于执行各种计算机实现的操作的计算机代码。该介质和计算机代码可以是那些为本发明目的专门设计和构建的,或者它们可以是对于计算机软件领域技术人员来说公知并且可以得到的类型。计算机可读介质的例子包括,但不限于:磁介质,如硬盘、软盘和磁带;光介质,如CD-ROM和全息设备;磁-光介质,如光软盘;以及为了存储和执行程序代码专门配置的硬件设备,如专用集成电路(ASIC)、可编程逻辑器件(PLD)以及ROM和RAM器件。计算机代码的例子包括如由编译器生成的机器代码,以及包含高级代码的文件,该高级代码能够由计算机使用解释器来执行。计算机可读介质可以是在载波中由计算机数据信号携带的并且表示能够被处理器执行的指令序列的计算机代码。
图6是在该牺牲结构侧面形成鳍的更详细的流程图,其包括多个循环,其中每个循环包括鳍沉积阶段(步骤604)和鳍形貌成形阶段(步骤608)。
优选地,该鳍沉积阶段(步骤604)使用的沉积气体包括CF4和H2组合或CH3F和N2或CxFy或CxHyF2或CxHy组合的至少一个,具有氧化或还原添加剂(如氢气、氮气或氧气)和载体气体(如He、 Ar、Ne、Kr、Xe等)。更一般地,该沉积气体包括碳氢化合物、碳氟化合物和氢氟烃、硅烷或含硅气体的至少一个。更优选地,该沉积气体进一步包括载体气体,如氩气或氙气。更优选地,该沉积气体进一步包括氧化添加剂和还原添加剂的至少一个,如O2、H2或NH3。
鳍沉积阶段(步骤604)的一个实施例提供150sccmCH3F、75sccm N2和100sccm Ar的流。压力设为80mTorr。基片的温度保持在20℃。该第二RF源448提供27MHz频率400瓦特和2MHz频率0瓦特的功率。在该沉积阶段,提供该沉积气体,将该沉积气体转变为等离子,以及停止该沉积气体。
优选地,该鳍形貌成型阶段使用的形貌成形气体包括CxFy和NF3和CxHy和CxHyF2至少一个。更优选地,该形貌成形气体进一步包括载体气体,如氩气或氙气。更优选地,该形貌成形气体进一步包括氧化添加剂和还原添加剂的至少一个,如O2、H2或NH3。因此,该形貌成形气体不同于该沉积气体。
该鳍形貌成形阶段(步骤608)的一个例子提供包含碳氢化合物的卤素(即,氟,溴,氯)气体,如100sccm的CF4。在这个例子中,CF4是在该形貌成形过程中提供的唯一的气体。向该室提供20mTorr的压力。该第二RF源448提供600瓦特的27MHz频率和0瓦特的2 MHz频率功率。在该形貌成形阶段期间,提供该形貌成形气体,将该形貌成形气体转变为等离子,以及然后停止该形貌成形气体。
优选地,该工艺执行2到20个循环。更优选地,该工艺执行3到10个循环。该沉积和形貌成形在多个循环的组合允许形成这些鳍的垂直侧壁。优选地,该垂直侧壁从其底部到顶部与该鳍的底 部成88°到90°的角。当结合该牺牲结构上的凹入形貌时,形成对称的些微呈锥形的鳍结构。
该周期性的循环可具有额外的沉积和/或成形阶段,或可具有其他额外的用于形成该鳍的阶段。
然后去除该牺牲结构(步骤112),留下鳍324,如图3F所示。
实施例2
在另一个实施例中,形成牺牲结构104,光刻胶掩模本身可用作牺牲结构,从而不使用额外的牺牲层。
在两种实施例中,提供额外的传统的处理步骤以由这些鳍形成finFET。
该创新性的工艺提供各种材料的鳍,如无定形碳、无定形硅、硅氧化物和硅氮化物。
尽管本发明依照多个实施方式描述,但是存在落入本发明范围内的改变、修改、置换和各种替代等同物。还应当注意,有许多实现本发明方法和设备的可选方式。所以,其意图是下面所附的权利要求解释为包括所有这样的落入本发明主旨和范围内的改变、修改、置换和各种替代等同物。
Claims (8)
1.一种形成鳍结构的方法,包括:
在基片上提供牺牲结构;
在该牺牲结构的侧面形成鳍结构,包括多个循环,其中
每个循环包括:
鳍沉积阶段,包括:
提供沉积气体;
由该沉积气体形成等离子;
沉积来自该等离子的沉积材料以形成鳍;
停止该沉积气体流;以及
鳍形貌成形阶段,包括
提供不同于该沉积气体的形貌成形气体;
由该形貌成形气体形成等离子;
成形所沉积的沉积材料的形貌;
停止该形貌成形气体流;以及
去除该牺牲结构。
2.根据权利要求1所述的方法,其中该沉积气体包括碳氢化合物、碳氟化合物、氢氟烃或任何含硅气体的至少一个,以及该形貌成形气体包括CxFy、NF3、CxHy和CxHyFz的至少一个。
3.根据权利要求1所述的方法,其中该沉积气体包括硅烷。
4.根据权利要求1-3任一项所述的方法,其中该鳍结构具有垂直侧壁。
5.根据权利要求1-3任一项所述的方法,其中该提供牺牲结构包括在该基片之上形成光刻胶掩模,其中利用该光刻胶掩模形成该牺牲结构。
6.根据权利要求1-3任一项所述的方法,其中该提供牺牲结构包括:
在该基片之上形成牺牲层,
在该基片之上形成掩模;
穿过该掩模将特征蚀刻入该牺牲层;以及
去除该掩模。
7.根据权利要求6所述的方法,其中该掩模是光刻胶掩模。
8.一种用于形成鳍结构的设备,包括:
等离子处理室,包括:
形成等离子处理室外壳的室壁;
基片支撑件,其用于在该等离子处理室外壳内支撑基片;
压力调节器,其用于调节该等离子处理室外壳中的压力;
至少一个电极,其用于向该等离子处理室外壳提供功率以保持等离子;
气体入口,其用于向该等离子处理室外壳内提供气体;以及
气体出口,其用于从该等离子处理室外壳排出气体;
气体源,其与该气体入口流体连通,包括;
牺牲层蚀刻剂源;
鳍沉积气体源;以及
鳍形貌成形气体源;
控制器,其可控地连接到该气体源和该至少一个电极,包括:
至少一个处理器;以及
用于在基片上提供牺牲结构的装置;
用于在该牺牲结构的侧面形成鳍结构的装置,该形成鳍结构包括多个循环,其中针对每个循环,该装置都包括:
用于沉积鳍材料的装置,该沉积鳍材料相应于鳍沉积阶段,其包括:
用于提供沉积气体的装置;
用于由该沉积气体形成等离子的装置;
用于沉积来自该等离子的沉积材料以形成鳍的装置;以及
用于停止该沉积气体流的装置;以及
用于使该沉积的鳍材料的形貌成型的装置,该使该沉积的鳍材料的形貌成型相应于鳍形貌成形阶段,其包括:
用于提供不同于该沉积气体的形貌成形气体的装置;
用于由该形貌成形气体形成等离子的装置;
用于成形所沉积的沉积材料的形貌的装置;以及
用于停止该形貌成形气体流的装置;以及用于去除该牺牲结构的装置。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI409857B (zh) * | 2006-01-23 | 2013-09-21 | Lam Res Corp | 鰭片結構形成 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8283255B2 (en) * | 2007-05-24 | 2012-10-09 | Lam Research Corporation | In-situ photoresist strip during plasma etching of active hard mask |
US8592318B2 (en) | 2007-11-08 | 2013-11-26 | Lam Research Corporation | Pitch reduction using oxide spacer |
US8187480B2 (en) * | 2008-11-13 | 2012-05-29 | Seagate Technology, Llc | Ultra thin alignment walls for di-block copolymer |
CN103000505B (zh) * | 2011-09-16 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | 多栅器件的形成方法 |
CN103021850B (zh) | 2011-09-20 | 2015-04-15 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
JP5915278B2 (ja) * | 2012-03-13 | 2016-05-11 | 株式会社リコー | プログラム、情報処理装置、記憶媒体 |
US8987835B2 (en) * | 2012-03-27 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with a buried semiconductor material between two fins |
US8586455B1 (en) * | 2012-05-15 | 2013-11-19 | International Business Machines Corporation | Preventing shorting of adjacent devices |
CN103258724B (zh) * | 2013-05-09 | 2016-09-28 | 清华大学 | 具有大高宽比fin结构的三维半导体器件及其形成方法 |
CN105097526B (zh) * | 2014-05-04 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | FinFET器件的制作方法 |
DE112015006918T5 (de) | 2015-09-17 | 2018-06-07 | Intel Corporation | Verfahren zum dotieren eines unteren finnengebiets einer halbleiterfinnenstruktur und vorrichtungen, die diese enthalten |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1645576A (zh) * | 2003-12-09 | 2005-07-27 | 国际商业机器公司 | 在FinFET中形成翅片的后退法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5436186A (en) * | 1994-04-22 | 1995-07-25 | United Microelectronics Corporation | Process for fabricating a stacked capacitor |
US6344392B1 (en) * | 1998-11-16 | 2002-02-05 | Vanguard International Semiconductor Corporation | Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor |
NL1015744C2 (nl) * | 2000-07-19 | 2002-01-22 | Dsm Nv | Werkwijze voor de bereiding van 2-(6-gesubstitueerde-1,3-dioxan-4-yl) azijnzuurderivaten. |
AU2002245124A1 (en) * | 2000-11-13 | 2002-07-24 | Vram Technologies, Llc | Sidewalls as semiconductor etch stop and diffusion barrier |
US6664582B2 (en) * | 2002-04-12 | 2003-12-16 | International Business Machines Corporation | Fin memory cell and method of fabrication |
US6642090B1 (en) * | 2002-06-03 | 2003-11-04 | International Business Machines Corporation | Fin FET devices from bulk semiconductor and method for forming |
US6645797B1 (en) * | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
KR100578130B1 (ko) * | 2003-10-14 | 2006-05-10 | 삼성전자주식회사 | 핀 전계효과 트랜지스터를 위한 다중 실리콘 핀 및 그형성 방법 |
KR100545863B1 (ko) * | 2004-07-30 | 2006-01-24 | 삼성전자주식회사 | 핀 구조물을 갖는 반도체 장치 및 이를 제조하는 방법 |
US6949768B1 (en) * | 2004-10-18 | 2005-09-27 | International Business Machines Corporation | Planar substrate devices integrated with finfets and method of manufacture |
US20060134917A1 (en) * | 2004-12-16 | 2006-06-22 | Lam Research Corporation | Reduction of etch mask feature critical dimensions |
US7491647B2 (en) * | 2005-03-08 | 2009-02-17 | Lam Research Corporation | Etch with striation control |
US7695632B2 (en) * | 2005-05-31 | 2010-04-13 | Lam Research Corporation | Critical dimension reduction and roughness control |
US7264743B2 (en) * | 2006-01-23 | 2007-09-04 | Lam Research Corporation | Fin structure formation |
KR20080061018A (ko) * | 2006-12-27 | 2008-07-02 | 동부일렉트로닉스 주식회사 | 반도체소자의 제조방법 |
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2006
- 2006-01-23 US US11/338,464 patent/US7264743B2/en active Active
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- 2007-01-05 CN CN2007800028753A patent/CN101371336B/zh not_active Expired - Fee Related
- 2007-01-05 KR KR1020087020703A patent/KR101380544B1/ko active IP Right Grant
- 2007-01-15 TW TW096101497A patent/TWI409857B/zh not_active IP Right Cessation
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1645576A (zh) * | 2003-12-09 | 2005-07-27 | 国际商业机器公司 | 在FinFET中形成翅片的后退法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI409857B (zh) * | 2006-01-23 | 2013-09-21 | Lam Res Corp | 鰭片結構形成 |
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MY161826A (en) | 2017-05-15 |
TWI409857B (zh) | 2013-09-21 |
KR101380544B1 (ko) | 2014-04-11 |
TW200731356A (en) | 2007-08-16 |
CN101371336A (zh) | 2009-02-18 |
WO2007087159A1 (en) | 2007-08-02 |
KR20080097439A (ko) | 2008-11-05 |
US20070170146A1 (en) | 2007-07-26 |
US7682479B2 (en) | 2010-03-23 |
US7264743B2 (en) | 2007-09-04 |
US20080017314A1 (en) | 2008-01-24 |
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