CN101335246A - Method of manufacturing flash memory device - Google Patents

Method of manufacturing flash memory device Download PDF

Info

Publication number
CN101335246A
CN101335246A CNA2008101278165A CN200810127816A CN101335246A CN 101335246 A CN101335246 A CN 101335246A CN A2008101278165 A CNA2008101278165 A CN A2008101278165A CN 200810127816 A CN200810127816 A CN 200810127816A CN 101335246 A CN101335246 A CN 101335246A
Authority
CN
China
Prior art keywords
dielectric film
semiconductor substrate
grid
slider
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008101278165A
Other languages
Chinese (zh)
Other versions
CN101335246B (en
Inventor
任贤珠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Publication of CN101335246A publication Critical patent/CN101335246A/en
Application granted granted Critical
Publication of CN101335246B publication Critical patent/CN101335246B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of manufacturing a flash memory device that prevents generation of voids when forming an interlayer dielectric film. The method may include forming a gate on a semiconductor substrate, and then sequentially stacking a first dielectric film and a second dielectric film on the semiconductor substrate, and then forming a first spacer comprising a first dielectric film pattern and a second dielectric film pattern on sidewalls of the gate by performing a first etching process, and then forming source and drain areas in the semiconductor substrate, and then removing the second dielectric film, and then sequentially stacking a third dielectric film and a fourth dielectric film on the semiconductor substrate, and then forming a second spacer comprising the first dielectric pattern and a third dielectric pattern on the sidewalls of the gate by performing a second etching process, and then forming an interlayer dielectric film on the semiconductor substrate including the gate and the first spacer.

Description

Make the method for flash memory device
The application is based on 35U.S.C. § 119 the require korean patent application 10-2007-0062648 number priority of (submitting on June 26th, 2007), and its full content is hereby expressly incorporated by reference with way of reference.
Technical field
The present invention relates to a kind of semiconductor device, more specifically, the present invention relates to a kind of method of making flash memory device.
Background technology
Flash memory device is a kind of non-volatile memory medium, even when outage, the data that are stored in wherein can not lost yet.When carrying out, read and during operation such as deletion, the flash memory device with high processing rate is favourable such as recording.Therefore, flash memory device has been widely used in the storage of basic input output systems (Bios) such as PC (PC), set-top box, printer and the webserver.Recently, flash memory device has been widely used in the device such as digital camera and cellular mobile phone.
Yet, along with flash memory device becomes more highly integrated, the size of the cellular of flash memory device (unit cell) reduces, and the space interval between the area of grid of formation cellular also reduces thereupon equally, thereby can produce space (void) when forming metal wire.
Summary of the invention
The specific embodiment of the present invention relates to a kind of method of making memory device, and it is used for preventing the generation in space when forming interlayer dielectric film (interlayer dielectric film).
The specific embodiment of the present invention relates to a kind of method of making flash memory device, at least one in comprising the following steps: on the Semiconductor substrate and/or above form grid; Then on this Semiconductor substrate and/or above sequentially pile up first dielectric film and second dielectric film, and by first etching process on the sidewall of this grid and/or above form the first medium pattern and second dielectric pattern; Then on this Semiconductor substrate and/or above form source region and drain region; Then on this Semiconductor substrate and/or above remove the second medium pattern and form the 3rd dielectric film; On the 3rd dielectric film, carry out second etching process then, thus on this gate lateral wall and/or above first dielectric pattern and the 3rd dielectric pattern in form slider (spacer); Then on the Semiconductor substrate that is formed with grid and slider and/or above form interlayer dielectric film.
The specific embodiment of the present invention relates to a kind of method, at least one in comprising the following steps: form grid on Semiconductor substrate; On this Semiconductor substrate, sequentially pile up first dielectric film and second dielectric film then; By implementing first etching process, on the sidewall of this grid, form first slider that comprises the first dielectric film pattern and the second dielectric film pattern then; In this Semiconductor substrate, form source region and drain region then; Remove second dielectric film then; On this Semiconductor substrate, sequentially pile up the 3rd dielectric film and the 4th dielectric film then; By implementing second etching process, on gate lateral wall, form second slider that comprises first dielectric pattern and the 3rd dielectric pattern then; On the Semiconductor substrate that comprises the grid and second slider, form interlayer dielectric film then.
The specific embodiment of the present invention relates to a kind of method, at least one in comprising the following steps: form a plurality of grids and form gate electrode in the cellular zone (cell area) of Semiconductor substrate in the surrounding zone of this Semiconductor substrate (peripheral area); On the sidewall of this grid and gate electrode, form first slider that comprises first dielectric layer and second dielectric layer then; Formation source/drain region in this Semiconductor substrate then; Remove second dielectric layer then to expose first dielectric layer; On the sidewall of this grid and gate electrode, form second slider that comprises first dielectric layer and the 3rd dielectric layer then.
The specific embodiment of the present invention relates to a kind of method, at least one in comprising the following steps: form grid at interval on Semiconductor substrate; On the sidewall of grid, form first slider that comprises first oxide layer (oxide skin(coating)) and first nitration case (nitride layer) then; Formation source/drain region in this Semiconductor substrate then; Remove first nitration case then so that first oxide layer exposes; On the sidewall of grid, form second slider that comprises first oxide layer and second nitration case then; And on grid and source/drain region, form silicide layer then; On the Semiconductor substrate that comprises grid, silicide layer and second slider, form interlayer dielectric film then; Form then and see through the contact plunger (contact plug) that grid, gate electrode and source/drain region are extended and be electrically connected to interlayer dielectric film.
Description of drawings
Fig. 1 shows the method for making flash memory device according to embodiment to Figure 11.
Embodiment
As shown in Figure 1, on Semiconductor substrate 10 with unit area (cell region) or district and neighboring area (peri region) or district and/or the top form gate electrode 18 and grid 20.In cellular zone, can form the grid 20 that comprises first grid oxide-film (sull) 11, floating boom 12, dielectric film 14 and control grid 16.In the surrounding zone, form second grid oxide-film 17 and gate electrode 18.Floating boom 12, control electrode 16 and gate electrode 18 can be made by polysilicon.Can be formed for making floating boom 12 and the dielectric film 14 of controlling grid 16 insulation with oxide-nitride thing-oxide (ONO) structure.When control electrode 16 is used for bias voltage excitation electron (bias voltage excitingelectron) is applied to thereunder the floating boom 12 that forms with charging or when discharging this electronics, floating boom 12 can be used to store data.
As shown in Figure 2, then can on the Semiconductor substrate 10 that comprises grid 20 and gate electrode 18 and/or above form slider film 34.Can be by sequentially piling up first oxide-film 30 and first nitride film (nitride film), 32 formation slider films 34.First oxide-film 30 can be formed and had scope 100 by tetraethyl orthosilicate (TEOS)
Figure A20081012781600101
To 300 Between thickness.First nitride film 32 can be formed and had scope 500 by silicon nitride (SiN)
Figure A20081012781600103
To 800 Between thickness.
As shown in Figure 3, thus can make the slider film 34 that forms in double-decker stand etch processes then forms first slider of being made up of first oxide film pattern 39 and first nitride film pattern 38 on the sidewall of grid 20 and gate electrode 18.For example, can form directly near (against) the sidewall of grid 20 and gate electrode 18 and also on the Semiconductor substrate 10 and/or above the first oxide film pattern 39.On first oxide film pattern 39 and/or above can form first nitride film pattern 38.
As shown in Figure 4, utilize first nitride film pattern 38 to carry out ion implantation process to form source/drain region 42 then as high concentration impurities district in the Semiconductor substrate 10 or zone as mask.
As shown in Figure 5, can after implementing ion implantation process, remove first nitride film pattern 38 then.Can remove first nitride film pattern 38 by implementing wet etch process.Wet etching process can comprise phosphoric acid (H 3PO 4).Before forming interlayer dielectric film, the space interval of removing between the grid 20 that forms in first nitride film pattern, 38 feasible (secure) cellular zones of protection fully becomes possibility.Therefore, when sequentially forming interlayer dielectric film, can prevent to produce the space and can protect fully to be used to form the processing edge (process margin) of contact afterwards.In addition, the thickness according to first nitride film pattern of removing 38 can reduce the space interval between the grid 20, thereby can improve the device integrated level.
As shown in Figure 6, then on the Semiconductor substrate 10 of the gate electrode 18 in grid in comprising cellular zone 20 and the surrounding zone and/or above form second nitride film 50.Second nitride film 50 can be made and had scope 70 by silicon nitride (SiN)
Figure A20081012781600105
To 200
Figure A20081012781600106
Between thickness.Second nitride film 50 can be used to prevent produce by subsequently by self-aligned silicide (salicide) handle on first oxide film pattern 39 with/above form the unusual device performance that self aligned polycide causes.Because in the process of removing first nitride film pattern 38, want the scheduled volume of the nitride film that keeps also to have process technology limit (process limit) for control, be more reliable and more stable method so in processing subsequently, deposit again.
As shown in Figure 7, can on second nitride film 50 and/or above form second oxide-film 55.Second oxide-film 55 can be made and had scope 360 by TEOS
Figure A20081012781600111
To 440
Figure A20081012781600112
Between thickness.
As shown in Figure 8, can on second oxide-film 55 and second nitride film 50, carry out etching process then, thereby form by second slider of forming near first oxide film pattern 39 and second nitride film pattern 52 of (against) grid 20 and gate electrode 18 sidewalls 54.In etching process, on grid 20, gate electrode 18 and the source/drain region 42 and/or above part second nitride film 50 and whole second oxide-film 55 that form be removed.
As shown in Figure 9, silicide can be formed metal (silicide-forming metal) 57 then is deposited on the Semiconductor substrate 10 that comprises the gate electrode 18, slider 54 and first oxide film pattern 39 that form in the grid 20 that forms in the cellular zone, the surrounding zone and/or the top.Silicide forms metal 57 and can be made by cobalt (Co).
As shown in figure 10, then can on the Semiconductor substrate 10 and/or above implement annealing process bringing out the reaction between silicon and the metal, thereby respectively on the upper space in grid 20, gate electrode 18 and source/drain region 42 and/or above form metal silicide layer 59 simultaneously.Through this annealing process, can only in Metal Contact silicon and polysilicon region, form metal silicide layer 59.As a result, because the reaction between metal and the silicide is blocked, can not form metal silicide layer 59 in other zones.After forming metal silicide layer 59 simultaneously on grid 20, gate electrode 18 and the source/drain region 42, can remove the silicide that does not have with silicon and polysilicon reaction by the selective etch process and form metal 57.
On the Semiconductor substrate 10 of the gate electrode 18 that forms in the grid 20 that can in comprising cellular zone, form then as shown in figure 11,, the surrounding zone, slider 54, first oxide film pattern 39 and metal silicide layer 59 and/or above form interlayer dielectric film 60.Interlayer dielectric film 60 can be dielectric (PMD) film and can be by at least a the making in phosphosilicate glass (PSG), boron-phosphorosilicate glass (BPSG) and the unadulterated silex glass (USG) before the metal.According to embodiment, can protect space enough between the grid 20 by removing the first nitride film pattern 38, thereby when forming interlayer dielectric film 60, can not produce the space between the grid 20.By interlayer dielectric film 60 is carried out selective etch, can in interlayer dielectric film 60, form the through hole (via hole) of at least one exposing metal silicide layer 59.The metal level of being made by tungsten (W) can be embedded in then in the through hole to form the contact plunger (contact plug) that is electrically connected to grid 20 and source/drain region 42.According to embodiment, owing to do not produce the space when forming interlayer dielectric film 60, when forming contact plunger, the diffusion phenomena that caused by the space do not produce.As a result, flash memory device can have the performance of enhancing in operating process.In addition, when forming contact plunger, the formation in space also can prevent to form bridge.
According to embodiment, the method for manufacturing flash memory device has been protected the space between (secure) grid, thereby prevents to produce when forming interlayer dielectric film the space.Thus, when forming contact plunger, prevent between device, to form bridge, make reliability that guarantees flash memory device and the high integration that realizes device become possibility owing to having removed metal level.
Although described multiple embodiment by a plurality of exemplary embodiments, should be appreciated that, it may occur to persons skilled in the art that multiple other are revised and embodiment all will fall in the spirit and scope of principle of the present disclosure.More specifically, in the scope of this specification, accompanying drawing and claims, can carry out various modifications and change aspect the part of subject combination arrangement and/or the arrangement.Except the modification and change of part and/or arrangement aspect, alternately using is conspicuous for a person skilled in the art equally.

Claims (20)

1. method comprises:
On Semiconductor substrate, form grid; Then
On described Semiconductor substrate, sequentially pile up first dielectric film and second dielectric film; Then
On the sidewall of described grid, form first slider that comprises the first dielectric film pattern and the second dielectric film pattern by carrying out first etching process; Then
In described Semiconductor substrate, form source region and drain region; Then
Remove described second dielectric film; Then
On described Semiconductor substrate, sequentially pile up the 3rd dielectric film and the 4th dielectric film; Then
On the described sidewall of described grid, form second slider that comprises first dielectric pattern and the 3rd dielectric pattern by carrying out second etching process; Then
On the described Semiconductor substrate that comprises described grid and described second slider, form interlayer dielectric film.
2. method according to claim 1, wherein, remove described second dielectric pattern and comprise:
By carrying out wet etch process to remove the described second dielectric film pattern.
3. method according to claim 2 wherein, is used phosphoric acid (H 3PO 4) implement described wet etch process as etching solution.
4. according to the described method of claim 1, wherein, the described first and the 4th dielectric film comprises sull and the described second and the 3rd dielectric film comprises nitride film.
5. according to the described method of claim 4, wherein, described sull comprises TEOS, and described nitride film comprises SiN.
6. method according to claim 1, wherein, sequentially pile up described first dielectric film and described second dielectric film comprises:
Formation sequentially has thickness range and exists
Figure A2008101278160003C1
Arrive
Figure A2008101278160003C2
Between described first dielectric film and have thickness range and exist
Figure A2008101278160003C3
Arrive
Figure A2008101278160003C4
Between described second dielectric film.
7. method according to claim 1, wherein, sequentially pile up described the 3rd dielectric film and described the 4th dielectric film comprises:
Formation has thickness range and exists
Figure A2008101278160003C5
Arrive
Figure A2008101278160003C6
Between described the 3rd dielectric film and have thickness range and exist Arrive
Figure A2008101278160003C8
Between described the 4th dielectric film.
8. method according to claim 1 wherein, forms described second slider and comprises:
Described second etching process of described the 3rd dielectric film of part and described whole the 4th dielectric films is removed in enforcement.
9. method according to claim 1 wherein, forms described grid and is included on the described Semiconductor substrate sequentially piled grids sull, floating boom, dielectric film and control grid.
10. method according to claim 1 further comprises, after forming described second slider and before the described interlayer dielectric film of formation:
On the described Semiconductor substrate that comprises described grid and described second slider, form metal level; Then
On described grid and described source/drain region, forming silicide layer by implementing annealing process on the described Semiconductor substrate.
11. method according to claim 10, wherein, described metal level comprises cobalt.
12. a method comprises:
In the cellular zone of Semiconductor substrate, form a plurality of grids and in the surrounding zone of described Semiconductor substrate, form a gate electrode; Then
On described grid and described gate electrode sidewall, form first slider that comprises first dielectric layer and second dielectric layer; Then
Formation source/drain region in described Semiconductor substrate; Then
Remove described second dielectric layer to expose described first dielectric layer; Then
On the described sidewall of described grid and described gate electrode, form second slider that comprises described first dielectric layer and the 3rd dielectric layer.
13. method according to claim 12 wherein, forms described first slider and comprises:
On the described upper space of described Semiconductor substrate, form described first dielectric film near described grid and described gate electrode sidewall; Then
On described first dielectric film, form described second dielectric film; Then
On described first dielectric film and described second dielectric film, implement first etching process.
14. method according to claim 12 wherein, forms described second slider and comprises:
On described first dielectric film, form described the 3rd dielectric film; Then
On described the 3rd dielectric film, form the 4th dielectric film; Then
On described the 3rd dielectric film and described the 4th dielectric film, implement second etching process.
15. method according to claim 14 wherein, is implemented described second etching process and is comprised:
Remove described the 3rd dielectric film of part and described whole the 4th dielectric film.
16. method according to claim 12 further comprises, after forming described second slider:
On described grid, described gate electrode and described source/drain region, form silicide layer; Then
On the described Semiconductor substrate that comprises described grid, described gate electrode, described silicide layer and described second slider, form interlayer dielectric film; Then
Formation extends through described interlayer dielectric film and is electrically connected to the contact plunger in described grid, described gate electrode and described source/drain region.
17. method according to claim 16 wherein, forms described silicide layer and comprises:
On the described Semiconductor substrate that comprises described grid, described gate electrode and described second slider, form the first metal layer; Then
On described Semiconductor substrate, implement annealing process.
18. method according to claim 17 wherein, forms described contact plunger and comprises:
In the described interlayer dielectric film that exposes described silicide layer, form through hole; Then
In described through hole, form second metal level.
19. method according to claim 18, wherein, described the first metal layer comprises cobalt, and described second metal level comprises tungsten.
20. a method comprises:
On Semiconductor substrate, form grid at interval; Then
On described gate lateral wall, form first slider that comprises first oxide layer and first nitration case; Then
Formation source/drain region in described Semiconductor substrate; Then
Remove described first nitration case to expose described first oxide layer; Then
On the described sidewall of described grid, form second slider that comprises described first oxide layer and second nitration case; Then
On described grid and described source/drain region, form silicide layer; Then
On the described Semiconductor substrate that comprises described grid, described silicide layer and described second slider, form interlayer dielectric film; Then
Formation extends through described interlayer dielectric film and is electrically connected to the contact plunger in described grid, described gate electrode and described source/drain region.
CN2008101278165A 2007-06-26 2008-06-25 Method of manufacturing flash memory device Expired - Fee Related CN101335246B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020070062648 2007-06-26
KR1020070062648A KR100812089B1 (en) 2007-06-26 2007-06-26 Method of manufacturing flash memory device
KR10-2007-0062648 2007-06-26

Publications (2)

Publication Number Publication Date
CN101335246A true CN101335246A (en) 2008-12-31
CN101335246B CN101335246B (en) 2010-08-25

Family

ID=39398283

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101278165A Expired - Fee Related CN101335246B (en) 2007-06-26 2008-06-25 Method of manufacturing flash memory device

Country Status (6)

Country Link
US (1) US7883952B2 (en)
JP (1) JP2009010381A (en)
KR (1) KR100812089B1 (en)
CN (1) CN101335246B (en)
DE (1) DE102008029811A1 (en)
TW (1) TW200901335A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785375A (en) * 2016-08-24 2018-03-09 三星电子株式会社 Semiconductor device and its manufacture method

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100954937B1 (en) 2007-12-21 2010-04-27 주식회사 동부하이텍 Method of fabricating flash memory device
KR100976684B1 (en) 2008-08-01 2010-08-18 주식회사 하이닉스반도체 Method for forming the contact hall of semiconductor memory device
KR20100081833A (en) * 2009-01-07 2010-07-15 삼성전자주식회사 Method of manufacturing non-volatile memory devices
US8476156B1 (en) * 2011-12-28 2013-07-02 Eon Silicon Solution Inc. Manufacturing method of flash memory structure with stress area
CN105374753B (en) * 2014-07-07 2019-07-05 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of memory

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2864850B2 (en) * 1992-03-09 1999-03-08 日本電気株式会社 Manufacturing method of nonvolatile semiconductor memory device
JPH09307010A (en) * 1996-03-11 1997-11-28 Ricoh Co Ltd Method of fabricating semiconductor storage
KR100324024B1 (en) * 1998-12-28 2002-05-13 박종섭 Gate electrode formation method of semiconductor device
KR100320957B1 (en) * 2000-01-27 2002-01-29 윤종용 Method for forming a contact hole in a semiconductor device
KR20020049929A (en) * 2000-12-20 2002-06-26 박종섭 Method of manufacturing a flash memory device
JP4866534B2 (en) * 2001-02-12 2012-02-01 エーエスエム アメリカ インコーポレイテッド Improved deposition method for semiconductor films.
KR100418091B1 (en) * 2001-06-29 2004-02-11 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
US7002223B2 (en) * 2001-07-27 2006-02-21 Samsung Electronics Co., Ltd. Semiconductor device having elevated source/drain
KR100450666B1 (en) * 2001-09-03 2004-10-01 삼성전자주식회사 Method of forming selectively metal silicide layer and semiconductor device having the same
KR100671607B1 (en) * 2002-07-09 2007-01-18 주식회사 하이닉스반도체 Method for manufacturing flash memory
KR20040026500A (en) * 2002-09-25 2004-03-31 삼성전자주식회사 Method of fabricating flash memory devices
KR100469129B1 (en) * 2002-09-30 2005-01-29 삼성전자주식회사 Non-volatile memory device and Method of manufacturing the same
KR100500448B1 (en) 2003-02-06 2005-07-14 삼성전자주식회사 Method of fabricating a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit fabricated thereby
JP2004363457A (en) * 2003-06-06 2004-12-24 Toshiba Corp Non-volatile semiconductor memory and method for manufacturing the same
CN1591823A (en) 2003-08-27 2005-03-09 上海宏力半导体制造有限公司 Mfg. Method of increasing IC assembling density
JP2005166822A (en) * 2003-12-01 2005-06-23 Toshiba Corp Semiconductor device including non-volatile memory and manufacturing method thereof
KR100578104B1 (en) * 2003-12-16 2006-05-10 한국과학기술원 Method for Fabricating Epitaxial Cobalt-Disilicide Layer Using Cobalt Nitride Film
US7067374B2 (en) * 2004-08-05 2006-06-27 Macronix International Co., Ltd. Manufacturing methods and structures of memory device
ITMI20042533A1 (en) * 2004-12-28 2005-03-28 St Microelectronics Srl METHOD OF MANUFACTURE OF NON-VOLATILE MEMORY DEVICES INTEGRATED ON A SEMICONDUCTOR SUBSTRATE
KR100606923B1 (en) * 2004-12-30 2006-08-01 동부일렉트로닉스 주식회사 The flash memory cell and its manufacturing method for void improvement and retention increment
KR101238136B1 (en) 2005-12-13 2013-02-28 엘지전자 주식회사 A condensing apparatus of a dish washer
US7651915B2 (en) * 2006-10-12 2010-01-26 Infineon Technologies Ag Strained semiconductor device and method of making same
US20080280442A1 (en) * 2007-05-09 2008-11-13 Hynix Semiconductor Inc. Method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785375A (en) * 2016-08-24 2018-03-09 三星电子株式会社 Semiconductor device and its manufacture method

Also Published As

Publication number Publication date
KR100812089B1 (en) 2008-03-07
CN101335246B (en) 2010-08-25
TW200901335A (en) 2009-01-01
DE102008029811A1 (en) 2009-01-15
US20090004795A1 (en) 2009-01-01
JP2009010381A (en) 2009-01-15
US7883952B2 (en) 2011-02-08

Similar Documents

Publication Publication Date Title
CN101335246B (en) Method of manufacturing flash memory device
US8829644B2 (en) Nonvolatile memory device and method of manufacturing the same
US7897512B2 (en) Methods of forming integrated circuit devices including a multi-layer structure with a contact extending therethrough
JP2009026802A (en) Manufacturing method of semiconductor device, and semiconductor device
US6521941B2 (en) Non-volatile memory device and fabrication method thereof
CN101207091B (en) Method manufactruing of flash memory device
US20080211006A1 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
CN100539084C (en) Make the method for flash memory
US20040191992A1 (en) Flash memory cell and fabrication thereof
US20080157165A1 (en) Flash Memory Device and Method of Manufacturing the Same
CN101183665B (en) Silicon-oxide-nitride-oxide-silicon flash memory and manufacturing method thereof
US7271062B2 (en) Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory
CN100468704C (en) Production method of SONOS flash memory
JP2007165829A (en) Gate formation method of flash memory device
US20070111449A1 (en) Non-volatile memory cell and method for manufacturing the same
US20070269947A1 (en) Method for manufacturing NAND flash memory
KR20080060486A (en) Flash memory and the fabricating method thereof
US7932149B2 (en) Method of manufacturing a semiconductor device
CN107123651B (en) Method for manufacturing nonvolatile memory and nonvolatile memory
CN100517657C (en) SONOS Flash memory manufacture method
WO2007099589A1 (en) Semiconductor device and process for producing the same
JP2010129740A (en) Non-volatile semiconductor memory device and method of manufacturing the same
KR100789610B1 (en) Method of manufacturing flash memory device
JP2009076636A (en) Manufacturing method of nonvolatile semiconductor storage device
US9431406B1 (en) Semiconductor device and method of forming the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100825

Termination date: 20130625