CN101330011A - Method of forming metal electrode of system in package - Google Patents
Method of forming metal electrode of system in package Download PDFInfo
- Publication number
- CN101330011A CN101330011A CNA2008101004945A CN200810100494A CN101330011A CN 101330011 A CN101330011 A CN 101330011A CN A2008101004945 A CNA2008101004945 A CN A2008101004945A CN 200810100494 A CN200810100494 A CN 200810100494A CN 101330011 A CN101330011 A CN 101330011A
- Authority
- CN
- China
- Prior art keywords
- layer
- hole
- semiconductor device
- copper
- combustible material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present invention relates to a method for forming a metal electrode of a system in package including a multilayer semiconductor device having semiconductor devices stacked in a plurality of layers. The method may include forming a through hole extending through the plurality of layers, forming a combustible material layer having high viscosity at a lower portion of the through hole in order to seal the lower portion thereof, and forming a through electrode by filling copper in the through hole. There is an effect of efficiently forming a through electrode having a large depth corresponding to the height of stacked semiconductor devices in the system in package. Filling copper in a through hole having a large depth-to-width ratio may be efficiently done by OSP coating, electrolysis copper plating, and electro Cu plating processes.
Description
According to 35U.S.C.﹠amp; 119, the priority of (submitting on June 22nd, 2007) that the application requires korean patent application 10-2007-0061484 number is hereby expressly incorporated by reference its full content.
Technical field
The present invention relates to a kind of method that is used to form the metal electrode of system grade encapsulation body (system in package), more specifically, relate to a kind of method that is used to form the metal electrode that comprises the system grade encapsulation body with the multilayer semiconductor device (multilayer semiconductordevice) that is stacked on the semiconductor device in a plurality of layers, wherein metal electrode passes each layer as the public electrode that places the semiconductor device on each layer.
Background technology
Along with the multi-functional and trend toward miniaturization of various electronic devices, can in electronic device, provide semiconductor device such as integrated circuit (IC)-components with sandwich construction.This multilayer semiconductor device can have a plurality of circuit devcies, and the high semiconductor device structure of the little integrated degree of size is increasing gradually.For example, a kind of highly integrated semiconductor device has been proposed, it has and have piling up and fixing LSI chip structure of through electrode (through electrode) above a plurality of layer, and a kind of three-dimensional (3D) semiconductor device has been proposed, it has a plurality of Semiconductor substrate structures of piling up that have integrated circuit.
Compact as realizing, a key technology of light and thin electronic equipment, various encapsulation technologies have been applied in the semiconductor device to realize the high-density installation of semiconductor chip.Be used for reducing the technology that semiconductor device is installed to required area on the motherboard as a kind of encapsulating structure that relates to semiconductor device, developed the packaging body in the trellis of a kind of pin insert type packaging body, a kind of mounted on surface packaging body, a kind of lower surface such as spherical grid array package body (BGA) with outside output such as miniaturization encapsulation (small outline package SOP) by ancillary equipment guiding such as dual in-line package (DIP).In addition, recently realize the technology of high-density installation by the area that reduces packaging body and semiconductor chip as a kind of, along with the miniaturization of substrate circuit, the pitch smaller of outside output and impel reducing of packaging body model.
Developed a kind of being used for and gone up the technology that a plurality of semiconductor chips are installed at single core packaging body (single package).In multicore packaging body (multichip package), developed a kind of chip-stacked encapsulation technology that is used to pile up a plurality of semiconductor chips, so that realize more high-density mounting.In addition, a plurality ofly in single core packaging body, have the semiconductor chip of difference in functionality and be called as system grade encapsulation body (SIP) by sealing, and carried out the exploitation of SIP by systematized multicore packaging body.
Simultaneously, the method for isolating from high-density packages and mounted semiconductor chip receives publicity as a kind of method of compactness, light and thin electronic equipment that realizes.This partition method has adopted system level chip (SOC), so that in the different mixed integrated system function that is loaded in the single-chip of semiconductor chip such as memory, logic and analog circuit.
Yet, on single-chip, in the situation of integrated memory, logic and analog circuit etc., be difficult to obtain the low pressure memory circuitry, therefore, be necessary to be controlled at the noise that produces in the logical circuit.In addition, in the situation of mixing the bipolar analog circuit of ground loading, be difficult in and make the analog circuit that is equal to memory and logical circuit on the cmos circuit.Therefore, be replaced in SOC, what can develop at short notice has low cost and receives publicity with the SIP of system level chip identical function.
As a kind of technology that requires to make 3D multilayer LSI and SIP, there is a kind of technology that is used on Semiconductor substrate, forming through electrode.The existing technology that is used for formation through electrode on silicon (Si) wafer still has a plurality of processing steps.In addition, in having the through electrode of the dark degree of depth, formation has difficulties.Should form can interface unit penetrate electricity with the encapsulation plurality of devices in one.In order to form through electrode, metal is received in by in the through hole that forms in preceding step etching, to form the conductor that electronics flows through.SIP comprises having the multilayer semiconductor device that is stacked on the semiconductor device in a plurality of layers.Owing to have the gross thickness of a plurality of layers multilayer semiconductor device, through hole has the darker degree of depth than open region.Therefore, there is a problem, that is, is difficult to closely form through electrode by in through hole, inserting tungsten by traditional chemical vapor deposition (CVD) technology.
Summary of the invention
Numerous embodiments relates to the method for the metal electrode of a kind of SIP of being used to form, more specifically, relate to a kind of method that is used to form the metal electrode that comprises SIP, so that metal electrode passes each layer as the public electrode that places each layer semiconductor-on-insulator device with the multilayer semiconductor device that is stacked on the semiconductor device in a plurality of layers.
Numerous embodiments relates to the method for the metal electrode of a kind of SIP of being used to form, and it firmly forms through electrode, and this SIP comprises having in order to pass the semiconductor device of a plurality of layers long through electrode.
Numerous embodiments relates to a kind of method that is used to form the metal electrode that comprises the SIP with the multilayer semiconductor device that is stacked on the semiconductor device in a plurality of layer, and in can comprising the following steps at least one: form and pass the through hole of multilayer; Apply and seal up combustible material in the bottom of this through hole then with high viscosity; Then by copper being filled in the through hole to form through electrode.
Numerous embodiments relates to a kind of method, at least one during it can comprise the following steps: a kind of system grade encapsulation body is provided, comprises having the multilayer semiconductor device that is stacked in the semiconductor device in a plurality of layers; Form the through hole that extends through a plurality of layers then; Form combustible material at the through hole foot then with high viscosity; Then by copper being filled in the through hole to form through electrode.
Numerous embodiments relates to a kind of method, at least one during it comprises the following steps: provide to comprise the system grade encapsulation body with the multilayer semiconductor device that is stacked in the semiconductor device in a plurality of layers; Form the through hole that extends through a plurality of layers then; Seal through hole then bottom; In through hole, form the through electrode that constitutes by copper then.
Numerous embodiments relates to a kind of method, at least one during it comprises the following steps: provide to comprise the system grade encapsulation body with the multilayer semiconductor device that is stacked in the semiconductor device in a plurality of layers; Form the through hole that extends through a plurality of layers then; Then the lowest surface of multilayer semiconductor device and through hole bottom on form the layer that constitutes by organic substance to seal this through hole bottom; On the upper space of the inwall of lowest surface, the through hole of the layer of forming by organic substance and multilayer semiconductor device, form copper subcrystal layer (copperseed layer) then; On the copper subcrystal layer, form the copper layer then; Remove the part of the copper layer that is formed on the multilayer semiconductor device topmost then; Remove layer that constitutes by organic substance and the copper layer that is formed on the foot of combustible material layer then, thereby form through electrode.
Description of drawings
According to the embodiment of the present invention, exemplary Figure 1A to 1F shows the method for the through electrode that is used to form the system grade encapsulation body that comprises multilayer semiconductor device.
Embodiment
Execution mode illustrated in the accompanying drawings, embodiment are done detailed explanation.In all the likely places, in whole accompanying drawing, use identical label to represent same or analogous parts.
Describe the structure and the effect of execution mode with reference to the accompanying drawings.The structure and the effect of execution mode shown in the drawings and that describe in this article are illustrated as at least one example, and the technical conceive of execution mode is not limited thereto with necessary structure and effect.
Exemplary Figure 1A to 1F shows the consecutive steps of method that is used to form the through electrode of the SIP that comprises multilayer semiconductor device according to embodiment of the present invention a kind of.This method can comprise the through electrode that forms the multilayer semiconductor device with double-layer structure (two-story).But execution mode can be not limited thereto, and is applied to form have three or the method for the through electrode of more multi-layered multilayer semiconductor device.
As shown in exemplary Figure 1A, through hole 102 can be formed on and extend through multilayer semiconductor device.Through hole 102 can be filled to form through electrode with electric conducting material subsequently.In the SIP with multilayer semiconductor device layer, through electrode can extend through a plurality of layers and form, so that the power line of the semiconductor device of each layer or various input and output signal interconnect prevailingly.
Shown in exemplary diagram 1F, can comprise the first transistor part 104 (it is the orlop of sandwich construction) with ground floor transistor device according to the multilayer semiconductor device of embodiment of the present invention, the first metal part 106 with the metal wire in the ground floor, with the metal wire of ground floor be connected with top metal level first through part (viaportion) 108, transistor seconds part 110 with second layer transistor device, the second metal part 112 with the metal wire in the second layer, with the metal wire of the second layer be connected with top metal level second by part 114, and through electrode 122 (it is the common wire (commonline) that is used for first and second layers of power supply or various input and output signals).
As shown in exemplary Figure 1A, in order to form through electrode 122, it can be the common wire of first and second layers of semiconductor device, and through hole 102 can form by extending through first and second layers.According to the embodiment of the present invention, through hole 102 can form by reactive ion etching (RIE).
As shown in exemplary Figure 1B, through hole 102 has the combustible material 116 of high viscosity by coating bottom and is sealed then.According to the embodiment of the present invention, the combustible material 116 with high viscosity can be Organic Solderability protective agent (OSP).OSP can prevent that copper (Cu) surface from contacting with air by the surface applied organic substance at the liner of printed circuit board (PCB), thereby prevents the copper oxidation.The organic substance that is coated in pad surfaces is the material of similar flux (flux), and it is the finish materials with high viscosity that is used in as in the method for the molten processing of precoating (prefluxtreatment).
As in exemplary Figure 1B, further illustrating, the combustible material layer 116 that constitutes by the Organic Solderability protective agent can be coated in through hole 102 bottom to form strip of paper used for sealing.Come the reason of bottom of closed hole 102 as follows by forming the Organic Solderability protective agent.The first, when forming Cu subcrystal layer (Cu seed layer) subsequently, because the reverse opening in hole 102 is opened and through hole 102 has the very dark degree of depth, copper can't deposit in the through hole 102.Therefore, the copper subcrystal layer can't utilize physical vapor deposition (PVD) and form.So can being sealed by the forming of combustible material 116 that is made of the Organic Solderability protective agent bottom of through hole 102 forms subcrystal layer can electroplate (electrolysis Cu plating) by cathode copper.The second, after copper galvanoplastic (ECP), be formed at can easily being removed bottom and as the copper layer 121 bottom of multilayer semiconductor device of through hole 102 subsequently.Particularly, because copper layer 121 can be by utilizing ECP to electroplate rather than utilizing tungsten CVD to form, so copper layer 121 also can be plated to through hole 102 bottom.Yet, if the Organic Solderability protective agent of combustible material layer 116 be formed on through hole 102 bottom and between the copper layer 121, when combustible material layer 116 melted in heat treated subsequently, copper layer 121 can be easily separated so.The 3rd; because the combustible material layer of being made up of the Organic Solderability protective agent 116 has high viscosity; so combustible material layer 116 can not flow in the through hole 102 during it forms, and Cu subcrystal layer 118 can on the inwall of through hole 102 and/or above closely form.
As shown in the exemplary diagram 1C, then, copper subcrystal layer 118 can form by cathode copper galvanoplastic (ECP).Copper subcrystal layer 118 can form by ECP, and copper begin to electroplate on all parts that contact with electrolyte and/or above.Metallide is a kind of electroless plating method, and wherein metal ion is reduced by the effect of chemical reducing agent, and does not utilize outside electric current.According to metallide, how shape that might material all can obtain uniform and fine and close electrodeposited coating.Metallide also can be electroplated the alloy that nonmetallic materials and plating contain reducing agent.Electrolysis Cu plating is meant and utilizes copper (Cu) metallide.
As further illustrating in exemplary diagram 1C, copper can be plated to the foot of the sidewall of through hole 102 and combustible material layer 116 to form copper subcrystal layer 118.Copper subcrystal layer 118 can have scope and exist
Arrive
Between thickness.According to embodiment of the present invention, the thickness of copper subcrystal layer 118 can be
Because the copper layer forms in cathode copper is electroplated with low rate, thus copper subcrystal layer 118 only formed, and copper is packed into through hole 102 by implementing ECP after a while.The reason that forms copper subcrystal layer 118 by ECP is as follows.The first, according to embodiment of the present invention, have in the darker degree of depth through hole 102 for copper being filled in compare with the open area of through hole 102, use the ECP method to replace tungsten CVD commonly used.Because being electroplax, ECP electroplates (or electrotype is electroplated electro plating), so need to form in advance subcrystal layer.The second, utilizing PVD commonly used to be used to form in the method for subcrystal layer, be difficult in its reverse side and have opening and have with respect to open region in the through hole 102 of deep degree and closely form subcrystal layer.Therefore, used the ECP method.
As shown in the exemplary diagram 1D, copper can be filled in the through hole 102 by implementing electroplax copper electroplating technology then, with in through hole 102 and on the conductor device and/or above form the first bronze medal layer 120 and forming on the second bronze medal layer 121 on the combustible material layer 116.According to embodiment of the present invention, can replace tungsten CVD method commonly used by the electroplax copper galvanoplastic of can bottom-uply fill (bottom-up filling) copper is filled in the through hole 102.Electroplax copper electroplating technology is meant the electroplax electroplating technology that uses copper (Cu).Bottom-up filling is a kind of technology that is used to improve the speed that film forms from through hole 102 bottoms, by injecting additive to electroplating solution and periodically and oppositely be applied to electric field and implement.Copper can be higher than from the speed of the sidewall growth of through hole 102 from the speed of the bottom growth of through hole 102.Therefore, effectively copper is filled into that to have in the through hole 102 of deep degree than open region be possible.The copper layer 120 and 121 that is produced by electroplax copper electroplating technology can be formed on the whole surface of multilayer semiconductor device and/or the top.Therefore, copper layer 120 and 121 can be formed at through hole 102 the inside, be formed on corresponding to the top of the through hole 102 of the topmost of multilayer semiconductor device and be formed on lower end corresponding to the combustible material layer 116 of the foot of multilayer semiconductor device.
As shown in the exemplary diagram 1E, be formed at the part of copper layer 120 of the topmost of multilayer semiconductor device, for example, covering is corresponding to the topmost of the through hole 102 of the top of multilayer semiconductor device, then can be flattened by chemico-mechanical polishing (CMP) method (or planarization, planarized).
As shown in the exemplary diagram 1F, combustible material layer 116 and the copper layer 121 bottom that is formed at the combustible material layer can be removed through Overheating Treatment then.For example can in 100 ℃ to 300 ℃ temperature range, implement heat treatment.Can in the time of 150 ℃, implement heat treatment.Heat treatment can be implemented 30 minutes to 100 minutes.Heat treatment can be implemented 60 minutes time.Therefore, the Organic Solderability protective agent of combustible material layer 116, it is the Organic Solderability protective agent with high viscosity, is melted and is removed by utilizing heating.Simultaneously, the copper layer 121 bottom that is formed at combustible material layer 116 can easily separate and be removed, thereby has formed through electrode 122.
As mentioned above, according to the method that is used for forming metal electrode of embodiment of the present invention, be effect for forming the through electrode that has deep degree than the height or the thickness of the semiconductor device that piles up effectively at system grade encapsulation body.Can be used as the public electrode of each semiconductor device according to the through electrode of embodiment of the present invention.Through hole according to embodiment of the present invention can extend through a plurality of layers that are used to pile up and encapsulate the package system of a plurality of semiconductor device.Further, electroplate and electroplax copper electroplating technology, copper is filled in closely to have in the through hole of deep degree than open region be effective by OSP coating, cathode copper.
Although describe the execution mode example with reference to multiple its exemplary execution mode, should be appreciated that it may occur to persons skilled in the art that multiple other modifications and embodiment, they all will fall in the spirit and scope of principle disclosed by the invention.More specifically, in the scope of, accompanying drawing open and claims, can aspect arrangement mode of arranging and/or part, carry out various modifications and change in subject matter in the present invention.Except the modification and change of part and/or arrangement aspect, selectable application selection apparent to those skilled in the art.
Claims (20)
1. method comprises:
System grade encapsulation body is provided, comprises having the multilayer semiconductor device that is stacked on the semiconductor device in a plurality of layers; And
Formation extends through described a plurality of layers through hole; And
Foot at described through hole forms the combustible material with high viscosity; And
By being filled in the described through hole, copper forms through electrode.
2. method according to claim 1, wherein said formation through electrode comprises:
Forming the copper subcrystal layer on all surfaces of described multilayer semiconductor device and on the inwall of described through hole; And
Form the copper layer in described through hole and on the whole surface of described multilayer semiconductor device and on the inwall of described through hole; And
Removal is formed on the described copper layer of described multilayer semiconductor device topmost; And
The part removing the combustible material layer and be formed on the described copper layer of described combustible material layer foot.
3. method according to claim 2, wherein said removal are formed on the described part of described copper layer of the topmost of described multilayer semiconductor device and utilize planarization technology to implement.
4. method according to claim 2, wherein said removal are formed at the described part of described copper layer of the topmost of described multilayer semiconductor device and implement by chemico-mechanical polishing.
5. method according to claim 2, wherein said copper subcrystal layer exists to have scope
Arrive
Between thickness and form.
6. method according to claim 2 wherein utilizes electrolytic plating method to form described copper subcrystal layer.
7. method according to claim 2 is wherein utilized electroplax to electroplate and form described copper layer in described through hole.
8. method according to claim 2, the described combustible material layer of wherein said removal is implemented by heat treatment with the described part of the described copper layer of the foot that is formed on described combustible material layer.
9. method according to claim 8, wherein said heat treatment is carried out between 100 ℃ to 300 ℃ and in 30 to 100 minutes the time range in temperature range.
10. method according to claim 1, wherein said combustible material layer comprises the Organic Solderability protective agent.
11. method according to claim 1, wherein said through hole forms by the response type ion(ic) etching.
12. method according to claim 1, wherein said through hole has big depth-to-width ratio.
13. a method comprises:
System grade encapsulation body is provided, comprises having the multilayer semiconductor device that is stacked on the semiconductor device in a plurality of layers; And
Formation extends through described a plurality of layers through hole; And
Seal described through hole bottom; And
The through electrode that formation is made of the copper in the described through hole.
14. method according to claim 13 is wherein saidly sealed the described of through hole and is comprised bottom:
The described layer that constitutes by combustible material that forms bottom at described through hole.
15. method according to claim 14, wherein said combustible material has high viscosity.
16. method according to claim 15, wherein said combustible material comprises organic substance.
17. method according to claim 14 wherein forms described through electrode and comprises:
On the inwall of the lowest surface of described multilayer semiconductor device and upper space and described through hole, form the copper subcrystal layer; And
On described copper subcrystal layer, form described copper layer; And
Removal is formed on the part of described copper layer of the described upper space of described multilayer semiconductor device; And
Remove described combustible material layer and be formed on the part of the described copper layer on the lowest surface of described combustible material layer.
18. a method comprises:
System grade encapsulation body is provided, comprises having the multilayer semiconductor device that is stacked on the semiconductor device in a plurality of layers; And
Formation extends through described a plurality of layers through hole; And
The lowest surface of described multilayer semiconductor device and described through hole form the layer that constitutes by organic substance bottom, to seal the bottom described of described through hole; And
On the upper space of the inwall of lowest surface, the described through hole of the described layer that constitutes by organic substance and described multilayer semiconductor device, form the copper subcrystal layer; And
On described copper subcrystal layer, form the copper layer; And
Removal is formed on the part of described copper layer of the topmost of described multilayer semiconductor device; And
Layer and the described copper layer that is formed on the foot of described combustible material that removal is made of organic substance, thus through electrode formed.
19. method according to claim 18, the wherein said layer that is made of organic substance is inflammable and has high viscosity.
20. method according to claim 18, the wherein said layer that is made of organic material comprises Organic Solderability protective agent material.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070061484A KR100907896B1 (en) | 2007-06-22 | 2007-06-22 | How to Form Metal Electrodes in System-in-Package |
| KR10-2007-0061484 | 2007-06-22 | ||
| KR1020070061484 | 2007-06-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101330011A true CN101330011A (en) | 2008-12-24 |
| CN101330011B CN101330011B (en) | 2010-06-02 |
Family
ID=40136931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101004945A Expired - Fee Related CN101330011B (en) | 2007-06-22 | 2008-06-23 | Method of forming metal electrode of system in package |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8053362B2 (en) |
| JP (1) | JP4839340B2 (en) |
| KR (1) | KR100907896B1 (en) |
| CN (1) | CN101330011B (en) |
| DE (1) | DE102008029194B4 (en) |
| TW (1) | TWI362710B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157438A (en) * | 2011-01-31 | 2011-08-17 | 江阴长电先进封装有限公司 | Method for manufacturing wafer-level patch panel |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8198547B2 (en) | 2009-07-23 | 2012-06-12 | Lexmark International, Inc. | Z-directed pass-through components for printed circuit boards |
| US20110017504A1 (en) * | 2009-07-23 | 2011-01-27 | Keith Bryan Hardin | Z-Directed Ferrite Bead Components for Printed Circuit Boards |
| US20110017502A1 (en) * | 2009-07-23 | 2011-01-27 | Keith Bryan Hardin | Z-Directed Components for Printed Circuit Boards |
| US8735734B2 (en) | 2009-07-23 | 2014-05-27 | Lexmark International, Inc. | Z-directed delay line components for printed circuit boards |
| US8752280B2 (en) | 2011-09-30 | 2014-06-17 | Lexmark International, Inc. | Extrusion process for manufacturing a Z-directed component for a printed circuit board |
| US9009954B2 (en) | 2011-08-31 | 2015-04-21 | Lexmark International, Inc. | Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material |
| US8790520B2 (en) * | 2011-08-31 | 2014-07-29 | Lexmark International, Inc. | Die press process for manufacturing a Z-directed component for a printed circuit board |
| US9078374B2 (en) | 2011-08-31 | 2015-07-07 | Lexmark International, Inc. | Screening process for manufacturing a Z-directed component for a printed circuit board |
| US8943684B2 (en) * | 2011-08-31 | 2015-02-03 | Lexmark International, Inc. | Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board |
| US8658245B2 (en) | 2011-08-31 | 2014-02-25 | Lexmark International, Inc. | Spin coat process for manufacturing a Z-directed component for a printed circuit board |
| US8912452B2 (en) | 2012-03-29 | 2014-12-16 | Lexmark International, Inc. | Z-directed printed circuit board components having different dielectric regions |
| US8830692B2 (en) | 2012-03-29 | 2014-09-09 | Lexmark International, Inc. | Ball grid array systems for surface mounting an integrated circuit using a Z-directed printed circuit board component |
| US8822838B2 (en) | 2012-03-29 | 2014-09-02 | Lexmark International, Inc. | Z-directed printed circuit board components having conductive channels for reducing radiated emissions |
| US8822840B2 (en) | 2012-03-29 | 2014-09-02 | Lexmark International, Inc. | Z-directed printed circuit board components having conductive channels for controlling transmission line impedance |
| CN116884889B (en) * | 2023-09-07 | 2024-01-16 | 成都汉芯国科集成技术有限公司 | Chip three-dimensional sip packaging system and packaging method based on TSV technology |
Family Cites Families (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07109873B2 (en) * | 1988-07-05 | 1995-11-22 | 株式会社東芝 | Semiconductor memory device |
| JPH0476946A (en) * | 1990-07-19 | 1992-03-11 | Fujitsu Ltd | Wafer integrated circuit device |
| US5612552A (en) * | 1994-03-31 | 1997-03-18 | Lsi Logic Corporation | Multilevel gate array integrated circuit structure with perpendicular access to all active device regions |
| KR100447035B1 (en) * | 1996-11-21 | 2004-09-07 | 가부시키가이샤 히타치세이사쿠쇼 | Manufacturing process of semiconductor device |
| JP2000311982A (en) * | 1999-04-26 | 2000-11-07 | Toshiba Corp | Semiconductor device, semiconductor module and method of manufacturing them |
| JP3775129B2 (en) * | 1999-09-21 | 2006-05-17 | セイコーエプソン株式会社 | Semiconductor chip connection method |
| JP3757766B2 (en) * | 2000-07-07 | 2006-03-22 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
| DE10044540C1 (en) | 2000-09-05 | 2002-01-31 | Siemens Ag | Forming conducting coatings on substrate through hole walls involves applying covering coating on one side, coating with electrically conducting material, removing covering coating |
| US7034386B2 (en) * | 2001-03-26 | 2006-04-25 | Nec Corporation | Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same |
| JP4703061B2 (en) * | 2001-08-30 | 2011-06-15 | 富士通株式会社 | Thin film circuit board manufacturing method and via forming board forming method |
| JP3861669B2 (en) * | 2001-11-22 | 2006-12-20 | ソニー株式会社 | Manufacturing method of multichip circuit module |
| KR100435813B1 (en) * | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | Multi chip package using metal bar and manufacturing method thereof |
| US6852627B2 (en) | 2003-03-05 | 2005-02-08 | Micron Technology, Inc. | Conductive through wafer vias |
| JP4057976B2 (en) * | 2003-08-05 | 2008-03-05 | 本田技研工業株式会社 | Variable compression ratio engine |
| US7453150B1 (en) * | 2004-04-01 | 2008-11-18 | Rensselaer Polytechnic Institute | Three-dimensional face-to-face integration assembly |
| US6867318B1 (en) | 2004-06-30 | 2005-03-15 | Nalco Company | Composition for coating of aluminum |
| JP4376715B2 (en) * | 2004-07-16 | 2009-12-02 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JPWO2006070652A1 (en) * | 2004-12-27 | 2008-06-12 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof, wiring board and manufacturing method thereof, semiconductor package and electronic device |
| DE102005004365A1 (en) | 2005-01-31 | 2006-08-10 | Infineon Technologies Ag | Conducting structure manufacturing method for integrated circuit arrangement, involves superimposing nucleation layer at base surface or cover surface before or after creation of through-hole, and depositing structure material in hole |
| US7701052B2 (en) * | 2005-10-21 | 2010-04-20 | E. I. Du Pont De Nemours And Company | Power core devices |
| EP2005468A1 (en) * | 2006-03-30 | 2008-12-24 | Koninklijke Philips Electronics N.V. | Improving control of localized air gap formation in an interconnect stack |
| KR100735483B1 (en) * | 2006-08-23 | 2007-07-03 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabricating method thereof |
| KR100806789B1 (en) * | 2006-08-30 | 2008-02-27 | 동부일렉트로닉스 주식회사 | Method of fabricating sip semiconductor device |
| KR100789571B1 (en) * | 2006-08-31 | 2007-12-28 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabricating method thereof |
| KR100752198B1 (en) * | 2006-09-13 | 2007-08-27 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor device |
| JP2008251666A (en) * | 2007-03-29 | 2008-10-16 | Tohoku Univ | Three-dimensional structure semiconductor device |
| KR100920039B1 (en) * | 2007-06-21 | 2009-10-07 | 주식회사 하이닉스반도체 | Stacked semiconductor package and method of manufacturing thereof |
| US20090026524A1 (en) * | 2007-07-27 | 2009-01-29 | Franz Kreupl | Stacked Circuits |
| US20090261416A1 (en) * | 2008-04-18 | 2009-10-22 | Wolfgang Raberg | Integrated mems device and control circuit |
| US7821107B2 (en) * | 2008-04-22 | 2010-10-26 | Micron Technology, Inc. | Die stacking with an annular via having a recessed socket |
| US20090296310A1 (en) * | 2008-06-03 | 2009-12-03 | Azuma Chikara | Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors |
-
2007
- 2007-06-22 KR KR1020070061484A patent/KR100907896B1/en not_active IP Right Cessation
-
2008
- 2008-06-17 US US12/140,558 patent/US8053362B2/en active Active
- 2008-06-19 JP JP2008160582A patent/JP4839340B2/en active Active
- 2008-06-19 DE DE102008029194A patent/DE102008029194B4/en not_active Expired - Fee Related
- 2008-06-20 TW TW097123209A patent/TWI362710B/en not_active IP Right Cessation
- 2008-06-23 CN CN2008101004945A patent/CN101330011B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157438A (en) * | 2011-01-31 | 2011-08-17 | 江阴长电先进封装有限公司 | Method for manufacturing wafer-level patch panel |
| CN102157438B (en) * | 2011-01-31 | 2013-05-01 | 江阴长电先进封装有限公司 | Method for manufacturing wafer-level patch panel |
Also Published As
| Publication number | Publication date |
|---|---|
| US20080318410A1 (en) | 2008-12-25 |
| KR100907896B1 (en) | 2009-07-14 |
| JP4839340B2 (en) | 2011-12-21 |
| CN101330011B (en) | 2010-06-02 |
| US8053362B2 (en) | 2011-11-08 |
| JP2009004783A (en) | 2009-01-08 |
| DE102008029194A1 (en) | 2009-02-26 |
| DE102008029194B4 (en) | 2011-05-19 |
| KR20080112724A (en) | 2008-12-26 |
| TW200908179A (en) | 2009-02-16 |
| TWI362710B (en) | 2012-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101330011B (en) | Method of forming metal electrode of system in package | |
| JP5366833B2 (en) | Conductive via formation using electroplating | |
| CN102804370B (en) | There is the microelectronic device and relative manufacturing process that penetrate substrate interconnection | |
| CN100570846C (en) | The implementation method of high, depth and width three-dimensional uprightness interconnect and three dimensional integrated circuits | |
| US6107186A (en) | High planarity high-density in-laid metallization patterns by damascene-CMP processing | |
| US6924224B2 (en) | Method of forming filled blind vias | |
| US8455357B2 (en) | Method of plating through wafer vias in a wafer for 3D packaging | |
| CN102484095B (en) | Vias and conductive routing layers in semiconductor substrates | |
| US9735090B2 (en) | Integrated circuit devices having through-silicon vias and methods of manufacturing such devices | |
| JP3782997B2 (en) | System and method for connecting device chips | |
| US20090071707A1 (en) | Multilayer substrate with interconnection vias and method of manufacturing the same | |
| CN103582942B (en) | Method for forming a vertical electrical connection in a layered semiconductor structure | |
| CN108461477A (en) | Metal interconnection for surpassing the integration of (jump) through-hole | |
| US8486830B2 (en) | Via forming method and method of manufacturing multi-chip package using the same | |
| KR101980871B1 (en) | Method for Processing Metallization in Through Type Through Glass Via | |
| US8913402B1 (en) | Triple-damascene interposer | |
| CN103762184A (en) | Chip package and a method for manufacturing a chip package | |
| CN106206476A (en) | Electronic package and manufacturing method thereof | |
| CN103325700B (en) | A kind ofly realize interconnected method of through hole and products thereof by bottom-up filling | |
| CN109637977A (en) | The groove structure and its manufacturing method of copper filling | |
| CN102959687B (en) | Method for metallising, mixture and electronic device | |
| US20060228934A1 (en) | Conductive materials for low resistance interconnects and methods of forming the same | |
| US20080242078A1 (en) | Process of filling deep vias for 3-d integration of substrates | |
| CN1681119A (en) | IC device and production thereof | |
| CN211045426U (en) | TSV (through silicon via) adapter plate interconnection structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100602 Termination date: 20130623 |