DE102005004365A1 - Conducting structure manufacturing method for integrated circuit arrangement, involves superimposing nucleation layer at base surface or cover surface before or after creation of through-hole, and depositing structure material in hole - Google Patents

Abstract

The method involves creating a through-hole (403) through a substrate of an integrated circuit arrangement, where the hole passes from a cover surface to a base surface of the arrangement. An electrically conductive nucleation layer (402) is superimposed at the base surface or cover surface before or after creating the hole. An electrically conductive material of a conducting structure is galvanically deposited in the hole. An independent claim is also included for an integrated circuit arrangement comprising a conducting structure.

Description

The The invention relates, inter alia, to a method for the production of Lead structures with high aspect ratio in an integrated circuit arrangement. The aspect ratio denotes the ratio between vertical height and smallest lateral dimension of the lead structure.

It object of the invention is a simple method for manufacturing of lead structures in an integrated circuit, which allows, in particular, lead structures with very small lateral Dimensions and with a small electrical resistance. Furthermore an integrated circuit arrangement should be specified.

• – Erzeugen eines Durchgangslochs, durch eine integrierte Schaltungsanordnung hindurch, wobei das Durchgangsloch von einer Deckfläche der Schaltungsanordnung zu einer Bodenfläche der Schaltungsanordnung reicht,
• – vor oder nach dem Erzeugen des Durchgangslochs Aufbringen einer elektrisch leitfähigen Keimbildungsschicht an der Bodenfläche oder an der Deckfläche,
• – galvanische Abscheidung eines elektrisch leitfähigen Materials in dem Durchgangsloch beginnend an der Keimbildungsschicht,

wobei das Durchgangsloch ein Aspektverhältnis größer als 10 oder größer als 100 hat.The object related to the method is solved by a method having the method steps given in claim 1, wherein the following method step is carried out without limitation by the order of listing:

• Producing a through-hole, through an integrated circuit arrangement, wherein the through-hole extends from a top surface of the circuit arrangement to a bottom surface of the circuit arrangement,
• Before or after the production of the through-hole, application of an electrically conductive nucleation layer to the bottom surface or to the top surface,
• Galvanic deposition of an electrically conductive material in the through hole starting at the nucleation layer,

wherein the through hole has an aspect ratio greater than 10 or greater than 100.

Though could the through-hole can also be filled with another method, For example, with a CVD method, but these methods are at through holes with Diameters or a minimum dimension smaller than 10 microns only conditionally applicable, for example because cavities arise in the through hole. The inventive method on the other hand is smaller than 2 microns even with minimum dimensions or even less than 1 micrometer and at said aspect ratios still easy to use. The deposition or filling process with the specified technical effects but is also at minimal lateral dimensions, e.g. Hole diameters, in the range of 1 micron up to 100 nanometers and / or in the range of 100 nanometers to 10 Nanometers and basically also in the range of 10 nanometers to 2 nanometers or smaller used. As a reference plane for the indication of the dimensions serves, for example, a plane which is exactly in the center of the substrate is arranged, which is the finished circuit arrangement wearing.

A sufficiently high current carrying capacity for the currents in integrated Circuits are given even with such minimal dimensions. The current carrying capacity is due to the high conductivity Reason of columnar grain growth further increased. Conversely, they decrease the caused by the ohmic resistance of the Durchgangslochfüllungen Losses. Thus, the method of the invention is different then especially thinking, when the minimum dimensions of the through holes are particularly small.

The Invention goes from consideration that at small minimum dimensions or widths of the lead structure, especially with dimensions less than two micrometers or smaller as a micrometer or less than 500 nanometers, the geometry the copper microstructure and thus especially the mean grain size both determined in interconnects as well as in vias. The with the structure widths decreasing copper grains would to a stronger one shaping lead to the so-called electrical side effect or "size effects", the increase in the resistivity of metallic compounds with describes smaller structure sizes. At the inventive method on the other hand it comes to a targeted growth from the bottom up, especially exclusively in this direction. The result is a columnar or columnar grain structure, at the grains in the vertical direction but also in the lateral direction with the larger lateral Dimension or the longitudinal direction, the e.g. greater than 3 microns is significantly larger as with a lateral growth of the grains. This is due to the fact that the grains hamper each other less in a columnar growth with a lateral growth as well. The larger grains produce less overall Grain boundaries in the conducting structure, so that the electron scattering at grain boundaries leading to an increase lead the resistance would, is reduced.

• – Vias werden von unten her und nicht von den Seiten her aufgefüllt, d.h. sogenannte Bottom-up-Füllung, wodurch neue Anwendungen, z.B. in der Nanoelektronik, erschlossen werden, von denen eine Anwendung weiter unten noch näher erläutert wird,
• – die Keimbildungsschicht lässt sich planar abscheiden, so dass eine Prozessvereinfachung im Vergleich zu konventionellen Verfahren entsteht, bei denen eine Keimbildungsschicht in Vias und Gräben mit kleinen lateralen Abmessungen abgeschieden werden müssen. Beispielsweise liegen die kleinsten lateralen Abmessungen im Bereich kleiner als 200 Nanometer oder kleiner als 100 Nanometer. Die Keimbildungsschicht braucht aufgrund des erforderlichen Stromtransports auch eine bestimmte Mindestschichtdicke, die beispielsweise mehrere Nanometer beträgt, beispielsweise mehr als 5 nm.
• – Durch die Anwendung des erfindungsgemäßen Verfahrens lassen sich größere Kupferkörner durch kolumnares Wachstum erzeugen, was zu einer Verringerung des Widerstands führt, der durch Streuung an Korngrenzen hervorgerufen wird. Dieser Effekt nimmt mit steigendem Aspektverhältnis bzw. mit kleiner werdenden minimalen lateralen Abmessungen zu.
• – Durch den Einsatz des erfindungsgemäßen Verfahrens sind kein "seed repair" bzw. keine ALD-Abscheidung erforderlich,
• – das optimale Wachstum nur von unten im Vergleich zu einem Wachstum auch von der Seite wird beim Elektroplatieren ohne den Zusatz von Additiven im elektrochemischen Bad erreicht, so dass das Galvanisieren stabiler und kostengünstiger durchgeführt werden kann,
• – aufgrund des gerichteten Wachstums lassen sich auch Aussparungen mit einem hohen Aspektverhältnis fehlerfrei füllen.

By means of the present invention, electrically conductive and in particular metallic conductive structures or compounds are produced by targeted growth from bottom to top at predefined locations in a substrate. A lateral growth is avoided. In the invention, the surface of the nucleation layer is only partially exposed - namely only at the locations where the deposition is to take place. For the electrochemical deposition is a continuous Used electrode. The electrode is removed again after electroplating in areas that are not covered by the conductive structures. In these areas, the electrode is thus a sacrificial electrode. By removing the arranged between the conductive structures areas of the sacrificial electrode electrical short circuits between the conductive structures are avoided. The following technical effects result:

• - Vias are filled from below and not from the sides, ie so-called bottom-up filling, whereby new applications, for example in nanoelectronics, are developed, an application of which will be explained in more detail below,
• The nucleation layer can be planarly deposited, resulting in process simplification compared to conventional methods in which a nucleation layer must be deposited in vias and trenches with small lateral dimensions. For example, the smallest lateral dimensions are in the range less than 200 nanometers or less than 100 nanometers. Due to the required current transport, the nucleation layer also needs a certain minimum layer thickness, which is, for example, several nanometers, for example more than 5 nm.
• By using the method according to the invention, larger copper grains can be produced by columnar growth, which leads to a reduction of the resistance, which is caused by scattering at grain boundaries. This effect increases with increasing aspect ratio or with decreasing minimum lateral dimensions.
• By using the method according to the invention, no "seed repair" or no ALD deposition is required,
• The optimum growth only from below compared to a growth also from the side is achieved in electroplating without the addition of additives in the electrochemical bath, so that plating can be carried out in a more stable and cost-effective manner,
• - Due to the directed growth and recesses can be filled with a high aspect ratio error-free.

at a development is the smallest lateral dimension of the through hole less than 10 microns or less than 2 microns or less than 500 nm is. In particular, the inventive method for through holes with minimum dimensions in the range of 20 microns to 100 nanometers or from 10 microns to 500 nanometers. The through holes have, for example. a round, square, rectangular or oval cross-section in a plane that is transverse to the longitudinal axis the through hole is located. The length of the through hole is for example for all specified lateral dimensions greater than 50 microns, greater than 100 micrometers or, for example, in the case of unthinned semiconductor substrates greater than 500 microns.

at one next Continuing the lead structure consists of copper or a copper alloy less than 40 atomic percent additives or with less than 5 atomic percent additives. Copper is because of it huge electrical conductivity especially suitable for three-dimensional wiring. But also other materials are used.

at In a further development, the method according to the invention is separated several times for one first circuit arrangement and separately for a second circuit arrangement carried out. The first circuit arrangement is located on a first substrate, but does not carry the second circuit. Vice versa is the second circuit arrangement on a second substrate, but does not carry the first circuit. Both Substrates are in particular first not mechanically connected to each other. Circuitry performed. The Circuit arrangements are only after the implementation of the Method connected to each other mechanically and electrically conductive, e.g. by bonding, in particular flip-chip bonding, or with help of conductive adhesive.

at an alternative development, at least two circuit arrangements each made on their own substrates. Thereafter, the substrates are stacked stacked. Only then is the inventive method once for the entire Stack executed, in particular by making the through-hole and by the galvanic deposition. Thus, the electrically conductive connections and possibly also the mechanical connection between the substrates produced in this development during galvanizing. This training comes in particular without additional and thus error prone Connection technologies for producing electrically conductive connections out.

at one next Further, the substrates are mechanically fixed during stacking connected to each other, for example, with a connecting means, the between two adjacent substrates is arranged. To connect are known from Waferbonden known techniques. Also sticking is particularly suitable. However, external tensioning devices are also used.

In a development, the through hole is produced after the production of components of the integrated circuit arrangement and preferably also after the production of at least one conductive structure layer of the circuit arrangement. This has the advantage that the integrated circuit arrangement can be tested before performing the electroplating. In addition, the quality of the vertical conductive structure is not affected by the manufacture of the integrated circuit. In one refinement, the conductive structure layer contains interconnects made of a metal, in particular copper, a copper alloy, aluminum or an aluminum alloy.

at an alternative development, the through hole in front of the Production of components of the integrated circuit arrangement or before the production of a conductive structure layer of the circuit arrangement produced and preferably also filled electrically. This alternative prevents in that the integrated circuit arrangement during the production of the through-hole or damaged during electroplating becomes. However, you have to Materials used in the through hole, which has a high melting temperature have, for example, greater than 800 degrees Celsius or greater than 900 degrees Celsius.

The Invention also relates a circuit arrangement, in particular with the inventive method or one of its developments is made. Thus apply the above-mentioned technical effects also for the circuit arrangement or for their Training.

• – ein bspw. einkristallines Substrat, das mindestens ein elektronisches Bauelement oder eine Vielzahl von Halbleiterbauelementen trägt,
• – eine in dem Substrat angeordnete Aussparung bzw. ein das Substrat durchdringendes Durchgangsloch eines Aspektverhältnisses größer als 10 oder größer als 100,
• – eine in der Aussparung bzw. in dem Durchgangsloch angeordneten Leitstruktur,
• – wobei die vertikale Ausdehnung eines Korns der Leitstruktur größer als das Zehnfache oder größer als das 100-Fache der kleinsten lateralen Abmessung der Leitstruktur ist.

The integrated circuit arrangement contains:

• A, for example, single-crystalline substrate which carries at least one electronic component or a multiplicity of semiconductor components,
• A recess arranged in the substrate or a through-hole penetrating the substrate of an aspect ratio greater than 10 or greater than 100,
• A conductive structure arranged in the recess or in the through hole,
• - wherein the vertical extent of a grain of the guide structure is greater than ten times or greater than 100 times the smallest lateral dimension of the guide structure.

at a further education contains the circuit arrangement at least one further, preferably monocrystalline, Substrate, the example. A variety of other semiconductor devices wearing, wherein the conductive structure semiconductor devices of both substrates with each other electrically conductive combines. For example. two, three, four or more than four substrates are stacked on top of each other, each penetrated by recesses or through holes are.

at In a further development, the lead structure extends through at least two substrates. Thus, the inventive method is only once for one Stack made of substrates so that the above technical effects as well for the Circuit arrangement according to this development be valid.

at one next Continuing consists of the conductive structure between the substrates the same material as in the substrates. This too is one Consequence of using a galvanization process to fill a Recess or a through hole, the or at least penetrates two substrates.

at one next Further development of the circuit arrangement is a subarea of a Grains of the conductive structure are arranged in the one substrate and a another portion of the same grain is in the substrate adjacent to this Substrate arranged. Again, this is a consequence of the application of the inventive method to fill a through-hole penetrating two substrates, in particular a consequence of the columnar growth occurring during electroplating. Between the electrically conductive interconnected conductive structures or partial conductive structures adjacent substrates is so besides the continuous conductive structure no additional electrically conductive Connecting means, in particular no solder or conductive adhesive.

in the Below are embodiments of the Invention with reference to the accompanying drawings. In this demonstrate:

1 and 2 Manufacturing stages in the manufacture of a stack of integrated circuit assemblies.

The on hand of the 1 and 2 shown cross sections are respectively in planes, in which also shows the normal direction of a main surface of a semiconductor substrate, wherein in the main surface a plurality of electronic components is arranged, for example of transistors. A lateral direction L is indicated by a double arrow. A vertical direction V is also indicated by a double arrow. The vertical direction V coincides with the normal direction of the main surface.

1 shows a manufacturing stage in the manufacture of an integrated circuit arrangement 399 that is a first semiconductor substrate 400 contains, in particular a single-crystal substrate 400 , eg a silicon substrate. Alternatively, the substrate 400 a substrate made of another material, in particular of an electrically insulating material, for example a glass or ceramic substrate. In the exemplary embodiment, the substrate 400 for example, after a thinning process still 100 microns thick.

In the substrate 400 For example, semiconductor devices have been fabricated on top of OS, which are in 1 but not shown. Also, one or more Leitstrukturlagen, especially metallization layers or interconnect layers, have already been made before the substrate 400 penetrating through holes, eg 403 , be produced with a diameter of, for example, less than 10 microns.

• – sogenannte Vias, d.h. Verbindungen zum überwiegend vertikalen Stromtransport, die in zwei im Winkel von 90° zueinander liegenden lateralen Richtungen beispielsweise die gleiche Ausdehnung haben, und
• – Leitbahnen, d.h. elektrisch leitende Verbindungen, die hauptsächlich zum lateralen Stromtransport in der integrierten Schaltungsanordnung dienen und die deshalb in einer lateralen Richtung eine erheblich größere Ausdehnung haben als in einer zu dieser lateralen Richtung im Winkel von 90° liegenden lateralen Richtung. Beispielsweise sind die Leitbahnen mehr als zweimal so lang bzw. mehr als fünfmal so lang wie breit.

The conductive structures are electrically conductive and are usually made of metal, wherein copper is currently selected. The guiding structures can be differentiated

• - so-called vias, ie connections to the predominantly vertical current transport, which in two at an angle of 90 ° to each other have lateral directions, for example, the same extent, and
• - Conductors, ie electrically conductive connections, which are mainly used for lateral current transport in the integrated circuit arrangement and therefore in a lateral direction have a significantly greater extent than in a lateral direction to this lateral direction at an angle of 90 ° lateral direction. For example, the interconnects are more than twice as long or more than five times as long as they are wide.

The simultaneously produced lead structures are in one Plane parallel to a plane a semiconductor substrate in which a plurality of electronic components is arranged. Both a Via layer and a Leitbahnlage can be also refer to the lead structure situation. The lead structures of a lead structure situation are according to one Draft designed from the draft for one of the relevant Leitstrukturlage different adjacent Leitstrukturlage.

The Lead structures of a layer are embedded, for example, in air-filled cavities or by electrically insulating material from each other and from the lead structures of other Leitstrukturlagen isolated. For isolation In particular, materials with a small relative dielectric constant used, for example, with a dielectric constant less than 3.9, i. so-called low k materials. A distinction is made between via layers and interconnect layers, also referred to as metallization layers become.

Before or after creating the through holes 403 becomes a nucleation layer 402 at the bottom surface of the substrate 400 deposited and used to perform a galvanic process. When performing the galvanic process is in the through holes 403 a through hole filling 404 deposited, in particular also from copper and by columnar growth, ie a growth from "bottom" to "above", ie from the bottom surface of the substrate 400 to the top surface of the substrate 400 ,

For example. After plating, filler projects from the through hole 403 which can be removed in a CMP step or used to make bumps. An additional wiring to be produced or an existing one and through the through-hole filling 404 . 406 contacted wiring of the circuit arrangement 399 leads, for example, from the metallization on the upper side OS to the through-hole filling 404 respectively. 406 at the top OS. This allows the integrated circuit arrangement 399 also be contacted from the back. In a first example of embodiment, the integrated circuit arrangement to be generated contains 399 only the substrate 400 , which is contacted on its top surface and on its bottom surface. The integrated circuit arrangement 399 contains in another embodiment, only one integrated semiconductor device, for example, a power semiconductor device for switching voltages greater than 100 volts or for switching currents greater than 1 ampere.

At the hand of the 2 explained embodiment includes the circuit arrangement 399 however, several substrates 400 and 410 in which through-holes with through-hole fillings 412 . 414 after the above on the hand of the 1 explained methods have been filled. The substrates 400 . 410 become with the help of the Durchgangslochfüllungen 404 . 400 . 414 and 412 contacted, where appropriate, further existing substrates 416 are indicated by a dashed line.

In other embodiments, the through holes become 403 previously optionally still lined with a barrier material on the side walls before the through-hole filling 404 . 406 . 412 respectively. 414 is introduced galvanically. The barrier material is electrically insulating. Alternatively, the barrier material is electrically conductive, but to ensure a columnar growth during plating, for example, by a suitable choice of the chemistry of the plating bath or the electroplating a direct deposition on the electrically conductive barrier layer must be avoided.

In other embodiments, the through holes become 403 even before the production of the semiconductor components or the metallization layers of the integrated circuit on the substrate 400 in the substrate 400 produced and filled by electroplating according to the method explained above. The through holes are generated, for example, by one of the methods given below.

In a further embodiment, the substrates 400 and 410 initially mechanically connected to each other, for example by bonding at the wafer level or on the chip level, wherein a substrate stack is formed. In the substrate stack at least one through-hole is then produced, which penetrates both substrates. Thereafter, only a growth nucleation layer is applied, for example on the substrate 410 but not on the other substrate 400 , Subsequently, both of these become substrates 400 and 410 penetrating through hole filled with a galvanizing process in which both substrates are immersed in the same plating bath and without interrupting the galvanizing. The result is a continuous electrically conductive connection 420 respectively. 421 ,

In summary applies that by the invention novel methods of production of vertically extending hole connections or of nanowires (nanowires) by an electrochemical deposition using a buried and only at predefined areas exposed sacrificial electrode or guide plate can be specified. The invention finds, for example Application in the wiring technology in integrated circuits.

The growth nucleation layer may be used as an electrode and the electroplating or pattern plating may take place selectively. A possible processing is to use a sulfuric acid copper sulfate solution (CuSO ₄ ) as electrolyte at optimum deposition conditions of 20 mA / cm ² . Suitable process parameters are, for example, 0.05 volt, 7 mA (milliamperes), 2 minutes or 0.05 volt, 4 to 5 mA, 1 minute (these are the standard plating conditions). In addition to a constant current flow, a pulsed current flow may also be suitable, wherein the current is pulsed at a constant voltage.

By the generation of vertical connections with high aspect ratio becomes the integration process considerably simplified. The connection structures are produced for example by dry chemical etching and then by applying an electrode in an electrochemical process with a metal filled. As electrode materials in addition to copper and other conductive materials suitable, e.g. Tantalum, titanium, aluminum, tungsten, iron, cobalt, Nickel, ruthenium, good conductive noble materials, in particular noble metals, or also conductive carbon, especially amorphous carbon, for the growth nucleation layers suitable. When deposited in the through-hole during plating Materials are out of the box Copper or copper alloys with less than 5 atomic percent additives as well other conductive Materials suitable, in particular those just mentioned for the nucleation layer Materials, being for Nucleation layer and filling material the same or different materials used become.

The Electrode, for example, by a chemical-mechanical polishing step away. Subsequently The different systems or system units are named after the in the 3D technology (three-dimensional) usual methods on top of each other stacked, e.g. through flip-chip technology, bonding, etc.

• – das sogenannte Bosch-Verfahren, siehe bspw. DE 42 41 045 C1 ,
• – verbesserte Bosch-Verfahren, siehe bspw. DE 197 06 682 ,
• – oder ein Verfahren gemäß WO 99/49506.

Methods for creating trenches or holes with small minimum feature sizes include:

• - The so-called Bosch process, see, for example. DE 42 41 045 C1 .
• - improved Bosch process, see, for example. DE 197 06 682 .
• - or a method according to WO 99/49506.

The holes or trenches For example, by a thinly ground Wafer etched through. Alternatively, after the trenches are created, at least until the trench bottom thinned so that also through holes arise. But drilling methods are also used to create the through holes, in particular laser drilling or drilling with a liquid jet.

One Method for creating through holes with large aspect ratios, e.g. greater than 50, and small diameters, for example. Less than 5 microns or at optimization even smaller than 1 micrometer, is from the book by Volker Lehmann "Electrochemistry of Silicon ", ISBN 3-527-29321-3, et al Page 200 known. Although the Lehmann method was originally used for pore arrays is suitable, it can be modified to produce the isolated through holes are, e.g. through the use of masks, in particular lithographic structured masks.

Next In the above electroplating conditions, other plating methods are also suitable. For example. becomes a thin one Gold layer with a thickness of, for example, less than 200 nanometers used as growth nucleation layer. Optionally, the gold layer on the side facing away from the through hole with a layer of another conductive Reinforced material, For example, with a thicker copper layer whose thickness, for example. More than 5 microns, however, for example, thinner than 100 microns.

• – 220 Gramm/Liter Cu₂SO₄·5H₂O, und
• – 32 Gramm/Liter H₂SO₄.

As galvanizing bath, for example, the following solution is used:

• 220 grams / liter of Cu ₂ SO ₄ .5H ₂ O, and
• - 32 grams / liter H ₂ SO ₄ .

When Anode serves, for example, a copper rod with a diameter of, for example. three millimeters. Optionally contains the copper rod also phosphorus. The gold layer is the cathode. The Potential difference between the two electrodes is, for example. 200 millivolts.

at larger hole diameters, For example, in the micrometer range, the through hole after application the nucleation layer are generated, wherein on the on the nucleation layer bspw. when using an etching process is stopped. In this case, only with respect to the example. Einkri stallinen If there is a via hole, i. a hole that at two facing away from each other surfaces of the substrate openings Has. The through hole runs especially straight.

Becomes the through hole on the other hand before the application of the nucleation layer generated, so the material of the nucleation layer, for example, with a thickness and a method applied which ensure the nucleation layer is one opening of the through-hole fills or closes.

L

lateral direction

V

vertical direction

399

integrated circuitry

400

substratum

401 401b

device layer

402

Nucleation layer

403

Through Hole

404 406

Through-hole filling

410

substratum

412 414

Through-hole filling

416

Further substrates

OS

top

420 421

through connection

Claims (14)

Method for producing a conductive structure ( 404 ) in an integrated circuit arrangement ( 400 ), with the steps: creating a through-hole ( 403 ) through a substrate of an integrated circuit arrangement ( 400 ), wherein the through hole ( 403 ) from a top surface of the circuit arrangement ( 400 ) to a bottom surface of the circuit arrangement ( 400 ), before or after the production of the through-hole ( 403 ) Applying an electrically conductive nucleation layer ( 402 ) on the bottom surface or on the top surface, galvanic deposition of an electrically conductive material ( 404 ) of a conductive structure in the through hole (FIG. 403 ) starting at the nucleation layer ( 402 ), wherein the through hole ( 403 ) has an aspect ratio greater than 10 or greater than 100. Method according to claim 1, characterized in that that the smallest lateral dimension of the through-hole becomes smaller than 10 microns or less than 2 microns or less than 500 nm, in particular, the smallest lateral dimension is in the range from 100 nanometers to 10 nanometers or in the range of 10 nanometers up to 2 nanometers. Method according to claim 1 or 2, characterized in that the lead structure ( 28 . 404 ) consists of copper or a copper alloy with less than 40 atomic percent additives or with less than 5 atomic percent additives. Method according to one of the preceding claims, characterized characterized in that the method separately for at least two arranged on a different substrate circuit arrangements carried out is, and that the circuitry after the implementation of the method electrically conductive with each other get connected. Method according to one of claims 1 to 3, characterized that at least two circuit arrangements on each a different substrate that the substrates are stacked on top of each other, and that the procedure once for running the entire stack becomes. Method according to claim 5, characterized in that that the substrates are mechanically bonded together during stacking be, in particular with a connecting means, between two is arranged adjacent substrates. Method according to one of the preceding claims, characterized characterized in that the through hole after the production of Components of the integrated circuit arrangement and preferably also after the production of at least one Leitstrukturlage the Circuit arrangement is generated. Method according to claim 1, characterized in that that the through hole prior to the manufacture of components of integrated circuit arrangement or before the production of a Power structure of the circuit arrangement is generated. Integrated circuit arrangement ( 399 ), with a substrate ( 400 ), the at least one electronic component ( 401 ), with one in the substrate ( 400 ) arranged recess ( 403 ) of an aspect ratio greater than 10 or greater than 100, with one in the recess ( 403 ) ( 404 ), wherein the vertical extent (V) of a grain of the conductive structure ( 404 ) is greater than ten times or greater than 100 times the smallest lateral dimension of the lead structure. Circuit arrangement ( 399 ) according to claim 9, characterized by a further substrate ( 410 ) bearing at least one other electronic component, the conductive structure ( 404 ) Components of Both Substrates ( 400 . 410 ) connects to each other electrically conductive. Circuit arrangement ( 399 ) according to claim 9 or 10, characterized in that the conductive structure through at least two substrates ( 400 . 410 ). Circuit arrangement ( 399 ) according to claim 11, characterized in that the conductive structure between the substrates ( 400 . 410 ) consists of the same material as in the substrates ( 400 . 410 ). Circuit arrangement ( 399 ) according to claim 12, characterized in that a partial region of a grain of the conductive structure in the one substrate ( 410 ) and that a different portion of the same grain in the substrate adjacent to this substrate ( 400 ) is arranged. Circuit arrangement ( 10 . 400 ) according to one of claims 9 to 13, characterized in that the circuit arrangement ( 10 . 400 ) has been prepared by a method according to any one of claims 1 to 8.