CN102157438B

CN102157438B - Method for manufacturing wafer-level patch panel

Info

Publication number: CN102157438B
Application number: CN 201110033791
Authority: CN
Inventors: 张黎; 赖志明; 陈栋; 陈锦辉
Original assignee: Jiangyin Changdian Advanced Packaging Co Ltd
Current assignee: Jiangyin Changdian Advanced Packaging Co Ltd
Priority date: 2011-01-31
Filing date: 2011-01-31
Publication date: 2013-05-01
Anticipated expiration: 2031-01-31
Also published as: CN102157438A

Abstract

The invention relates to a method for manufacturing a wafer-level patch panel, belonging to the technical field of integrated circuit or discrete device package. The method comprises the following steps of: taking a carrier wafer; sputtering or chemically plating a metal conductive layer on the carrier wafer; forming a mask graphic opening on the metal conductive layer; filling metal in the mask graphic opening; forming a metal cylinder array on the surface of the carrier wafer; filling the metal cylinder array of the whole carrier wafer with a substrate material of the patch panel to form a wafer with the metal cylinder array; separating the wafer from the carrier wafer; corroding the metal conductive layer on the wafer; and forming metal re-wiring graphs on the two surfaces of the wafer, and protecting the metal re-wiring graphs and forming metal re-wiring protection layers and opening graphs. Through the method for manufacturing the wafer-level patch panel, disclosed by the invention, the difficulty and the cost of the process can be greatly reduced, and the scale production of a high-density patch panel process can be achieved.

Description

The preparation method of wafer-level patch panel

Technical field

The present invention relates to a kind of preparation method of wafer-level patch panel.Belong to integrated circuit or Discrete device packaging technical field.

Background technology

In recent years, along with the high speed development of Electronic Encapsulating Technology, the new packing forms of some constantly occurs.As based on the crystal wafer chip dimension encapsulation of disk, three-dimensional stacked encapsulation technology and flip-chip packaged technology etc.The appearance of these novel encapsulated technology has not only promoted the service behaviour of chip, has also greatly saved package dimension and volume.

Be subject to the factor of chip size and unfailing performance, the range of application of Wafer-Level Packaging Technology also is confined to the product of some low pin numbers.In the three-dimensional stacked technology, although Bonding can be realized multiple-level stack, be limited by lead-in wire line length and diameter in the application facet of high speed transmission of signals module, thereby large-area use or at aspects such as flash memory, smart card, radio frequency identification.And some high speed processing chips still carry out in the upside-down mounting mode such as the packing forms of central bit processor (CPU), graphic process unit (GPU), chipset (Chipset) etc.The keyset of present upside-down mounting mainly contains:

1) BT resinoid base keyset;

2) ceramic base keyset;

3) with the silica-based keyset of silicon through hole.

Wherein BT resinoid base keyset and ceramic base keyset are subjected to process technology limit in metal line, and its live width line-spacing is larger, can't satisfy application requirements in the design of high-density package structure.Silica-based keyset with the silicon through hole adopts the mode of filling metal in the silicon through hole, mode with disk is carried out metal line, can realize fine linewidth and line-spacing structure, can realize highdensity switchover capability, its technical process such as Figure 12 ~ shown in Figure 22, this technique has two large difficult points:

1) through hole forms, and common through hole generation type is to utilize the method for deep reaction ion etching, thereby it is lower to form efficient, and because of the etching process governing factor, the through-hole wall of formation is the scallop structure;

2) dielectric layer deposition difficulty.Be to guarantee the insulating properties between silicon and the via metal, need at through-hole wall deposition one dielectric layer, but just seem very difficult because of the deposition of the minimum dielectric layer of clear size of opening;

3) via metal is filled difficulty.Because it is to deposit in advance the Seed Layer metal in through hole that via metal is filled, and then adopts electroplating technology to carry out, this mode is difficult to avoid cavity blemish (growth characteristics of plated metal) in the through hole.

Based on the reason of above-mentioned three aspects:, utilize the silica-based keyset technology of silicon through hole technology also not possess the large-scale production ability.

Summary of the invention

The object of the invention is to overcome the deficiency of the silica-based keyset technology of above-mentioned silicon through hole, a kind of preparation method's method that is applicable to the wafer-level patch panel of high-density packages is provided.

The object of the present invention is achieved like this: a kind of preparation method of wafer-level patch panel, and described method comprises following processing step:

Step 1, get the carrier disk;

Step 2, form release agent at the carrier disk, again metal conducting layer on sputter on the release agent or chemical plating;

Step 3, stick or apply mask material at metal conducting layer, the mode by photoetching or laser forms the mask pattern opening at mask material;

The mode that step 4, utilization are electroplated is filled metal in the mask pattern opening, form metal column in the mask pattern opening;

Step 5, lift-off mask material, the carrier disk surfaces of metal conducting layer forms the metal column array on sputter or chemical plating;

Step 6, utilize the mode seal that the keyset basis material is filled up the metal column array of whole carrier disk, form the disk with the metal column array;

Step 7, will break away from the disk of metal column array and carrier disk;

Step 8, erode the metal conducting layer of staying with on the disk of metal column array;

Step 9, form again wiring pattern of a metal on the surface with the disk of metal column array that erodes metal conducting layer, this metal is wiring pattern and described metal column array interconnect again, and is protected and form a metal connect up protective layer and opening figure again;

The metal column array is exposed on another surface of the described disk with the metal column array of step 10, rubbing down step 9;

Step 11, form again wiring pattern of another metal on another surface of the disk that exposes the metal column array, this metal again wiring pattern also with described metal column array interconnect, and protected and formed another metal connect up again protective layer and opening figure.

Theory of the present invention is to be pre-formed the metal column array by plating; then by the mode of plastic packaging array is protected; formation is with the disk with the metal column array of metal column array, and then carries out again Wiring technique complete design figure at the disk with the metal column array.Why adopt this technique and method, in order to avoid via etch and filling process, simultaneously, the mode that employing is sealed is integrated plastic packaging material or category of glass dielectric layer and metal column and is formed the new disk with the metal column array with metal column, avoid the depositing operation of dielectric layer, reduced technology difficulty and cost.

The invention has the beneficial effects as follows:

The preparation method of wafer-level patch panel of the present invention, greatly reduction technology difficulty and the process costs of degree can be realized the large-scale production of high density patching plate technique.

Description of drawings

Fig. 1 ~ Figure 11 is that wafer-level patch panel of the present invention forms each operation instance graph of technique.

Figure 12 ~ Figure 22 is existing each operation representative instance figure of silica-based keyset packaging technology.

Reference numeral among the figure:

Keyset matrix 1-1, metal column array 1-2, metal be wiring pattern 1-3A, metal connect up again protective layer and opening figure 1-4A, metal connect up again protective layer and opening figure 1-4B, carrier disk 2-1, release agent 2-2, metal conducting layer 2-3, mask material 2-4, mask pattern opening 2-5 of wiring pattern 1-3B, metal more again;

Silicon substrate T-1, mask material and opening T-2-1/T-2-2, through hole T-3, through hole and surface passivation layer T-4, plated metal Seed Layer T-5, via metal T-6, again wiring metal T-7A, protective layer T-8A, base dielectric layer T-9, again wiring layer T-7B, protective layer T-8B.

Embodiment

Referring to Fig. 1 ~ Figure 11, Fig. 1 ~ Figure 11 is that wafer-level patch panel of the present invention forms craft embodiment figure.Can be found out by Fig. 1 ~ Figure 11, wafer-level patch panel preparation method of the present invention, described method comprises following processing step:

Step 1, get carrier disk 2-1, such as Fig. 1;

Step 2, form release agent 2-2 at carrier disk 2-1, release agent 2-2 is generally sulfide and chromate etc., and metal conducting layer 2-3 on sputter or chemical plating on the release agent 2-2 such as Fig. 2, its objective is that doing conduction for next step electroplating technology prepares again;

Step 3, stick or apply mask material 2-4 at metal conducting layer 2-3, mask material 2-4 adopts thick dry film or thick colloidal substance, and the mode by photoetching or laser forms mask pattern opening 2-5 at mask material 2-4, such as Fig. 3;

The mode that step 4, utilization are electroplated is filled metal in mask pattern opening 2-5, form metal column in mask pattern opening 2-5, and such as Fig. 4, usually filling metal is copper, silver or its alloy material;

Step 5, lift-off mask material 2-4, the carrier disk 2-1 of metal conducting layer surface forms metal column array 1-2 on sputter or chemical plating, such as Fig. 5;

The mode that step 6, utilization are sealed is filled up keyset matrix 1-1 material the metal column array 1-2 of whole carrier disk, such as Fig. 6, formation is with the disk of metal column array, for keeping electrical insulating property, the keyset material require is considered preferably dielectric property, simultaneously the good strength of materials should be arranged, the thermal coefficient of expansion that is complementary with the metal column array, as the plastic packaging material with dielectric function, or the glass dielectric medium, need not to add dielectric layer in interconnecting metal post junction;

Step 7, will break away from the disk of metal column array and carrier disk 2-1, such as Fig. 7;

Step 8, erode the metal conducting layer 2-3 that stays with on the disk of metal column array, such as Fig. 8;

Step 9, form again wiring pattern 1-3A of a metal on the surface with the disk of metal column array that erodes metal conducting layer, this metal is wiring pattern 1-3A and described metal column array 1-2 interconnection again, and protected and form a metal connect up again protective layer and opening figure 1-4A, such as Fig. 9;

Metal column array 1-2 is exposed, such as Figure 10 in another surface of the described disk with the metal column array of step 10, rubbing down step 9;

Step 11, another surface of disk with the metal column array behind rubbing down form again wiring pattern 1-3B of another metal; this metal again wiring pattern 1-3B also with described metal column array 1-2 interconnection, and protected and formed another metal connect up again protective layer and opening figure 1-4B.

Referring to Figure 12 ~ Figure 22, Figure 12 ~ Figure 22 is existing each operation representative instance figure of silica-based keyset packaging technology.Figure 12 is silicon substrate T-1; Figure 13 forms mask material and opening T-2-1/T-2-2 at silicon substrate T-1; Figure 14 is that deep reaction ion etching forms through hole T-3; Figure 15 is for removing mask material; Figure 16 is for utilizing PCVD through hole and surface passivation layer T-4; Figure 17 is sputtering sedimentation plated metal Seed Layer T-5; Figure 18 is that plated metal is with filling vias metal T-6; Figure 19 is for removing an electroplated metal layer; Figure 20 is for forming wiring metal T-7A, protective layer T-8A and opening thereof in one side again; Figure 21 is that the rubbing down another side exposes metal T-6; Figure 22 is for to form wiring layer T-7B and protective layer T-8B and opening thereof at another side again.

Claims

1. the preparation method of a wafer-level patch panel, it is characterized in that: described method comprises following processing step:

Step 1, get the carrier disk;

The mode that step 6, utilization are sealed is filled up the keyset basis material metal column array of whole carrier disk, formation is with the disk of metal column array, described keyset basis material has preferably dielectric property, simultaneously the good strength of materials should be arranged, the thermal coefficient of expansion that is complementary with the metal column array;

Step 7, will break away from the disk of metal column array and carrier disk;