CN101325217B - 一种半导体结构 - Google Patents
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Abstract
本发明涉及一种半导体结构,至少包含一半导体衬底;一半导体衬底上的栅极堆栈;一至少有一部分位于半导体衬底内且和栅极堆栈相邻的外延区,其中外延区包含锗化硅以及具有第一导电性类型的杂质,该第一导电性类型为P型或N型;半导体衬底的第一部分邻接于外延区,其中半导体衬底的第一部分具有该第一导电性类型;半导体衬底的第二部分邻接于第一部分,半导体衬底的第二部分具有相对于该第一导电性类型的第二导电性类型,该第二导电性类型为N型或P型;一硅化金属区形成于外延区和半导体衬底的第一部分和第二部分上。
Description
技术领域
本发明涉及一种半导体器件,且特别涉及一种具有锗化硅区的金属氧化物半导体(MOS)器件的结构。
背景技术
近几十年来,半导体器件(例如:金属氧化物半导体器件)的尺寸缩小,不断改善了集成电路的速度、性能、密度和单价。根据晶体管设计和其内部特征,调整晶体管栅极下方沟道区的长度来改变结合沟道区的电阻,由此提高晶体管效率。更确切地说,假如其它参数维持一定,缩短沟道区的长度可降低晶体管源极到漏极的电阻,当晶体管栅极具有充足电压时,将会引起源极和漏极之间的电流增加。
在改良MOS器件上,若施加电压于MOS器件的沟道区上可改善载流子的移动率。一般而言,希望能在N型金属氧化物半导体(NMOS)器件的沟道区感应出一个从源极到漏极方向的拉伸应力,而在P型金属氧化物半导体(PMOS)器件的沟道区感应出一个从源极到漏极方向的挤压应力。
一般将挤压应力应用在PMOS器件沟道区上的常用方法为使锗化硅应力源在源极和漏极区生长。常见方法如,半导体衬底上的栅极堆栈成型;栅极堆栈侧壁的栅极间隙壁成型;锗化硅应力源在凹槽内的外延生长。由于锗化硅比硅具有更高的晶格常数,由此提供一挤压应力给位于锗化硅源极的应力源和锗化硅漏极的应力源之间的沟道区上。同样地,碳化硅应力源可施加到NMOS器件上。由于碳化硅的晶格常数比硅小,因此可将拉伸应力应用于沟道区上。
图1示出一常用电路图。其中包含PMOS器件2和4与公用的共源极6。PMOS器件2包含栅极多晶硅7和漏极区8。PMOS器件4包含栅极多晶硅9和漏极区10。PMOS器件2和4使用传统应力源成型过程形成,共源极6与漏极区8和10为锗化硅应力源。为保护芯片区(chip area),连接共源极6的方式采用软连接(soft connection)法,该连接包含有锗化硅线12、与锗化硅线12相连接的N+型区14和接触(Contact)16。锗化硅线12与共源极6和漏极区8和10同时成型。硅化金属层(图中未示)形成于N+型区14、锗化硅线12、共源极6和漏极区8和10上。
然而传统应力源成型过程有缺陷。图2示出沿图1中A-A’线的结构横截面图,硅化金属层18在共源极6、锗化硅线12和N+型区14上方形成。其中位于锗化硅线12和N+型区14之间的一分界面区(interface region)为区19,该区19上的硅化金属层18的厚度比其它区还要薄。而这极有可能与和锗相比,金属更易于与硅形成硅化物的事实有关。
减少在区19中的硅化金属层18的厚度,将会引起薄层电阻末端(sheetresistance tailing)生成。理论上,假设测量多个具有图1和图2所示的结构的试样,那么在无末端效应(Tailing effect)的情况下,试样的薄层电阻应该在相对小的范围内。假设在有末端效应的情况下,那么大多数的试样将具有很高的薄层电阻。目前已知,薄层电阻与集成电路的RC延迟直接相关。而末端效应将会引起RC延迟的增加,并可能引起集成电路的功能破坏。这些问题则需要加以解决。
发明内容
本发明所要解决的技术问题在于提供一种具有锗化硅区的金属氧化物半导体结构,避免现有半导体结构中末端效应的产生。
为了实现上述目的,本发明提出一种半导体结构,包含半导体衬底;一个位于半导体衬底上的栅极堆栈;一个至少有一部分位于半导体衬底内且邻接于栅极堆栈的外延区,其中外延区包含锗化硅以及具有第一导电性类型的杂质,该第一导电性类型为P型或N型;半导体衬底的第一部分邻接于外延区,其中半导体衬底的第一部分具有该第一导电性类型;半导体衬底的第二部分邻接于第一部分,其中半导体衬底的第二部分具有相对于该第一导电性类型的第二导电性类型,该第二导电性类型为N型或P型;以及在外延区和半导体衬底的第一和第二部分上的硅化金属区。
为了实现上述目的,本发明还提出一种半导体结构,包含一半导体衬底;一半导体衬底上的栅极;一个在半导体衬底上的锗化硅区。锗化硅区包含一与栅极邻接的第一部分,一与第一部分邻接的第二部分;第二部分的宽度比第一部分的宽度小。半导体结构还包含有一个重掺杂P型区邻接于锗化硅区的第二部分,其中重掺杂P型区的宽度与锗化硅区的第二部分大致相同;上升区(Pickup region)邻接于重掺杂P型区,其中上升区是N型;以及一硅化金属区,位于该锗化硅区、重掺杂P型区和上升区上。
为了实现上述目的,本发明又提出一种半导体结构,包含半导体衬底;一第一P型金属氧化物半导体(PMOS)器件,包含一在半导体衬底上的第一栅极多晶硅;一第二PMOS器件,包含一在半导体衬底上的第二栅极多晶硅,其中第一与第二栅极多晶硅相互平行;一锗化硅区,邻接于第一与第二栅极多晶硅之间,锗化硅区具有第一宽度;一锗化硅延伸区,邻接于锗化硅区;一P+型区,邻接于锗化硅延伸区;一N+型延伸区,邻接该P+型区,其中锗化硅延伸区、P+型区和N+型区均具有第二宽度,其小于该第一宽度;一上升区,邻接于N+型延伸区,其中该上升区为N+型区;以及一硅化金属区,位于该锗化硅延伸区、P+型区、N+型区,和上升区上。
将P+型区插入N+型区与锗化硅区之间,可使薄层电阻的末端效应降低。
为让本发明的上述和其它目的、特征、优点与实施例更加明显易懂,以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1示出传统半导体结构,其中软连接使上升区与锗化硅区电气连接;
图2示出图1所示结构的横截面;
图3示出根据本发明的一较佳实施例,其中将一P+型区插入于N+上升区和锗化硅区之间;
图4到图8示出图3所示的实施例的中间阶段;
图9示出根据本发明的另一替代实施例。
【主要器件符号说明】
2:PMOS器件 4:PMOS器件
6:共源极 7:栅极多晶硅
8:漏极区 9:栅极多晶硅
10:漏极区 12:锗化硅线
14:N+型区 16:接触
18:硅化金属层 19:问题区
20:PMOS器件 22:PMOS器件
24:栅极多晶硅 26:栅极多晶硅
28:共源极区 30:漏极区
32:漏极区 34:锗化硅区
38:有源区 39:接触
42:有源区 40:有源区
45:掩膜 43:P型掩膜
48:N型掩膜边界 46:非导体区
52:P型掩膜边界 50:N+上升区
56:原有源区边界 54:P型掩膜延伸区边界
62:栅极间隙壁 60:P+型区
66:层间介电层 64:硅化金属层
70:源/漏极区 68:硅化金属区
具体实施方式
以下详细描述本发明较佳实施例的制造与使用。然而应可理解的是,本发明提供诸多可应用的发明概念,其能具体化于各种特定内容中。所描述的特定实施例仅以特定形式说明制造及使用本发明,并非用以限制本发明的范围。
请参照图3,其示出本发明一较佳实施例。
PMOS器件20包含漏极区30、共源极区28和栅极电极24,该栅极电极24可由多晶硅形成。在全文叙述中,MOS器件的栅极电极均为栅极多晶硅,虽然其也可由其它导电材料如金属、硅金属和二者的组合形成。PMOS器件22包含共源极区28,漏极区32和栅极多晶硅26。栅极间隙壁62形成于栅极多晶硅24和26的侧壁上。漏极区30、32和共源极区28由锗化硅形成。共源极区28还代表锗化硅区28。
共源极区28的连接是一种软连接,包含N+上升区50。一个窄掺杂区包含掺杂锗化硅区34和P+型区60,并连接N+上升区50和共源极区28。在区28、30、32、34、50和60上形成有一硅化金属层(图中未示)用以改善连接。接触39电气连接硅化金属层与金属化层(图中未示)。
图4到图8示出图3所示的结构成型的中间阶段。图4示出初始结构的俯视图。非导体区46形成于半导体衬底中,限定半导体衬底上的有源区38、40和42。例如非导体区46包含浅沟渠绝缘(STI)区。有源区38、40和42形成一连续区。有源区42比有源区38和40狭窄。在实施例中,有源区42的宽度W1小于0.3μm,或优选的小于0.1μm,更优选的小于0.08μm。有源区42的长度L1优选的小于0.25μm,或者更优选的介于0.1μm到0.2μm之间。
栅极多晶硅24和26形成于有源区40上。如本领域所公知的,栅极介电层(图中未示)形成于栅极多晶硅24和26以及有源区40的下方。栅极多晶硅24和26以及栅极介电层的形成过程为本领域的公知方法,在此不再说明。
参照图5,在有源区38掺杂注入N型杂质,例如磷、砷和二者的组合。结果形成N+上升区50。在形成N+上升区50中、N型掩膜41(以点阴影表示)覆盖住整个有源区40和至少一部分的有源区42,但留下有源区38和非导体区46的部分周围呈现暴露状态以进行离子注入。优选地,暴露区为一个矩形。N型掩膜41包含光刻材料、氮化硅或其它常用的掩膜材料。在实施例中,上升区50有一浓度高于1E20/cm3的杂质。优选地,上升区50稍微延伸至有源区42,例如以一小于0.05μm的距离D1。
图6示出锗化硅区的形成。形成P型掩膜43覆盖住有点区并留下开放的无点区。根据较佳实施例可知,P型掩膜43残留出一个矩形区,但不包含已延伸入矩形区的P型掩膜43延伸区。大致上,P型掩膜43具有一边界52已替代重叠覆盖在N型掩膜41的边界48上(如图5所示)。P型掩膜43延伸区最好具有一大于0.06μm的长度L2。P型掩膜43延伸区的宽度W2最好远大于有源区42的宽度W1。最好,在有源区42的两侧,P型掩膜43延伸区能延伸并超过有源区42大于0.08μm作为余边。P型掩膜43延伸区的边界54最好与原有源区40的边界56分开,举例来说,大于0.08μm。这样可避免发生P型掩膜43延伸区与有源区40最近的边界产生非常小距离的分离。在本例中,在后续的工艺步骤中,位于边界54和56之间的有源区42部分将有可能不会完全地填满锗化硅。
在本发明的较佳实施例中,P型掩膜43是通过将无延伸区的传统掩膜应用于逻辑操作(logic operations,LOP)形成。通过LOP,P型掩膜的边界根据需要可以进行修改。
锗化硅区使用P型掩膜43形成。如本领域所公知的,凹槽首先形成于暴露的有源区40和42中(如图5所示)。半导体材料(较佳为锗化硅)以选择性外延生长(SEG)法在凹槽中外延生长,形成共源极区28和漏极区30和32。
在下列工艺步骤中,如图7A所示,P型掩膜43已去除,形成栅极间隙壁62。形成掩膜45(以点图表示)以覆盖一矩形区,除了未移除的延伸区,该矩形区与P型掩膜43相似。然后完成P型离子注入。因此,锗化硅区28、30和32有P型杂质的注入。位于N+上升区50和共源极区28之间的区60形成一个P+型区。优选地,P+型区60的P型杂质浓度远高于1E20/cm3。
图7B示出沿图7A中B-B’线的结构横截面图。图7C示出沿C-C’线的横截面图,优选地,锗化硅区28、30和32的上表面高于P+型区60和N+上升区50的上表面。
图8示出硅化金属层64、层间介电层(inter-layer dielectric,ILD)66和接触39的形成,其中图8是沿图7A中C-C’线的横截面图。如本领域所公知的,硅化金属层64以毯覆式(blanket)形成金属层(图中未示),利用晶片退火引起金属层和下方的硅或锗化硅之间的反应,然后去除未反应的金属层进而留下硅和/或锗化硅。接下来,形成ILD66且接触39也跟着在ILD66中形成。接触39将覆盖在上方的金属化层(图中未示)与硅化金属层64连接,该硅化金属层64进一步与共源极区28连接。
当电流流过接触39和共源极区28之间时,电流会生成一条带有低电阻路径的硅化金属层64。一般而言,接近锗化硅区28的边界(侧壁)的硅化金属区68会比其它部位还薄。其结果将由于硅化金属区68的薄层电阻远大于硅化金属层64的其它部分而导致末端效应(Tailing effect)的产生。有利的是,因为P+型区60和锗化硅区28为相同的导电性类型,除硅化金属区68外,电流还会流过P+型区60和锗化硅区28。因此减少薄层电阻产生。由前所述,末端效应可有效的减少,甚至有可能完全消除。相比之下,在不包括P+型区60的传统结构中,N+型区50将会与锗化硅区28邻接且形成N-P结,阻碍电流流向锗化硅区28,由此末端效应产生。
图9示出根据本发明的另一实施例,其中PMOS器件的源/漏极区邻接于STI区46而非另一个PMOS器件。然后,上升区50形成,且通过P+型区60与源/漏极区70相连。上升区50和P+型区60的形成和尺寸必须与图3到图8所示的实施例中的相同。
本发明的较佳实施例可应用于NMOS器件的形成,其中包含用于给MOS器件的各沟道区施加拉伸应力的碳化硅应力源。该结构与图3和图9所示的结构相似,除了所述的区的类型相反,以及锗化硅区被碳化硅区代替。优选地,N+型注入区邻接碳化硅应力源和P+型上升区形成。
虽然已详细描述了本发明及其优点,但应该理解,在不脱离所附权利要求所限定的本发明的精神与范围的情况下,可以进行各种改变、替代物和替代法。另外,本发明的范围也不局限于说明书中所描述的工艺、机械、制造、要素组成、方式、方法以及步骤的特定实施例。从本发明的公开范围中,本领域的普通技术人员将会理解,与在此描述的相应的实施例执行大体上相同功能或达到大体上相同的结果的、已存在或以后将被开发的工艺、机械、制造、要素组成、方式、方法或步骤可以根据本发明加以利用。因此,所附权利要求书旨在包含该工艺、机械、制造、要素组成、方式、方法或步骤的范围。
Claims (11)
1.一种半导体结构包含:
一半导体衬底;
一栅极堆栈,位于该半导体衬底上;
一外延区,至少有一部分位于该半导体衬底内,且和该栅极堆栈相邻,该外延区包含锗化硅以及具有第一导电性类型的杂质,该第一导电性类型为P型或N型;
一半导体衬底的第一部分,邻接于外延区,该半导体衬底的第一部分具有该第一导电性类型;
一半导体衬底的第二部分,邻接于第一部分,该半导体衬底的第二部分具有相对于该第一导电性类型的第二导电性类型,该第二导电类型为N型或P型;以及
一硅化金属区,位于外延区和半导体衬底的第一部分和第二部分上。
2.根据权利要求1所述的半导体结构,其特征在于,还包含一个接触,该接触与直接位于半导体衬底的第二部分上的硅化金属区的一部分连接。
3.根据权利要求1所述的半导体结构,其特征在于,该半导体衬底的第一部分的宽度小于外延区的宽度和半导体衬底的第二部分的宽度。
4.根据权利要求3所述的半导体结构,其特征在于,该半导体衬底的第一部分的宽度小于0.1μm。
5.根据权利要求3所述的半导体结构,其特征在于,该外延区还包括一邻接于该半导体衬底的第一部分的附加部分,而该附加部分的宽度与半导体衬底的第一部分的宽度相等。
6.一种半导体结构包含:
一半导体衬底;
一栅极,位于该半导体衬底上;
一锗化硅区,位于该半导体衬底上,其中该锗化硅区包含一邻近于该栅极的第一部分以及邻接于该第一部分的第二部分,该第二部分的宽度小于第一部分的宽度;
一重掺杂P型区,邻接于该锗化硅区的第二部分,其中该重掺杂P型区的宽度与该锗化硅区的第二部分的宽度相同;
一上升区,邻接于该重掺杂P型区,该上升区为N型;以及
一硅化金属区,位于该锗化硅区、重掺杂P型区和上升区上。
7.根据权利要求6所述的半导体结构,其特征在于,该锗化硅区的第二部分的长度大于0.1μm。
8.根据权利要求6所述的半导体结构,其特征在于,该锗化硅区的第二部分的宽度小于0.08μm。
9.根据权利要求6所述的半导体结构,其特征在于,至少包含一浅沟渠绝缘区,连接于该锗化硅区的第一部分上与该栅极相对的一面。
10.一种半导体结构包含:
一半导体衬底;
一第一PMOS器件,包含一第一栅极多晶硅位于该半导体衬底上;
一第二PMOS器件,包含一第二栅极多晶硅位于该半导体衬底上,其中该第一与第二栅极多晶硅相互平行;
一锗化硅区,介于并邻接该第一和第二栅极多晶硅之间,该锗化硅区具有第一宽度;
一锗化硅延伸区,邻接于该锗化硅区;
一P+型区,邻接于该锗化硅延伸区;
一N+型延伸区,邻接于该P+型区,且该锗化硅延伸区、P+型区和N+型区具有相同的第二宽度,其小于该第一宽度;
一上升区,邻接于该N+型延伸区,该上升区是N+型区;以及
一硅化金属区,位于该锗化硅延伸区、P+型区、N+型区,和上升区上。
11.根据权利要求10所述的半导体结构,其特征在于,还包含:
一接触,物理连接于该硅化金属区,其中该接触直接位于上升区上。
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