CN101310389A - 金属基极纳米线晶体管 - Google Patents
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Abstract
在此提出一种金属基极晶体管。该晶体管包括第一和第二电极(2，6)、以及控制第一和第二电极之间的电流的基极电极(6)。第一电极(2)由半导体材料制成。基极电极(3)是沉积在形成第一电极的半导体材料上面的金属层。根据本发明，第二电极由与基极电极(3)电接触的半导体纳米线(6)形成。
Description
技术领域
本发明涉及一种晶体管，该晶体管具有由金属制成的基极电极、以及由半导体纳米线形成的发射极或集电极。
背景技术
几十年前，金属基极晶体管(MBT)已经作为高速器件被提出。希望MBT能够实现比双极结晶体管更高的性能。通过使用硅(Si)作为发射极，金(Au)作为基极，以及锗(Ge)作为集电极来获得MBT的最佳性能。然而，MBT概念理论上的优点并不能在商业化的器件中实现，这主要是因为制造这样的器件存在困难。具体地讲，难以在基于金属的层上获得单晶体半导体层。因此，一方面，直到现在MBT仍然不能替代双极结晶体管来作为高速器件。另一方面，由于晶体管结构在纵向上规模下降，使得近年来双极晶体管在性能方面有极大进展。即，近年来形成纵向晶体管结构的半导体层的厚度被做得越来越薄。这样的结果可以被解释为如下：由于电荷载体的传输速度受限，导致存在与在形成晶体管的多个层上的信号传输相关的固有的延迟时间或传输时间。通过降低这些层的厚度，传输时间也会降低。当今，双极器件受到发射极-基极结的电荷存储的限制。相关的电容连同微分输入电阻导致的延迟占现代双极晶体管的全部延迟的50％以上。尽管已经有了进步，但是仍然需要更快的晶体管。
发明内容
因此，本发明提出了一种金属基极晶体管，这是因为它在基极的耗尽层中存储了很少的电荷。而且，取决于用于制作MBT的专门加工技术，其可降低对耗尽层中的缺陷的灵敏度。
具体地讲，本发明提出了一种晶体管，该晶体管包括第一和第二电极、以及控制第一和第二电极之间的电流的基极电极。第一电极由半导体材料制成。基极电极是沉积在形成第一电极的半导体材料上的金属层。根据本发明，第二电极由与基极电极接触的半导体纳米线形成。
纳米线是具有纳米(nm)级直径的结构，而在纵向其可具有微米(μm)级长度。由于其在横向上尺寸较小，量子力学效应会起很大作用。因此，纳米线有时也被称作“量子线”。
在本发明的一个实施例中，基极由过渡金属硅化物制成。更具体地讲，可从钴和镍组成的组中选择过渡金属。有利的是，纳米线随后可在基极电极上生长。
在本发明的一个实施例中，纳米线由硅和/或锗制成。在此情况下，纳米线可由半导体异质结构组成。
对于一些应用而言，纳米线异质结构的成分在纳米线的径向上改变是有用的。
对于其它应用而言，纳米线异质结构的成分在纳米线的轴线方向上改变是有用的。
附图说明
通过阅读以下有关附图的描述，本发明将会变得更好理解，并且其它特征和优点将变得更清楚。
图1是根据本发明的金属基极晶体管的示意图；
图2是图1所示的晶体管的能带示意图；以及
图3a至3e显示了制造步骤的顺序以制造图1所示的金属基极晶体管。
具体实施方式
图1示出了根据本发明的金属基极晶体管的实施例的示意图。注意，图1的尺寸不是按比例的，而且仅仅是以说明性的目的给出的。以下将首先描述该晶体管的结构。其后再描述制造晶体管的一种可能的方法。
在图1中，晶体管作为一个整体由标号1表示。晶体管1布置在形成衬底2的高n掺杂硅晶片之上。尽管掺杂级的精确值取决于所选的材料以及它们的相关能带结构(band alignments)，但是，在本实施例中，掺杂级约为10-19cm-3水平。在衬底2上布置薄单晶体金属层3。该金属层3是类似于CoSi2或NiSi2的金属硅化物，并且具有nm级的厚度。由通过浅沟渠绝缘方式制成的绝缘区域4横向构成晶体管1。金属层3的顶部与直接生长在金属层3之上的纳米线6接触。通常，该纳米线的直径小于100nm，并且不长于500nm。该纳米线由类似于硅(Si)的单一半导体制成，或者由类似于硅和锗(Si，Ge)的不同的半导体材料制成。类似于衬底2，纳米线6是高n掺杂的。电介质隔离层7沉积在上述器件之上，起到保护的作用。最后，在电介质隔离层7中的窗口中提供欧姆接触，以形成与纳米线6接触的发射极触点8、与金属层3接触的基极触点9、和与衬底2接触的集电极触点10。
由于衬底2和纳米线6都是高n掺杂半导体材料，所以它们在晶体管1中的作用是可以互换的。即，在本发明的另一实施例中，纳米线6是晶体管的集电极，衬底2是晶体管的发射极。
确定纳米线长度的主要标准是纳米线内的耗尽层在其轴线方向的厚度。纳米线应该长于耗尽层的厚度，但不要过长。纳米线在其长度或径向上可由不同半导体材料构成。前者使得能够在纳米线顶部保持较好的接触特性，例如，通过在纳米线顶部使用窄能带隙材料来实现，而后者由于降低了对表面缺陷的敏感度使得可提高纳米线的串联电阻。具有不同能带隙的半导体材料和可被结合到单一纳米线中的半导体材料例如是Si和Ge。然而，本发明不限于这些材料。原则上，其还可应用于包括周期系的第III组和第V组中的元素，诸如GaAs、Al1-xGaxAs、InAs、InP等。这些所谓的III-V半导体可主要被用在III-V半导体晶片上作为衬底。
在图2中示出了晶体管的能带示意图，其中施加了发射极-基极电压UEB。该图的纵坐标表示能量E，并且横坐标对应于由箭头表示的图1中的晶片的法线方向X。如图所示，发射极的电子在基极层上注入并越过基极和集电极之间的肖特基势垒。
在以下描述中并参照图3a至3e，提出了加工步骤的一个可能序列来制造根据本发明的金属基极晶体管。注意，在此描述的处理方法仅仅是一个示例性的方法，并且根据要被制造的器件的特定参数，本领域技术人员从所公开的处理方法可以设想出多种变型。
制造工艺开始于标准的n型硅衬底2，该衬底2通过注入被形成为高n型掺杂的衬底2。掺杂级是10-19cm-3水平，并且通过注入砷(As)或磷(P)离子来实现。可购买到的离子注入机可以用于该步骤。
在注入之后，例如，通过浅沟渠隔离来形成衬底图案，以在衬底上形成隔离区域。通过以小纵横比在硅衬底中蚀刻浅沟渠来实现浅沟渠隔离。标准的干法或湿法蚀刻技术被用于该步骤。接下来，氧化硅4被沉积到沟渠区域。在将衬底平面化之后，硅化物前体金属11的薄层被沉积在衬底之上。镍或钴被用作本发明的该实施例中的金属。然而，其它硅化物可被用在其它实施例中，例如，TiSi2、TaSi2、MoSi2、WSi2、和PtSi。可通过溅射或-为了更好的界面质量-通过类似于原子层沉积之类的先进技术来进行沉积。在加温退火步骤期间，前体金属于衬底的硅反应以形成金属硅化物3。如图3b所示，即使在退火步骤之后，在硅化物层3之上还保留了未反应的前体金属11的薄层。显然，前体金属11未在沉积的氧化硅4的区域中进行反应，如图3b所示。这个加工步骤被称作部分硅化步骤。
通过标准的光刻技术，在前体金属层11的顶部限定催化剂区域12。接下来，通过标准的湿法蚀刻技术蚀刻掉暴露出的未反应的金属(图3c)。
用适当的溶剂去除在催化剂区域12上存在的剩余的光致抗蚀剂。其后，催化剂区域12上未反应的金属被用作用于使用VLS技术生长半导体纳米线的催化剂，如图3d所示。
公知的是，通过金或铁对包含气体的硅进行催化分解可以形成长纳米线。该技术通常被称作汽-液-固(VLS)机制。包含金属和硅的纳米液滴位于生长中的线的尖端。不幸的是，金和铁在硅中具有较大的扩散系数，并且生成了较深的电子能级，而这对最终完成的器件的电子性能是有害的。因此，当需要金属化层时，在半导体加工技术中，金属硅化物是优选的。对于本发明来说，已经使用了镍和钴硅化物，但是接下来，为了简单而描述基于钴的处理，但是这并不限制本发明的范围。
根据所提出的方法，通过在可购买到的硅衬底上进行化学汽相沉积(CVD)来沉积钴层。CoCl4气被引入H2气氛的反应器中。CoCl4的分压力是0.06帕斯卡，并且总的反应器压力是670帕斯卡。在硅衬底的表面上，CoCl4与衬底的硅进行反应，并形成CoSi2。在600-700℃的范围内选择衬底的沉积温度。在接下来的退火步骤中，在900℃的高温下，终止了硅化钴的形成。为了在硅化钴上生长硅纳米线，衬底被暴露在反应器的气氛中，该反应器是在大约650℃的温度下，在2700帕斯卡的氢气氛中具有70帕斯卡的分压力的SiH2Cl2的反应器。在这些条件下，硅纳米线在硅化钴上生长。
如果期望使纳米线生长为硅/锗异质结构，则使用激光来在炉中从固体靶蒸发锗。激光束将放置在炉内的锗靶的表面加热，直到锗原子蒸发。其后，蒸发的锗原子被结合到纳米线中。根据生长条件，可使纳米线生长为轴线Si/Ge异质结构，即，纳米线的成分在其轴线方向上改变。只要优选地在硅化钴和纳米线之间的界面上发生反应分解，就能保持一个尺寸生长。类似地，从锗靶蒸发的锗原子也被结合到硅化钴和纳米线之间的界面上生长的纳米线中。通过交替地提供硅和锗，纳米线生长为在纳米线的轴线方向具有Si/Ge异质结构。
通过把三氢化砷(AsH3)或磷化氢(PH3)添加到注入的气流中来使纳米线变成n型掺杂的纳米线。通过三氢化砷或磷化氢的分压力来确定掺杂级。
在不同的生长条件下，还可以使纳米线生长为径向的Si/Ge异质结构，即，纳米线的成分在其径向上改变。为了实现径向异质结构，必须选择生长条件，以使得反应物在纳米线的整个表面上同质分解，并且生成具有与已在开始时生长的核心纳米线不同的成分的外壳。
注意，在上下文中，术语“异质结构”指的是以下成分的纳米线，所述成分为具有类似于硅和锗的不同材料、例如具有类似于n型掺杂的硅和p型掺杂的硅的不同掺杂类型的硅的相同材料、和最后的具有在纳米线的轴线方向或径向上具有不同晶体取向的硅的相同材料。在高多数载流子迁移率的意义上来讲，例如纳米线的表面的调制掺杂的纳米线的径向异质结构是非常具有优势的。
最后，氮化硅(Si3N4)被沉积在晶体管结构之上作为电介质隔离部分7，如图3e所示。在电介质隔离部分7中开有窗口，并且根据公知的用于进行欧姆接触的技术来进行接触。如果必要，可以使用额外的掩模步骤来进行与纳米线的专门接触。
Claims (8)
1.一种晶体管，包括：第一和第二电极(2，6)，以及用于控制第一和第二电极之间的电流的基极电极(3)，其中第一电极(2)由半导体材料制成，其中基极电极是沉积在形成第一电极的半导体材料之上的金属层，其特征在于，第二电极由与基极电极(3)电接触的半导体纳米线(6)形成。
2.如权利要求1所述的晶体管，其特征在于，纳米线(6)生长在基极电极(3)上。
3.如权利要求1所述的晶体管，其特征在于，基极电极(3)由过渡金属硅化物制成。
4.如权利要求3所述的晶体管，其特征在于，从钴和镍组成的组中选择所述过渡金属。
5.如权利要求1所述的晶体管，其特征在于，纳米线(6)由硅和/或锗制成。
6.如权利要求5所述的晶体管，其特征在于，所述纳米线由半导体异质结构组成。
7.如权利要求6所述的晶体管，其特征在于，纳米线(6)异质结构的成分在纳米线(6)的径向上改变。
8.如权利要求6所述的晶体管，其特征在于，纳米线(6)异质结构的成分在纳米线(6)的轴线方向上改变。
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| PCT/IB2006/053995 WO2007057802A1 (en) | 2005-11-18 | 2006-10-29 | Metal-base nanowire transistor |
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| US20100204062A1 (en) * | 2008-11-07 | 2010-08-12 | University Of Southern California | Calibration methods for multiplexed sensor arrays |
| US20100256344A1 (en) * | 2009-04-03 | 2010-10-07 | University Of Southern California | Surface modification of nanosensor platforms to increase sensitivity and reproducibility |
| US9048301B2 (en) | 2013-10-16 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company Limited | Nanowire MOSFET with support structures for source and drain |
| US11133384B1 (en) * | 2020-04-19 | 2021-09-28 | Koucheng Wu | Quantum wire resonant tunneling transistor |
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| JP2535738B2 (ja) * | 1988-12-09 | 1996-09-18 | 工業技術院長 | 半導体装置 |
| JPH0595121A (ja) * | 1991-10-01 | 1993-04-16 | Nippon Telegr & Teleph Corp <Ntt> | 量子細線構造およびその作製方法 |
| US7030408B1 (en) * | 1999-03-29 | 2006-04-18 | Hewlett-Packard Development Company, L.P. | Molecular wire transistor (MWT) |
| US6996147B2 (en) * | 2001-03-30 | 2006-02-07 | The Regents Of The University Of California | Methods of fabricating nanostructures and nanowires and devices fabricated therefrom |
| EP1634334A1 (en) * | 2003-04-04 | 2006-03-15 | Startskottet 22286 AB | Nanowhiskers with pn junctions and methods of fabricating thereof |
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| TWI248681B (en) * | 2004-03-29 | 2006-02-01 | Imec Inter Uni Micro Electr | Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel |
| US7170120B2 (en) * | 2005-03-31 | 2007-01-30 | Intel Corporation | Carbon nanotube energy well (CNEW) field effect transistor |
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| US7709923B2 (en) | 2010-05-04 |
| CN101310389B (zh) | 2010-06-23 |
| ATE518250T1 (de) | 2011-08-15 |
| US20080237574A1 (en) | 2008-10-02 |
| TW200727477A (en) | 2007-07-16 |
| JP5049978B2 (ja) | 2012-10-17 |
| EP1952444B1 (en) | 2011-07-27 |
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