CN101295283A - Bus device and data transmission method thereof - Google Patents
Bus device and data transmission method thereof Download PDFInfo
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- CN101295283A CN101295283A CNA2008101139779A CN200810113977A CN101295283A CN 101295283 A CN101295283 A CN 101295283A CN A2008101139779 A CNA2008101139779 A CN A2008101139779A CN 200810113977 A CN200810113977 A CN 200810113977A CN 101295283 A CN101295283 A CN 101295283A
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Abstract
The invention discloses a bus device and a data transmission method; wherein, the bus device comprises an I<2>C bus used for connecting a CPU and a chip and a logic device used for carrying out the conversion of input and output; the CPU is connected with the logic device by a local bus; the logic device is controlled to effectively set the address of the chip which is connected with the CPU, so as to lead the CPU to access and control the chip with the effective address. The method comprises that the CPU controls the output of the logic device by the local bus and leads the logic device to carry out the effective setting of the address of the chip which is connected with the CPU; the CPU carries out the access and control to the chip which has effective address and is connected with the CPU by the I<2>C bus. The device and the method of the invention can extend the quantity of the chip which can be controlled by the CPU by I<2>C bus with low cost.
Description
Technical field
The present invention relates to bussing technique, especially a kind of bus unit and data transmission method thereof.
Background technology
Between the integrated circuit (Inter-Integrated Circuit, hereinafter to be referred as: I
2C) bus is a kind of twin wire universal serial bus by PHILIPS company exploitation, be used to connect central processing unit (Center ProcessUnit, hereinafter to be referred as: CPU) and peripherals.
I
2The C bus be by data line (Serial Date Line, hereinafter to be referred as: SDA) and clock line (SerialClock Line, hereinafter to be referred as: the SCL) universal serial bus of Gou Chenging can transmit and receive data.CPU and controlled integrated circuit (Integrated Circuit, hereinafter to be referred as: IC) (claim again: chip), carry out two-way transmission, the highest transfer rate 100kbps between IC and the IC.Various Be Controlled circuit all are connected in parallel on this bus.But just as the number that telephone set is only put through separately could be worked, so each circuit and module all have unique address.In the transmission of Information process, I
2On the C bus and each modular circuit that connects be primary controller (or controlled device), be again transmitter (or receiver), this depends on the function that it will be finished.The control signal that CPU sends is divided into address code and controlled quentity controlled variable two parts.Wherein, address code is used for addressing, connects the circuit that needs control that is:, determines the kind of control; The amount that controlled quentity controlled variable determines the classification (as contrast, brightness etc.) of this adjustment and needs to adjust.Like this, though each control circuit hang on same the bus, independently of one another, uncorrelated mutually.
I
2The C rules are used master/slave both-way communication.Device sends data on the bus, and then this device is defined as transmitter; Device receives data and then is defined as receiver.Main device and can work in from device receives and transmit status.Bus must be controlled by main device (being generally CPU).
I
2During the C bus operation, CPU produces clock SCL, and exports the control byte to peripherals on SDA.The Gao Siwei of control byte is the type of device identifier, and then three is the address, and last position is the read-write position.When read-write position is 1 is read operation, be 0 o'clock be write operation.Different outer periphery has different type of device identifiers, and for example: EEPROM generally should be 1010.If I
2The equipment that has a plurality of same types on the C bus, their address must be set to difference, could correctly be visited by CPU.Because I
2The address that CPU sends on the C bus is 3, and every bit address can only be 0 or 1, so an I
2The equipment of the same type that can connect on the C bus mostly is 8 (2 3 powers=8) most.As shown in Figure 1, be employing I in the prior art
2The communication system synoptic diagram that the C bus connects.I
2The address of C equipment is 3, is connected to power supply or ground, and representative is set to 1 or 0 respectively.Among Fig. 1, an I
2The address of C equipment is 001 (A2A1A0), the 2nd I
2The address of C equipment is 010 (A2A1A0).
If CPU need be at I
2Connect equipment on the C bus, then need to expand I more than 8 same types
2The C bus.I commonly used at present
2The C bus expanding method has following two kinds:
A kind of method is to use more I
2The C bus.If use two I
2The C bus, every I
2The equipment that connects 8 same types on the C bus is chip, like this by two I
2The C bus just can connect the equipment of 16 same types.The shortcoming of this method is that the limited amount of the addressable same type equipment of CPU is in the I of CPU
2C bus number.Because the I of existing CPU
2C bus interface limited amount can only connect one to two I usually
2The C bus, therefore, CPU can connect the equipment of 16 same types at most, can't connect the same type equipment of greater number.If will increase the I of CPU
2The C bus interface then needs higher cost.
Another kind method is to use special-purpose I
2C extended chip expansion I
2The quantity of C bus.As shown in Figure 2, adopt I for prior art
2C extended chip expansion I
2The communication system synoptic diagram of C bus number.CPU is by an I
2C is connected to I
2On the C extended chip, this I
2The C extended chip can expand 8 I
2The C bus.CPU passes through I
2The total line traffic control I of C
2The electronic switch of C extended chip inside, thus expand I
2C1, I
2C2 ..., I
2Eight I such as C8
2The C bus.CPU is by the I of its connection
2The total line traffic control I of C
2The electronic switch of C extended chip, thus make this I
2Eight I that the C extended chip expands
2In the C bus one I with CPU
2The C bus links to each other, the I of CPU by connecting
2This I that expands of C bus operation
2The equipment that connects on the C bus.For example: the I that CPU connects
2C bus elder generation and I
2C1 is connected, operation I
2The equipment that connects on the C1 bus; After operation was finished, CPU was by operation I
2The C extended chip disconnects and I
2The connection of C1 bus is with I
2The C2 bus is connected; By that analogy.By adopting I
2The method of C extended chip, CPU no longer is subject to the I of itself
2C bus interface quantity, altogether can with 8 I
2The C bus connects, the equipment of 64 same types of operation.If I
2The extended chip of C itself can configuration address, and then CPU can be connected with 8 extended chips, and manipulable number of devices can also improve 8 times.But this method need be used special I
2C extended chip, and I
2The cost of C extended chip is higher, and this can cause the increase of circuit cost again.
Summary of the invention
The purpose of the embodiment of the invention is: a kind of bus unit and data transmission method thereof are provided, and extension CPU is passed through I under lower cost
2The quantity of the controllable chip of C bus.
For achieving the above object, according to an aspect of the embodiment of the invention, a kind of bus unit that provides comprises the I that connects CPU and chip
2The C bus, also comprise the logical device that is used to carry out the input and output conversion, CPU is connected with logical device by local bus, and the address of controlling the chip that described logical device connects CPU is carried out validity and set, so that CPU can be to the control that conducts interviews of the effective chip in address.
According to another aspect of the embodiment of the invention, the data transmission method of a kind of bus unit that provides comprises:
CPU exports control by local bus to logical device, makes logical device carry out validity to the address of the chip of CPU connection and sets;
CPU passes through I
2The C bus is to the control that conducts interviews of the effective chip in address in the chip that connects.
Based on the technique scheme of the embodiment of the invention, CPU comes logical device is exported control by the input of local bus to logical device, thereby realizes CPU is passed through I
2The address setting of each chip that the C bus connects, like this, CPU just can be to the control that conducts interviews of the effective chip in address.Because logical device can be converted to input signal abundant output signal, therefore, can carry out validity to the address of the chip of abundant quantity and set, thereby make CPU can pass through I
2The C bus has been expanded CPU and has been passed through I the control that conducts interviews of abundant chip
2The quantity of the controllable chip of C bus.And, because logical device is than special-purpose I
2C extended chip or have a plurality of I
2The cost of the CPU of C bus is low, and bus unit of the present invention compared with prior art can reduce circuit cost.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is employing I in the prior art
2The communication system synoptic diagram that the C bus connects.
Fig. 2 adopts I for prior art
2C extended chip expansion I
2The communication system synoptic diagram of C bus number.
Fig. 3 is the structural representation of bus unit embodiment of the present invention.
Fig. 4 is the output principle synoptic diagram of local bus of the present invention.
Fig. 5 carries out an exemplary plot of input and output conversion for logical device of the present invention.
Fig. 6 is the level synoptic diagram of signal in the local bus of the present invention.
Fig. 7 is the process flow diagram of the data transmission method embodiment of bus unit of the present invention.
Embodiment
In the embodiment of the invention, logical device is exported control by CPU, thus the address of a plurality of chips that CPU is connected carry out validity and set, make CPU need the address of chip of access control effective, pass through I and make
2Other chip address that the C bus connects is invalid, under the situation that reduces circuit cost, CPU is passed through I
2The quantity of the chip of C bus access control is expanded.
As shown in Figure 3, be the structural representation of bus unit embodiment of the present invention.The bus unit of this embodiment comprises the I that connects CPU and chip
2C bus 101, with the logical device 102 that is used to carry out the input and output conversion, CPU is connected with logical device 102 by local bus 103, and 102 couples of CPU of steering logic device pass through I
2The validity setting is carried out in the address of one or more chips that C bus 101 connects, and makes CPU pass through I
2Need the address of chip of access control effective in a plurality of chips that C bus 101 connects, pass through I and make
2Other chip address that C bus 101 connects is invalid, so that CPU can be to the control that conducts interviews of the effective chip in address.
Because the address of chip is made of the value on three address wires on the chip, therefore, can make CPU pass through I
2Wherein address wire on each chip that C bus 101 connects respectively with the corresponding connection of each output port of logical device 102.Like this, the value on all the other two address wires on the chip is invalid, the address validity of this chip just by with address wire that each output port of logical device 102 is connected on the value decision.If effective with the value on the address wire that each output port of logical device 102 is connected, then the address of this chip is effective; If invalid with the value on the address wire that each output port of logical device 102 is connected, then the address of this chip is invalid.
In bus unit embodiment illustrated in fig. 3, can also comprise the mapping table between the output port that records chip and the corresponding logical device 102 that is connected the wherein address wire on this chip.CPU exports control according to described mapping table to each output port of logical device 102, make each output port to the address wire output effective value or the invalid value that connect, thereby realization is carried out the validity setting to the address of a plurality of chips of CPU connection.
Local bus (LOCAL BUS) is the bus that CPU carries.As shown in Figure 4, be the output principle synoptic diagram of local bus of the present invention.According to Fig. 4, the output signal of this local bus generally includes following three classes: control signal, address signal and data-signal.Control signal by sheet selected control system signal (hereinafter to be referred as: CS), read control signal (hereinafter to be referred as: R) with write control signal (hereinafter to be referred as: W) form.Address signal is made up of multidigit address wire A (n...0).Data-signal is made up of long numeric data line D (m...0).Control signal and address signal are one way signals, are exported to chip by CPU.Data-signal is a two-way signaling, is exported to chip by CPU during write operation, is imported to CPU by chip during read operation.CPU carries out read or write by local bus to the chip that the corresponding interface is arranged.
Logical device is a kind of chip that specific function is provided, and it can be converted to specific output signal to input signal.As shown in Figure 5, carry out an exemplary plot of input and output conversion for logical device of the present invention.Logical device among Fig. 5 can be realized the decoding of 4 to 16 outputs.The CS of CPU, W, D (3...0) output on the logical device, and wherein, the width of data line D (3...0) is 4, and logical device is output as 16.Logical device is converted into output with CPU to the write operation of this logical device.For example: CPU writes 0 to logical device, that is: the signal that transmits on the data line is 0000, first output port output 1 of logical device, other output port output 0; CPU writes 1 to logical device, that is: the signal that transmits on the data line is 0001, second output port output 1 of logical device, other output port output 0.
As shown in Figure 6, be a level synoptic diagram of signal in the local bus of the present invention.When CPU did not operate logical device, CS in the local bus and W were high level, and D is a high-impedance state.CPU is during to the logical device write operation, and CS and W in the local bus become low level, the data that D output need be write.Through Preset Time, CS and W become high level.Pass through certain time delay again, when D finishes output, return high-impedance state again, write operation finishes.When write operation, each output of CS and W is fixed, according to the order variation of height-low-Gao.The output of D changes from the order of high resistant-output data-high resistant, and wherein output data output valve as required changes.As logical device is write 0, that is: D is output as 0000, and then the output of first output port of logical device 1, other output port output 0.As logical device is write 1, that is: D is output as 0001, and then the output of second output port of logical device 1, other output port output 0.
Among the bus unit embodiment shown in Figure 3, pass through I with CPU
2It is that example specifies that C bus 101 connects three chips.Among three address wire A2A1A0 of three chips, in advance the value on address wire A1 and the A2 all is configured to preassigned invalid value, for example: the value on A1 and the A2 all is configured to 0.The address wire A0 of three chips is connected respectively on the logical device 102.CPU is connected with logical device 102 by local bus 103.Logical device becomes output signal with the write operation translation of CPU on local bus 103, thereby the value of controlling on the address wire A0 of three chips is invalid value 0 or effective value 1.In addition, the effective value on the address wire is the same with invalid value, can specify its value by preestablishing, and can be other arbitrary value beyond the invalid value.Not during access chip, logical device 102 all exports 0 to the address wire A0 of three chips that connect, and is invalid value 0 thereby make three values on the chip A0 at CPU, at this moment, and the I of three chips
2The C address all is invalid address 000.
When CPU visits first chip, according to the mapping table between the output port that records chip and the logical device 102 of a corresponding wherein address wire that is connected this chip, search the output port that connects the address wire A0 of first chip on the logical device 102, by this output port output effective value 1 of local bus 103 controls, making the value on the first chip A0 is effective value 1, and make the output port output invalid value 0 that connects second chip and the 3rd chip, making the value on second chip and the 3rd chip A0 is invalid value 0.At this moment, the address of first chip is that the address of effective address 001, the second chip and the 3rd chip is invalid address 000.CPU passes through I
2C bus 101 reference address 001 can be to the control that conducts interviews of first chip.Because the address of second chip and the 3rd chip is invalid address 000, does not respond the operation of CPU.
Equally, when CPU visits second chip, according to the mapping table between the output port that records chip and the logical device 102 of a corresponding wherein address wire that is connected this chip, search the output port that connects the address wire A0 of second chip on the logical device 102, by this output port output effective value 1 of local bus 103 controls, making the value on the second chip A0 is effective value 1, and make the output port output invalid value 0 that connects first chip and the 3rd chip, making the value on first chip and the 3rd chip A0 is invalid value 0.At this moment, the address of second chip is that the address of effective address 001, the first chip and the 3rd chip is invalid address 000.CPU passes through I
2C bus 101 reference address 001 can be to the control that conducts interviews of second chip.Because the address of first chip and the 3rd chip is invalid address 000, does not respond the operation of CPU.
In like manner, CPU can take similar method that CPU is passed through I
2The 3rd chip that C bus 101 connects and more other chip control that conducts interviews.In addition, also can be according to preestablishing, with the value on other address wire on the chip, for example: with address wire A0 and A2, or the value on A0 and the A1 is set to invalid value, and corresponding address wire A1 or A2 are connected with the output port of logical device 102, control by the value on 102 couples of address wire A1 of logical device or the A2, address wire A0 that also can segment chip and the value on the A2 are set to invalid value, and address wire A1 is connected with the output port of logical device 102, or the address wire A0 of segment chip and the value on the A1 are set to invalid value, and address wire A2 is connected with the output port of logical device 102, as long as CPU can know that according to the mapping table between the output port that records chip and the logical device 102 of a corresponding wherein address wire that is connected this chip the address of chip is just passable.
If CPU passes through I
2C bus 101 connects more chip, as long as control by the value on one of them address wire of 102 pairs of each chips of logical device, the address that makes the chip of not visiting all is the invalid address, that is: the value that constitutes on each address bit of this address is an invalid value, for example: 000, do not respond the operation of CPU, and make the address that needs access chip is effective address, that is: the value that constitutes on one of them address bit of this address is an effective value, for example: 001,010,100, just can realize access control to a plurality of chips.Like this, can carry out validity to the address of the chip of abundant quantity and set, as long as logical device has the wherein value on address wire of enough output control chips, CPU can pass through I
2The number of chips of C bus access control can be unrestricted, effectively expanded CPU and passed through I
2The quantity of the controllable chip of C bus.And, because logical device is than special-purpose I
2C extended chip or have a plurality of I
2The cost of the CPU of C bus is low, and bus unit of the present invention can low-costly be realized I
2The expansion of C bus compared with prior art, can reduce circuit cost.
The data transmission method of a kind of bus unit that the embodiment of the invention provides comprises: CPU exports control by local bus to logical device, makes logical device carry out validity to the address of the chip of CPU connection and sets; CPU passes through I
2The C bus is to the control that conducts interviews of the effective chip in address in the chip that connects.
As shown in Figure 7, the process flow diagram for the data transmission method embodiment of bus unit of the present invention in conjunction with bus unit shown in Figure 3, is specifically described its data transmission method, and it may further comprise the steps:
Particularly, CPU is according to the mapping table between the output port that records chip and the logical device 102 of a corresponding wherein address wire that is connected this chip, by write control signal in the local bus 103 and data-signal, output signal on each output port is provided with, the output signal that the A0 address wire of chip from access control to CPU that will is connected is an effective value 1, and the output signal that connects to the address wire A0 of other chip is an invalid value.CPU is by the output signal on each output port of steering logic device 102, to passing through I
2Value on the address wire of each chip that C bus 101 connects is carried out validity and is set, and making the value on the address wire A0 on one of them chip that CPU will visit is effective value, is effective address thereby make the address of this chip.
The embodiment of the invention can be carried out validity to the address of the chip of abundant quantity and set, thereby makes CPU can pass through I
2The C bus is to the control that conducts interviews of abundant chip, and effectively extension CPU is passed through I
2The quantity of the controllable chip of C bus.And, because logical device is than special-purpose I
2C extended chip or have a plurality of I
2The cost of the CPU of C bus is low, and bus unit of the present invention compared with prior art can reduce circuit cost.
It should be noted last that: above embodiment is only in order to illustrating technical scheme of the present invention, but not the present invention is made restrictive sense.Although the present invention is had been described in detail with reference to above-mentioned preferred embodiment, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and this modification or be equal to the spirit and scope that replacement does not break away from technical solution of the present invention.
Claims (7)
1, a kind of bus unit comprises the I that connects CPU and chip
2The C bus, it is characterized in that also comprise the logical device that is used to carry out the input and output conversion, CPU is connected with logical device by local bus, the address of controlling the chip that described logical device connects CPU is carried out validity and is set, so that CPU can be to the control that conducts interviews of the effective chip in address.
2, bus unit according to claim 1 is characterized in that, the wherein address wire on each chip that CPU connects respectively with the corresponding connection of each output port of logical device.
3, bus unit according to claim 1 and 2, it is characterized in that, also comprise the mapping table that records between chip and the corresponding output port that is connected the wherein logical device of an address wire on this chip, CPU controls the output on each output port of logical device according to described mapping table, thereby the address of the chip that CPU is connected is carried out validity and set.
4, a kind of data transmission method of bus unit is characterized in that, comprising:
CPU exports control by local bus to logical device, makes logical device carry out validity to the address of the chip of CPU connection and sets;
CPU passes through I
2The C bus is to the control that conducts interviews of the effective chip in address in the chip that connects.
5, data transmission method according to claim 4 is characterized in that, also comprises: in advance CPU is passed through I
2Value on wherein two address wires on each chip that the C bus connects is set to invalid value, and CPU passes through I
2Another root address wire on each chip that the C bus connects respectively with the corresponding connection of output port of logical device; Described logical device carries out the validity setting to the address of the chip of CPU connection and comprises: by the output signal on each output port of logical device, CPU is passed through I
2Value on each address wire that the C bus connects is carried out validity and is set, and making the value on the address wire of the chip that CPU will visit is effective value.
6, data transmission method according to claim 5 is characterized in that, described CPU exports control by local bus to logical device and comprises:
CPU is according to the mapping table that records between chip and the corresponding output port that is connected the wherein logical device of an address wire on this chip, by write control signal in the local bus and data-signal, output signal on each output port of steering logic device, the output signal that the address wire of the chip that CPU will access control is connected is an effective value, and the output signal that the address wire of other chip connects is an invalid value.
7, according to claim 5 or 6 described data transmission methods, it is characterized in that, also comprise:
CPU exports control by local bus to logical device after finishing access control to chip, makes the value on the address wire on this chip that logical device connects be set to invalid value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101139779A CN101295283A (en) | 2008-05-30 | 2008-05-30 | Bus device and data transmission method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101139779A CN101295283A (en) | 2008-05-30 | 2008-05-30 | Bus device and data transmission method thereof |
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| CN101295283A true CN101295283A (en) | 2008-10-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2008101139779A Pending CN101295283A (en) | 2008-05-30 | 2008-05-30 | Bus device and data transmission method thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101895523A (en) * | 2009-05-22 | 2010-11-24 | 华为技术有限公司 | Board-to-board communication method, system, mainboard and service single board |
| CN102339267A (en) * | 2010-06-04 | 2012-02-01 | 英特赛尔美国股份有限公司 | I2C address translation |
| CN102411550A (en) * | 2011-08-24 | 2012-04-11 | 四川九洲电器集团有限责任公司 | I2C bus controlled device based apparatus and method |
| CN103229158A (en) * | 2012-11-23 | 2013-07-31 | 华为技术有限公司 | Control circuit and control method for inter-integrated circuit bus |
| CN103577356A (en) * | 2013-11-06 | 2014-02-12 | 杭州华三通信技术有限公司 | Equipment and method for achieving IIC interface address extension |
| CN106959933A (en) * | 2017-03-16 | 2017-07-18 | 数据通信科学技术研究所 | A kind of method of extended bus system and bus marco |
| CN114579491A (en) * | 2022-01-28 | 2022-06-03 | 新华三技术有限公司合肥分公司 | Integrated circuit bus multiplexing device and network equipment |
| CN114691573A (en) * | 2020-12-31 | 2022-07-01 | 北京配天技术有限公司 | Hardware identification circuit, method and related equipment |
-
2008
- 2008-05-30 CN CNA2008101139779A patent/CN101295283A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101895523A (en) * | 2009-05-22 | 2010-11-24 | 华为技术有限公司 | Board-to-board communication method, system, mainboard and service single board |
| CN102339267B (en) * | 2010-06-04 | 2016-01-20 | 英特赛尔美国股份有限公司 | I2C address is changed |
| CN102339267A (en) * | 2010-06-04 | 2012-02-01 | 英特赛尔美国股份有限公司 | I2C address translation |
| US9477634B2 (en) | 2010-06-04 | 2016-10-25 | Intersil Americas LLC | I2C address translation |
| CN102411550A (en) * | 2011-08-24 | 2012-04-11 | 四川九洲电器集团有限责任公司 | I2C bus controlled device based apparatus and method |
| CN103229158A (en) * | 2012-11-23 | 2013-07-31 | 华为技术有限公司 | Control circuit and control method for inter-integrated circuit bus |
| WO2014079034A1 (en) * | 2012-11-23 | 2014-05-30 | 华为技术有限公司 | Control circuit and control method for inter-integrated circuit bus |
| CN103577356B (en) * | 2013-11-06 | 2016-07-06 | 杭州华三通信技术有限公司 | Realize the Apparatus and method for of IIC interface IP address extension |
| CN103577356A (en) * | 2013-11-06 | 2014-02-12 | 杭州华三通信技术有限公司 | Equipment and method for achieving IIC interface address extension |
| CN106959933A (en) * | 2017-03-16 | 2017-07-18 | 数据通信科学技术研究所 | A kind of method of extended bus system and bus marco |
| CN106959933B (en) * | 2017-03-16 | 2019-08-23 | 数据通信科学技术研究所 | A kind of method of extended bus system and bus marco |
| CN114691573A (en) * | 2020-12-31 | 2022-07-01 | 北京配天技术有限公司 | Hardware identification circuit, method and related equipment |
| CN114579491A (en) * | 2022-01-28 | 2022-06-03 | 新华三技术有限公司合肥分公司 | Integrated circuit bus multiplexing device and network equipment |
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