CN101281894A - 半导体组件承载结构及其叠接结构 - Google Patents

半导体组件承载结构及其叠接结构 Download PDF

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CN101281894A
CN101281894A CNA2007100922358A CN200710092235A CN101281894A CN 101281894 A CN101281894 A CN 101281894A CN A2007100922358 A CNA2007100922358 A CN A2007100922358A CN 200710092235 A CN200710092235 A CN 200710092235A CN 101281894 A CN101281894 A CN 101281894A
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semiconductor component
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electric connection
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连仲城
张家维
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Unimicron Technology Corp
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Quanmao Precision Science & Technology Co Ltd
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Abstract

一种半导体组件承载结构及其叠接结构，该半导体组件承载结构包括：一电路板，表面设有线路层，该电路板具有至少一开口，且该线路层具有多个电性连接垫及导电结构；一具有多个电极垫的半导体组件，其嵌埋于该开口中，且该些电极垫并通过该导电结构电性连接该线路层；以及多个导电凸块，其设于该电性连接垫表面；各该半导体组件承载结构可设置对应导电凸块的焊锡球，以供一电路板的导电凸块对应接合至另一电路板的焊锡球，由此形成叠接结构。

Description

半导体组件承载结构及其叠接结构
技术领域
一种半导体组件承载结构及其叠接结构，尤指一种整合半导体组件的承载结构及其叠接结构于电路板的承载技术。
背景技术
电子产品轻小化已是现今电子产业发展的趋势，而随着电子产品制作的缩小化，对于各种不同功能的半导体组件镶嵌在一电路板上则有朝更高密度的使用需求。因此，在单一芯片承载件上接置并电性连接有至少二个以上的半导体芯片，且该芯片与承载件间的接置方式是将半导体芯片一一向上叠接在承载件上，再以焊线进行电性连接。
请参阅图1，为美国专利第5,323,060号的多芯片半导体封装件1的剖面示意图，其将一第一半导体芯片12a接置于一电路板11上，并通过一第一焊线1 3a电性连接至该电路板11，且采用堆叠方式(stacked)以将一第二半导体芯片12b间隔一胶层14堆叠于该第一半导体芯片12a上，而该胶层14的材质一般为环氧胶(epoxy)或胶带(tape)，之后再通过一第二焊线13b电性连接至该电路板11。但是该第一半导体芯片12a的焊线制造方法(wire bonding)需在该第二半导体芯片12b堆叠前完成先进行，亦即每一层芯片的黏晶(die bonding)制造及焊线制造均需分别进行，因而增加额外的制造复杂度；再者，由于该第一半导体芯片12a、胶层14与第二半导体芯片12b是一一顺序向上堆叠于该电路板11上，且为有效防止第二半导体芯片12b触碰至第一焊线13a，该胶层14厚度必须增高至该第一焊线13a的线弧高度以上，如此，不仅增加该多芯片半导体封装件1的整体厚度，而不利于半导体装置的轻薄化，同时因该胶层14的整体厚度均匀控制不易，甚而导致该第二半导体芯片12b触碰至第一焊线13a或该第一焊线13a与该第二焊线13b接触产生短路等不良问题。
又电子产品在积集化的趋势下，以提高电子产品的使用功能，并且降低电子产品的高度，遂将半导体组件内嵌于承载板的技术逐渐受到重视，而嵌埋于电路板的半导体组件可为主动组件或被动组件。如图2所示，为现有将半导体组件嵌埋于一电路板中的结构示意图，于一承载板20上表面形成有至少一开口200，该开口200是用以接置一半导体组件21，而该半导体组件21具有一作用面21a，且该作用面21a具有多个电极垫212，于该承载板20上表面以及该半导体组件21的作用面21a上形成一介电层22，并于该介电层22上形成一线路层23，且该线路层23具有多个导电结构231以连接该半导体组件21的电极垫212，依此增层方式形成多层线路层以及介电层，从而构成一多层电路板。
然于上述制造方法中，由于单一承载板20嵌埋单一半导体组件21的电性功能有限，若要增加该承载板20的电性功能则必须增加该半导体组件21的数量，如此则必须在该承载板20上开设多个开口200，但该承载板20的面积有限无法扩大，因而限制了承载板20电性功能的扩充与发展。
因此，如何提供一种可将半导体组件嵌埋于电路板中，同时强化其电性需求及功能，实已成为目前亟欲解决的技术问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的主要目的在于提供一种半导体组件承载结构及其叠接结构，以简化制造方法。
本发明的另一目的在于提供一种半导体组件承载结构及其叠接结构，以强化整体结构的电性需求及功能。
为达成上述及其它目的，本发明提供一种半导体组件承载结构及其叠接结构。
该半导体组件承载结构包括：一电路板，表面设有线路层，且该电路板具有至少一开口，该线路层具有多个电性连接垫及导电结构；一具有多个电极垫的半导体组件，嵌埋于该开口中，且该些电极垫并通过该导电结构电性连接该线路层；以及多个导电凸块，设于该电性连接垫表面。较佳地，该导电凸块设于该电路板其中一表面的线路层的电性连接垫表面。于前述的半导体组件承载结构中，还可包括于未形成有导电凸块的另一表面的电性连接垫表面的焊锡球。
该半导体组件承载结构的叠接结构则包括：至少二电路板，各该电路板表面设有线路层，且该电路板具有至少一开口，于该开口中嵌埋一具有多个电极垫的半导体组件，而该线路层具有多个导电结构以电性连接该半导体组件的电极垫，又该线路层具有多个电性连接垫；多个导电凸块，设于至少一电路板的电性连接垫表面；以及多个焊锡球，其形成于未设有该导电凸块的线路层的电性连接垫表面，以供一电路板的导电凸块对应接合至另一电路板的焊锡球，从而形成电路板间的电性连接。
前述的半导体组件承载结构及其叠接结构中，该电路板可为印刷电路板及IC封装基板的其中之一。该导电凸块为铜、银、金、镍/金及镍/铅/金所组成群组的其中之一。该半导体组件为主动组件及被动组件的其中之一。
相比于现有技术，本发明的半导体组件承载结构及其叠接结构，可直接熔合各该导电凸块与焊锡球以叠接多半导体组件承载结构，由此简化制造方法，并进而强化整体结构的电性需求及功能，实已解决现有技术的缺失。
附图说明
图1为美国专利第5,323,060号的多芯片半导体封装件1的剖面示意图；
图2为现有嵌埋半导体组件的半导体组件承载结构示意图；
图3A为本发明较佳实施例的半导体组件承载结构的剖视图；
图3B为显示于图3A形成供一电路板的导电凸块对应接合至另一电路板的焊锡球的剖视图；
图4A为图3B的半导体组件承载结构的叠接结构的分解示意图；以及
图4B为图4A的叠接结构的组合示意图。
附图标记说明
1    多芯片半导体封装件
11、31    电路板
12a       第一半导体芯片
12b       第二半导体芯片
13a       第一焊线
13b       第二焊线
14        胶层
200、311  开口
20        承载板
212、351  电极垫
21a       作用面
21        半导体组件
22        介电层
23、33    线路层
231、333  导电结构
3         半导体组件承载结构
30        叠接结构
331       电性连接垫
35        半导体组件
37        导电凸块
39        焊锡球
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，所属技术领域中具有通常知识者可由本说明书所揭示的内容轻易地了解本发明的其它优点与功效。
图3A至图4B为依本发明的半导体组件承载结构及其叠接结构的较佳实施例所绘制的图。
请参阅图3A，为本实施例的半导体组件承载结构3，包括电路板31、形成于该电路板31上下表面的线路层33、嵌埋于该电路板31开口311中的半导体组件35、形成于该电路板31上表面的线路层33的导电凸块37，其中该电路板31可为印刷电路板或IC封装基板，且该电路板31具有至少一开口311，以于该开口311中嵌埋至少一半导体组件35。
该线路层33形成于该电路板31上下表面，且该电路板31上下表面的线路层33均形成有多个电性连接垫331以及接置于该电性连接垫331的导电结构333。
该半导体组件35可为CPU或内存(DRAM、SRAM、SDRAM)等主动组件，或者可为如电容(capacitors)、电阻(resistor)或电感(inductors)等被动组件。于本实施例中，该半导体组件35具有多个电极垫351，且该电极垫351是电性连接该线路层的导电结构333。
至少一导电凸块37形成于该电性连接垫331表面。于本实施例中，是在位于该电路板31上表面的线路层33的电性连接垫331表面设置导电凸块37，且该导电凸块37可为诸如铜(Cu)、银(Ag)、金(Au)、镍/金(Ni-Au)及镍/铅/金(Ni-Pb-Au)的其中之一所制成的凸块。较佳可由铜加上前述任一材料制成该导电凸块37。
虽本实施例的半导体组件承载结构3主要包括电路板31、线路层33、半导体组件35及导电凸块37，于其它实施例中还可于该电路板31下表面的线路层33的电性连接垫331表面设置焊锡球(Solderjoint)39，如图3B所示。
请参阅图4A，当欲叠接该半导体组件承载结构3时，得在位于该电路板31下表面的线路层33的电性连接垫331表面设置焊锡球39，以令该焊锡球39与该导电凸块37直接熔接以电性连接两半导体组件承载结构3。
如图4B所示，该半导体组件承载结构3的叠接结构30包括设有线路层33及形成于各电路板31中的开口311的二电路板31、设于各该电路板31其中一线路层33的电性连接垫331表面的多个导电凸块37、嵌埋于该开口311中的半导体组件35、以及形成于未设有该导电凸块37的线路层33的电性连接垫331表面的多个焊锡球39。
该线路层33具有多个电性连接垫331及导电结构333，该半导体组件35的电极垫351通过该导电结构333电性连接该线路层33，各该导电凸块37与焊锡球39对应接合以电性连接，从而形成电路板间的电性连接。
之后，亦可通过相对应的各该导电凸块37与焊锡球39持续叠接该半导体组件承载结构3，以构成一多层半导体组件承载结构的叠接结构。当然，如有需要亦可于两叠接的电路板31的外表面形成线路增层结构(未图标)，以形成多层电路板的结构，并非以本实施例中所示的为限。
此外，于该电路板31最外表面的电性连接垫331表面的焊锡球39，即该叠接结构30最外层的半导体组件承载结构3的焊锡球39，除可供一电路板的导电凸块对应接合至另一电路板的焊锡球外，亦可作为电性连接外部电子装置(未图标)的导电结构。
由此可知，本发明的半导体组件承载结构及其叠接结构，是在至少一电路板表面的电性连接垫上形成有导电凸块，并与另一电路板的焊锡球相对应，通过直接熔接导电凸块与焊锡球而形成通路，以电性连接多个叠接的电路板及嵌埋于该电路板中的半导体组件，而可简化制造方法，并进而强化整体结构的电性需求及功能，相对已克服现有技术的缺失。
但是以上所述的具体实施例，仅用以例释本发明的特点及功效，而非用以限定本发明的可实施范畴，在未脱离本发明上揭的精神与技术范畴下，任何运用本发明所揭示内容而完成的等效改变及修饰，均仍应为前述的权利要求书所涵盖。

Claims (10)

1. 一种半导体组件承载结构，包括：
一电路板，表面设有线路层，且该电路板具有至少一开口，该线路层具有多个电性连接垫及导电结构；
一具有多个电极垫的半导体组件，嵌埋于该开口中，且该些电极垫并通过该导电结构电性连接该线路层；以及
多个导电凸块，其设于该电性连接垫表面。
2. 根据权利要求1所述的半导体组件承载结构，其中，该电路板为印刷电路板及IC封装基板的其中之一。
3. 根据权利要求1所述的半导体组件承载结构，其中，该导电凸块为铜、银、金、镍/金及镍/铅/金所组成群组的其中之一。
4. 根据权利要求1所述的半导体组件承载结构，其中，该导电凸块是设于该电路板其中一表面的线路层的电性连接垫表面。
5. 根据权利要求1所述的半导体组件承载结构，其中，该半导体组件为主动组件及被动组件的其中之一。
6. 根据权利要求4所述的半导体组件承载结构，还包括在未形成有导电凸块的另一表面的电性连接垫表面形成有焊锡球。
7. 一种半导体组件承载结构的叠接结构，包括：
至少二电路板，各该电路板表面设有线路层，且该电路板具有至少一开口，于该开口中嵌埋一具有多个电极垫的半导体组件，而该线路层具有多个导电结构以电性连接该半导体组件的电极垫，且该线路层具有多个电性连接垫；
多个导电凸块，其设于至少一电路板的电性连接垫表面；以及
多个焊锡球，其形成在未设有该导电凸块的线路层的电性连接垫表面，以供一电路板的导电凸块对应接合至另一电路板的焊锡球，以形成电路板间的电性连接。
8. 根据权利要求7所述的半导体组件承载结构的叠接结构，其中，该电路板为印刷电路板及IC封装基板的其中之一。
9. 根据权利要求7所述的半导体组件承载结构的叠接结构，其中，该导电凸块为铜、银、金、镍/金及镍/铅/金所组成群组之一。
10. 根据权利要求8所述的半导体组件承载结构的叠接结构，其中，该半导体组件为主动组件及被动组件其中之一。
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CN102751256A (zh) * 2011-04-22 2012-10-24 欣兴电子股份有限公司 嵌埋被动组件的封装基板及其制造方法
US9179549B2 (en) 2010-08-13 2015-11-03 Unimicron Technology Corporation Packaging substrate having embedded passive component and fabrication method thereof
CN105530765A (zh) * 2014-09-29 2016-04-27 富葵精密组件(深圳)有限公司 具有内埋元件的电路板及其制作方法

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JP2001053243A (ja) * 1999-08-06 2001-02-23 Hitachi Ltd 半導体記憶装置とメモリモジュール
KR100688768B1 (ko) * 2004-12-30 2007-03-02 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조 방법

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US9179549B2 (en) 2010-08-13 2015-11-03 Unimicron Technology Corporation Packaging substrate having embedded passive component and fabrication method thereof
CN102751256A (zh) * 2011-04-22 2012-10-24 欣兴电子股份有限公司 嵌埋被动组件的封装基板及其制造方法
CN102751256B (zh) * 2011-04-22 2015-10-14 欣兴电子股份有限公司 嵌埋被动组件的封装基板及其制造方法
CN105530765A (zh) * 2014-09-29 2016-04-27 富葵精密组件(深圳)有限公司 具有内埋元件的电路板及其制作方法

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