CN101241846B - Techniques for improving etch rate uniformity - Google Patents
Techniques for improving etch rate uniformity Download PDFInfo
- Publication number
- CN101241846B CN101241846B CN2008100852345A CN200810085234A CN101241846B CN 101241846 B CN101241846 B CN 101241846B CN 2008100852345 A CN2008100852345 A CN 2008100852345A CN 200810085234 A CN200810085234 A CN 200810085234A CN 101241846 B CN101241846 B CN 101241846B
- Authority
- CN
- China
- Prior art keywords
- wafer
- side ring
- substrate
- plasma processing
- processing chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000000126 substance Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 230000006872 improvement Effects 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 4
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 148
- 230000008878 coupling Effects 0.000 description 50
- 238000010168 coupling process Methods 0.000 description 50
- 238000005859 coupling reaction Methods 0.000 description 50
- 210000002381 plasma Anatomy 0.000 description 50
- 238000005530 etching Methods 0.000 description 37
- 239000000463 material Substances 0.000 description 26
- 230000008569 process Effects 0.000 description 24
- 230000005684 electric field Effects 0.000 description 15
- 239000000945 filler Substances 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010849 ion bombardment Methods 0.000 description 7
- 238000013459 approach Methods 0.000 description 5
- -1 for example Substances 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 230000005284 excitation Effects 0.000 description 3
- 239000003112 inhibitor Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 241000237983 Trochidae Species 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000005596 ionic collisions Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
- H01J37/32642—Focus rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10S156/915—Differential etching apparatus including focus ring surrounding a wafer for plasma apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Improved methods and apparatus for ion-assisted etch processing in a plasma processing system are disclosed. In accordance with various aspects of the invention, an elevated edge ring, a grooved edge ring, and a RF coupled edge ring are disclosed. The invention operates to improve etch rate uniformity across a substrate (wafer). Etch rate uniformity improvement provided by the invention not only improves fabrication yields but also is cost efficient and does not risk particulate and/or heavy metal contamination.
Description
The application is that application number is dividing an application of 00809793.3 application.
Invention field
The present invention relates to the manufacturing of semiconductor integrated circuit, more specifically, the present invention relates to improving one's methods and installing of plasma process system intermediate ion-assisted etch processing.
Association area is described
At the device of Semiconductor substrate, for example, material layer optionally can be deposited to substrate surface in the manufacturing of integrated circuit or flat-panel monitor or from the substrate surface etching.Well-known in this area, the etching of sedimentary deposit can be used multiple technologies, comprises that plasma-enhancing etching finishes.In plasma-enhancing etching, actual etching typically occurs in the plasma processing chamber in the plasma process system.In order to form desirable figure at substrate surface, be typically and adopt a kind of suitable mask layer (for example, photoresist mask layer).Then by suitable etchant source gas, or admixture of gas produces a kind of plasma gas, and it is used the etching region of not masked layer protection, thereby stays desirable figure.
For ease of discussing, Figure 1A has drawn a kind of plasma processing apparatus 100 of simplification, and it is suitable for the manufacturing of Semiconductor substrate device.The plasma processing apparatus 100 of this simplification includes the wafer processing chamber 102 of electrostatic chuck (ESC) 104.Chuck 104 is as electrode, and supporting wafers (being substrate) 106 during manufacture.Edge joint circle of side ring 108 and chuck 104.In etch processes, one group of parameter in the wafer processing chamber 102 is subjected to strictly controlling to obtain the etching result of high tolerance.The processing parameter that influences etching result can comprise gas componant, the excitation of plasma, and the distribution of plasma above wafer 106 etc.Because etched tolerance (with the performance of the Semiconductor substrate device of last acquisition) extremely sensitive to this processing parameter, so require to be controlled exactly.
The surface of wafer 106 is etched by the suitable etchant source gas that is discharged in the wafer processing chamber 102.Can etchant source gas be discharged by shower nozzle.Also can use other mechanism, as via being configured in indoor gas ring or, etchant source gas being discharged via the spout of imbedding in wafer processing chamber 102 walls.In ion-assisted etch is handled, supply with radio frequency (RF) power of shower nozzle etchant source gas is lighted a fire, above wafer 106, forming plasma cloud (" plasma ") during the etch processes.Should be noted that the plasma exciting method that also can use other.For example, apply microwave energy, use induction coil, introduce electromagnetic wave, perhaps will be capacitively coupled to shower nozzle plasma is activated by antenna excitation.In ion-assisted etch is handled, with the radio frequency power source (not shown) chuck 104 is carried out radio-frequency driven typically.
In a kind of ion-assisted etching was handled, its local etching rate was controlled by ion concentration.Ion-assisted etching is handled and typically is used to oxide etching and polysilicon etching.In other words, ion-drive/assisted etch is handled and is commonly referred to as this etch processes, and in this processing, etching mainly is to become easy by the physical reactions of plasma ion that is accelerated (ion) and wafer (substrate).The application of ion-assisted etching comprises, for example, and sputter, reactive ion etching (RIE), chemical sputter, the chemical sputter that physically splash plating that chemistry is auxiliary and physics are auxiliary.
For ion-assisted etching, RF power is added on the chuck 104 (and shower nozzle 110) will above wafer 106, forms the shell of electric field and electric field itself.This electric field shell 112 of association with it impels ion to quicken to wafer 106 top surfaces.Ideally, the ion that is accelerated is angle (promptly being quadrature or the about 90 ° of angles basically) collision to be substantially perpendicular to wafer 106 surfaces during etch processes.This speeding-up ion of impacting wafer 106 helps " physics " etched wafer 106.
Side ring 108 is the insulating materials of a kind of float on electrically (not driven by RF).The ion bombardment during the etch processes is not freely come on the limit that side ring 108 is used to shield chuck 104.Side ring 108 can help wafer 106 is bombarded in ion focusing.Shown in Figure 1A, chuck 104 can be surrounded by the inner surface 114 of side ring 108.This inner surface 114 also is within the outside of wafer 106.
The outer surface 116 of side ring 108 exceeds the outside of wafer 106.The top of the inner surface 114 of side ring 108 not only with chuck 104, simultaneously also adjacent with wafer 106.Usually, the top surface 118 of side ring 108 is lower than the top surface of wafer 106 or is in same level with it.
Handling a subject matter that links mutually with the ion-assisted etching that uses conventional plasma processing apparatus is that the rate of etch on wafer 106 surfaces is inhomogeneous.Especially, near the rate of etch at Waffer edge position apparently higher than rate of etch near the each point of center wafer.Figure 1B is depicted as the sectional view of wafer 106 after the etch processes, and the etch depth of visible wafer 106 peripheral parts is greater than the etch depth of the mid portion of wafer 106.
This non-homogeneous rate of etch is mainly returned the non-uniform thickness of studying carefully in the shell 112 of wafer 106 surfaces.As shown in Figure 1A, the thickness of the shell 112 of the mid portion of wafer 106 (or density of the plasma gas on shell border) is obviously greater than the thickness (density) of the shell 112 of these wafer 106 peripheral parts.That is to say that its shell of vicinity in the district of electrically floating is at the periphery " bending " of wafer 106 above side ring 108.This shell bending that centers on wafer 106 peripheries makes during ion-assisted etching is handled near the periphery of more relatively ionic bombardment wafer 106.The higher collision rate causes near higher relatively rate of etch (the seeing Figure 1B) wafer perimeter near the periphery.
The shell bending also produces another problem.Especially, near the shell bending wafer 106 peripheries lures that ion is not to collide with the angle (promptly not being quadrature or about 90 ° of angles basically) of wafer 106 Surface Vertical basically into.In ion-assisted etching was handled, the ion collision of this non-perpendicular angle also can produce higher rate of etch.And, near the non-perpendicular angle of this ion collision the edge the etched parts on the wafer 106 (for example, groove, path or line) are had a kind of undesirable " inclination " effect.Tilt generally to refer to a kind of undesirable effect during the etching, thus a kind of one or more limits of parts surperficial perpendicular with wafer not basically.Herein, at the periphery of wafer 106, " inclination " effect produces nonsymmetrical component.Predetermined member is symmetrical, thus asymmetric be undesirable, and can cause serious problems and cause the integrated circuit of manufacturing to be scrapped substantially.
A kind of potential scheme that solves some problem that is associated with rate of etch inhomogeneities in the ion-assisted etching processing is to enlarge chuck to make it exceed Waffer edge.Enlarging chuck can make the shell sweep be shifted outside Waffer edge effectively.Perhaps, using this for pure chemical etch is a kind of feasible scheme.But it is infeasible handling this way for ion-assisted etching, because the extension of chuck will be exposed to ion and etching process.Chuck is exposed and can cause particle and/or serious metal contamination during the ion-assisted etching processing.The chuck exposed portions also may suffer from obviously high rate of etch and make with to stain the problem that is associated more complicated.And the rate of etch that the chuck expose portion is high can make chuck damage rapidly, causes the frequent replacing of whole chuck, but chuck but is a part expensive in the running stores.
To handle relevant some relevant problem of rate of etch heterogeneity in order reducing, might to change the distribution of wafer top plasma with ion-assisted etching.For example, by trying hard to plasma focus to wafer, believe that traditional focusing ring can be reduced in the ion concentration (plasma) that distributes on the Waffer edge at " focusing ring " that can place a kind of routine above the shell.If success, the reduction of plasma distribution can reduce near the rate of etch (promptly reducing the ion populations at bump edge) the wafer perimeter.The outer member of utilization such as focusing ring can compensate the shell curvature effect to a certain extent.But, in the ionization etch processes, introduce another element and may cause and contamination and/or the relevant new problem of valuable consumable part.In addition, concerning some ionization etch application, use traditional focusing ring or even infeasible.
Summary of the invention
Roughlly speaking, the present invention relates to be used for improving one's methods and installing of plasma handling system intermediate ion assisted etch processing.The present invention helps improving the etch rate uniformity of entire substrate (wafer).The present invention can realize in many ways, comprises as equipment, as device with as method.Several embodiments of the present invention are discussed below.
Disclose a kind of according to the present invention the improved plasma processing apparatus of a kind of embodiment of first kind of situation.This improved plasma processing apparatus includes the wafer processing chamber of electrostatic chuck (ESC) and lifting side ring.Chuck is as electrode and supporting wafers (being substrate) during manufacture.A kind of embodiment of this situation according to the present invention, edge joint circle of lifting side ring and chuck also upwards exceed the top surface of wafer.
Disclose a kind of according to the present invention the improved plasma processing apparatus of a kind of embodiment of second kind of situation.Herein, this plasma processing unit uses the side ring of flute profile.This flute profile side ring comprises a flute profile district, basically around near zone the Waffer edge and the zone below the bottom wafer surface.
Disclose a kind of according to the present invention the improved plasma processing apparatus of a kind of embodiment of the third situation.This improved plasma processing apparatus includes the wafer processing chamber that radio frequency (RF) drives the side ring that is connected with RF.Radio frequency side ring in succession places above the part of the chuck that RF drives and one side of adjacent substrate, RF coupling side ring in a part of radio-frequency (RF) energy that chuck provided that is driven by RF is coupled to simultaneously.
The invention provides a kind of plasma processing chamber that is used for etch substrate, said plasma processing chamber comprises: substrate has top surface, basal surface and limit; Radio frequency (RF) drives chuck, and said RF drives the basal surface that chuck supports at least a portion substrate; With interior RF coupling side ring, it places said RF to drive above the part of chuck and one side of adjacent substrate.A part of RF energy being coupled that chuck provided that wherein said RF drives is to said interior RF coupling side ring.The RF coupler that provides between the part of chuck is provided for RF coupling side ring and said RF in said.Wherein a part of RF energy that chuck provided that is driven by said RF is coupled to said interior RF coupling side ring by said RF coupler.
The present invention has many advantages.One of advantage of the present invention is that the etch rate uniformity on the substrate surface obviously improves.Another advantage of the present invention is that the obvious improvement of etch rate uniformity is to obtain under the risk situation that does not have process chamber to be stain.Also having an advantage is to eliminate etched inclination basically.
From the following detailed description, in conjunction with the accompanying drawing of the example of showing the principle of the invention, other aspects of the present invention and advantage will come into focus.
The accompanying drawing summary
By detailed description below in conjunction with accompanying drawing, will readily appreciate that present invention, wherein similar labelled notation homogeneous structure element, wherein:
Figure 1A illustrates the reduced graph of the plasma processing apparatus 100 that is suitable for the manufacturing of Semiconductor substrate device.
Figure 1B is depicted as wafer cross-section figure after the etch processes, the etched herein degree of depth at the peripheral part of wafer than big at the mid portion of wafer.
Shown in Figure 2 is a kind of embodiment of first kind of situation according to the present invention, includes the plasma processing apparatus of lifting side ring.
Shown in Figure 3 is a kind of embodiment of the 2nd kind of situation according to the present invention, includes the plasma processing apparatus 300 of flute profile side ring.
Shown in Figure 4 is a kind of embodiment of the 3rd kind of situation according to the present invention, the plasma processing apparatus 400 of RF coupling side ring and outer side ring in including.
Shown in Figure 5 is another embodiment of the third situation according to the present invention, includes the RF coupler, the plasma processing apparatus of interior RF coupling side ring and outer side ring.
Shown in Figure 6 is the another embodiment of the 3rd kind of situation according to the present invention, includes the part of cutaway view of the plasma processing apparatus 600 of dielectric filler.
Detailed Description Of The Invention
The invention relates to ion-assisted etching is handled in plasma process system improving one's methods and installing.The present invention helps improving the etch uniformity of entire substrate (wafer).The improvement of etch rate uniformity provided by the present invention has not only improved the manufacturing yield, and is cost-effective, and the risk of not emitting particle and/or heavy metal to stain.
2-6 discusses to the embodiment of several situations of the present invention below with reference to accompanying drawings.But, those skilled in the art will readily understand that the detailed description to these accompanying drawings is for illustrative purpose, because the present invention can be generalized to beyond these limited embodiments herein.
Shown in Figure 2 is the plasma processing apparatus 200 of a kind of embodiment of the 1st kind of situation according to the present invention.This plasma processing unit 200 includes the wafer processing chamber 202 of electrostatic chuck (ESC) 204.Chuck 204 during processing as electrode and supporting wafers (being substrate) 206.Edge joint circle of lifting side ring 208 and chuck 204 also extends upward the top surface that exceeds wafer 206.
The outer surface 216 of side ring 208 exceeds the outward flange of wafer 206.The top of the inner surface 214 of lifting side ring 208 comprises grooving district 218.Wafer 206 is placed in the grooving district 218 and the part on inner surface 114 tops is covered.The top surface 220 of lifting side ring 208 on the top surface of wafer 206 with it at a distance of a preset distance D.This preset distance D becomes according to the concrete special processing of implementing and being adopted.Typically, this preset distance D is about 1 to 10mm.In etch processes, one group of parameter in the wafer processing chamber 202 is subjected to controlling closely to keep the high accuracy etching result.The processing parameter of control etching result comprises gas componant, the excitation of plasma gas, the distribution of wafer 206 top plasmas etc.Because etch tolerance (thereby performance of the final Semiconductor substrate device that obtains) is to these processing parameter height sensitivities, so require to be controlled exactly.
The surface of wafer 206 is etched by the suitable etchant source gas that is discharged in the wafer processing chamber 202.This etchant source gas can discharge by shower nozzle 210.Etchant source gas also can be passed through other mechanism, such as by being placed in the compression ring in the wafer processing chamber 202, or discharges by the spout that is built on wafer processing chamber 202 walls.In ion-assisted etching is handled, supply with radio frequency (RF) power of shower nozzle 210 and during etch processes, etchant source gas is lighted a fire, above wafer, form plasma cloud (" plasma gas ") thus.Typically, in ion-assisted etching is handled, use RF source (not shown) that chuck 204RF is driven.
In a kind of ion-assisted etching was handled, local rate of etch was mainly controlled by ion concentration.Typically, ion-assisted etching is used to finish oxide etching or polysilicon etching.In other words, to handle and generally speaking refer to its etching mainly be physical reactions owing to the plasma ion that is accelerated (" ion ") same wafer (substrate) the easy etch processes that becomes for ion-drive/assisted etch.Ion-assisted etching is used and is comprised, for example, and sputter, reactive ion etching (RIE), chemical sputter, the physically splash plating that chemistry is auxiliary, and the auxiliary chemical sputter of physics.
For ion-assisted etching, RF power is added to chuck 206 (and shower nozzle 210) will above wafer 106, forms electric field, and electric field itself there is a shell 212.Follow the electric field of shell 212 to impel ion to quicken to wafer 106 top surfaces.Lifting side ring 208 extends upward the top surface that exceeds wafer 206 as described above.By side ring being extended on the top surface of wafer 206,208 pairs of shells 212 of this lifting side ring are revised.Particularly, in one embodiment, the thickness (density) of shell 212 becomes near wafer 206 peripheries, and the thickness (density) with wafer 206 mid portions is identical basically.Note, use lifting side ring 208 can make the shell 212 that obtains at last even basically in crystal 2 06 gamut.Compare with the shell among Figure 1A 112 this moment, and shell 212 obviously improves.Because the thickness (density) of shell 212 is even, the collision rate that obtains with conventional route that compares of the collision rate on ion and wafer 206 surfaces is more even significantly in entire wafer 206 scopes as a result.And the angle on ionic bombardment wafer 206 surfaces at the inner region of wafer 206, all is a quadrature in its surrounding zone simultaneously basically not only.Therefore, it is more even significantly that the rate of etch on the whole surface of wafer 206 compares to the rate of etch that conventional route obtains, and the etched parts in surrounding zone can not suffer damage because of " inclination " problem.
Figure 3 shows that the plasma processing apparatus 300 of a kind of embodiment of the 2nd kind of situation according to the present invention.This plasma processing unit includes the wafer processing chamber 302 of electrostatic chuck (ESC) 304.Chuck 304 is as electrode and supporting wafers 306 (being substrate) during processing.Edge joint circle of flute profile side ring 308 and chuck 304.
It is typically electrically the insulating material of float (not encouraged by RF) flute profile side ring 308.The edge that flute profile side ring 308 is used to shield chuck 304 exempts from ion bombardment during etch processes.As shown in Figure 3, chuck 304 is that inner surface 310 by side ring 308 is surrounded.Inner surface 310 also is within the outward flange of wafer 306.The outer surface 312 of flute profile side ring 308 has exceeded the outward flange of wafer 306.In one embodiment, the upper face of flute profile side ring 308 is in same plane with the upper face of wafer 306 basically.But flute profile side ring 308 has a flute profile district 318 at its upper face of adjacent wafer 306 edges.As shown in Figure 3, this flute profile district 318 is determined with the kerve mouth 324 that is connected the 1st and the 2nd ramp portion 320 and 322 by the 1st ramp portion 320, the 2 ramp portion 322.Ramped surfaces 320 is connected to the part area of coverage 322 with upper surface 314.
As previous the discussion, RF power is added to chuck 304 will above wafer 306, forms the shell of electric field and electric field itself.Follow the electric field of shell to impel ion to quicken to the top surface of wafer 106.Flute profile side ring 308 provides the flute profile district 318 that is in basically below wafer 106 edges.As shown in Figure 3, flute profile district 318 also can further extend, and further is lower than the basal surface of wafer 306 in the edge of wafer 306.In another embodiment, this flute profile district can only extend downward the basal surface of about wafer 306.
By the flute profile district is provided, the shell of 308 pairs of wafer 306 tops of this flute profile side ring plays correcting action.Particularly, in one embodiment, near the shell thickness (density) the wafer perimeter (edge) becomes more approaching with the thickness (density) of shell directly over the chuck 304 basically.The flute profile district that estimates flute profile side ring 308 is straight to abduction with shell effectively, so that shell flatten at the edge of wafer 306.
Because the inhomogeneity improvement of thickness (density) of shell above wafer 306, the collision rate on ion pair wafer 306 surfaces compare to the result who obtains with conventional route on wafer 306 whole surfaces more even.And the situation that the angle on ionic bombardment wafer 306 surfaces, the marginal zone of wafer 306 compares in Figure 1A ionic medium body processing unit more approaches quadrature.Therefore, the rate of etch that compares to the whole surface of conventional method wafer is more even, and etched parts are less because of the suffered influence of " inclination " problem in the surrounding zone.
Figure 4 shows that the plasma processing apparatus 400 of a kind of embodiment of the 3rd kind of situation according to the present invention.This plasma processing unit 400 includes the wafer processing chamber 402 of electrostatic chuck (ESC) 404.Chuck 404 is as electrode and supporting wafers 406 (being substrate) during processing.Interior RF coupling side ring 408 meets the boundary with the notch 410 of chuck 404, and the RF coupled zone that exceeds wafer 406 edges is provided.Outer side ring 412 meets the boundary with the outward flange of interior RF coupling side ring 408 and chuck 404.
The notch 410 that interior RF coupling side ring 408 is used to shield chuck 404 makes it to exempt from ion bombardment during etch processes.As shown in Figure 4, the inner surface 414 and the basal surface 416 of the notch 410 contiguous interior coupling side rings 408 of chuck 404.This inner surface 414 is also in the outward flange of wafer 406.The outer surface 418 of interior RF coupling side ring 408 has exceeded the outward flange of wafer 406 and has exceeded the outward flange 420 of chuck 404.The top of the inner surface 414 of RF coupling side ring 408 comprises grooving district 414.Wafer 406 just be seated in this grooving district 414 and with the inner surface of interior RF coupling side ring 408 and contiguous in slit between the outer surface of chuck 404 of RF coupling side ring 408 cover.The top surface 422 of interior RF coupling side ring 408 is in sustained height with the top surface of wafer 406 basically.The outer surface 418 of interior RF coupling side ring 408 is preset distance X apart from the distance at the edge of wafer 406.This preset distance X can become according to the special processing of concrete enforcement and employing.Typically, 1-2cm is suitable for the preset distance X that great majority are handled.
RF power is added to chuck 404 can form electric field and electric field generation itself above wafer 406 shell 424.The electric field that is attended by shell 424 impels ion to quicken to the top surface of wafer 406.Adopt the material of suitable performance manufacture in RF coupling side ring 408, a part of RF energy that makes it to supply with chuck 404 realizes that by interior RF coupling side ring 408 RF is coupled.The available multiple material that can not pollute plasma treatment is manufactured RF coupling side ring 408.Suitable examples of materials comprises semi-conducting material (for example, the carbide of silicon) or dielectric substance, and wherein the conductivity of material can be controlled by doping and similar approach.Select the material and the conductivity of interior RF coupling side ring 408 according to desirable RF degree of coupling.Typically, both can be thin by using, interior RF coupling side ring 408 also can be by increasing the coupling that improve RF as the conductivity of interior RF coupling side ring 408 materials.If RF coupling side ring 408 is etched in when wafer 406 is etched, then should produce and stain and should not be too expensive material, because it requires periodicity to change.On the other hand, in one embodiment, the material of outer side ring 412 does not provide any tangible RF coupling from chuck 404, therefore should not require periodic replacement to most of parts.
RF coupling side ring 408 helps providing the RF coupled zone that exceeds wafer 406 edges, makes the whole surface of the shell 424 of last acquisition at wafer 406, comprises the edge of wafer 406, has homogeneous thickness basically.By the RF coupled zone of extension is provided, the shell 424 of 408 pairs of wafer 406 tops of RF coupling side ring is revised.Particularly, in one embodiment, the thickness (or density) of shell 424 becomes basically identical with the thickness (density) of shell 424 directly over the chuck 404 near the wafer perimeter (edge).Notice that the thickness (density) of the shell 424 that obtains has at last improved the uniformity of the shell 424 in wafer 406 scopes significantly.Compare with the shell among Figure 1A 112, the shell 424 of wafer 406 tops obviously improves.
Because the uniform thickness (density) of wafer 406 top shells 424, the collision rate on ion pair wafer 406 surfaces is compared more even significantly on the whole surface of wafer 406 with the result that approach obtained with routine.And the angle of ion and wafer 406 surface collisions is not only in the inner region of wafer 406, and is essentially quadrature in its surrounding zone.Therefore, the rate of etch on whole surface of comparing wafer 406 with conventional method is more even, and does not suffer damage because of " inclination " problem at the etched parts of surrounding zone.
Figure 5 shows that the plasma processing apparatus 500 of the another embodiment of the 3rd kind of situation according to the present invention.Plasma processing apparatus 500 is included the wafer processing chamber 502 of electrostatic chuck (ESC) 504.Chuck 504 is during manufacture as electrode and supporting wafers 506 (being substrate).One edge joint circle of interior RF coupling side ring 508 and chuck 504 also provides a RF coupled zone that exceeds wafer 506 edges.One outer edge joint circle of outer side ring 512 and interior RF coupling side ring 508 and chuck 404.As shown in Figure 5, outer side ring 512 also meets the boundary with RF coupler 514.
The top surface of RF coupler 514 is located immediately under the basal surface of interior RF coupling loop 508.Interior RF coupling loop 508 shields RF coupler 514 mutually with etch processes (being ion bombardment).The notch 516 that interior RF coupling loop 508 and RF coupler 514 are used to shield chuck 504 avoids ion bombardment.
As shown in Figure 5, RF coupler 514 is located like this, makes the inner surface 518 and the basal surface 520 of the notch 516 contiguous RF couplers 514 of chuck 504.Inner surface 518 also is within the outside of wafer 506.Similar with interior RF coupling side ring 508, the outer surface of RF coupler 514 exceeds the outward flange of wafer 406 and exceeds the outward flange 522 of chuck 504.
In addition, if RF coupler 514 conductively-closeds and be not subjected to ion bombardment, hope, available high conductivity is manufactured the quantity of the RF energy that RF coupler 514 is coupled with increase.In one embodiment, the RF coupler can use the high conductivity (for example, aluminium) of dielectric substance (for example, anodization cross aluminium) coating (or layer) parcel to manufacture.Therefore, both can be by having used thin coating, or the conductivity that increases the material that is used as RF coupler 514 is improved the coupling of RF.
And as shown in Figure 5, outer side ring 512 has a lap 524, and this part has upwards exceeded the top surface of interior RF coupling side ring 508.Any shielding of cracking that this lap 524 may exist.So just provide better protection for the outer surface of chuck 504 and the outer surface of RF coupler 514.
As discussed previously such, the RF function is added to chuck 504 will above wafer 506, forms the shell of electric field and electric field itself.The electric field that is attended by shell impels ion to quicken to wafer top surface.Interior RF coupling side ring 508 helps providing the RF coupled zone, and this coupled zone exceeds the edge of wafer 506, and the shell that makes it finally to obtain comprises the limit of wafer 506 on the whole surface of wafer 506, homogeneous thickness is basically arranged.By a kind of RF coupled zone of extension is provided, the shell of 508 pairs of wafer 506 tops of RF coupling side ring is revised.Particularly, in one embodiment, near the thickness (density) the wafer perimeter (edge) becomes, and the thickness (density) with shell directly over the chuck is identical basically.As discussed earlier, the shell thickness that obtains at last (density) has improved the shell uniformity in wafer 506 scopes significantly.Therefore, compare with the shell of Figure 1A, the shell of wafer 506 tops has had tangible improvement.
Because wafer 406 top shells have homogeneous thickness (density), compare with the approach of routine, ion is more even significantly in the whole surface range of wafer 506 with the collision rate on wafer 506 surfaces.And the collision angle on ion and wafer 506 surfaces is not only in the inner region of wafer 506, and is essentially quadrature in the neighboring area.Therefore, the rate of etch on whole surface of comparing wafer 506 with conventional method is more even, and can not suffer damage because of " inclination " problem in the etched details of surrounding zone.
Figure 6 shows that the part of the plasma processing apparatus 600 of the another other embodiment of the 3rd kind of situation according to the present invention.This plasma processing unit 600 includes the wafer processing chamber 602 of electrostatic chuck (ESC) 604 (side of sectional view only is shown).Chuck 604 during processing as electrode and supporting wafers 604 (being substrate).Edge joint circle of interior RF coupling side ring 608 and chuck 604 also provides a RF coupled zone that exceeds wafer 606 edges.Edge joint circle of outer side ring 610 and interior RF coupling side ring 608.RF coupler 612 is positioned at below the RF coupling side ring 608 and and edge joint circle of chuck 604.In being seated in, dielectric filler 614 meets the boundary under the RF coupling side ring 608 and with RF coupler 612.A top of the contiguous chuck 604 of the basal surface of dielectric filler 614.
Dielectric has to be beneficial to aspect the RF electric energy that focuses on the RF coupling big or small provides even more flexibility.Dielectric filler 614 can make any coupling minimum of external side ring 610.For example, can use the suitable insulation material, such as pottery, quartz, polytetrafluoroethylene and polymer are manufactured dielectric filler 614.Also can control the size of insulation as the thickness of the material of dielectric filler 614 by selection.
Dielectric filler 616 is placed on below the outer side ring 610.One outer edge joint circle of dielectric filler 616 and chuck 604.It is isolated with the corrosion inhibitor district of outer corrosion inhibitor rings 618 that being positioned with of dielectric filler 616 is beneficial to the chuck 604 that RF is driven.Typically, corrosion inhibitor ring 618 be positioned at wafer processing chamber 602 a wall near.
The same with what Fig. 4 and Fig. 5 were discussed, by the RF coupled zone that exceeds wafer 604 edges is provided, the shell of wafer 604 tops is revised.Therefore, with comparing with the result that conventional method obtained, the rate of etch on wafer 606 whole surfaces is more even, and the etched parts in surrounding zone can not suffer damage because of " inclination " problem.
Can manufacture various side ring discussed above with material relatively inexpensive and that be easy to process and/or change.This material can be selected from the quite multiple material that is suitable for special etch processes.
The present invention has many advantages.One of advantage of the present invention is that the etch rate uniformity on entire substrate surface obviously improves.Another advantage of the present invention is that the obvious improvement of etch rate uniformity is to obtain under the situation of not emitting the process chamber risk of contamination.Also having an advantage is to eliminate the inclination of etched parts basically.
Though only several embodiments of the present invention are described in detail, much less, the present invention can many other special forms be implemented and can not be departed from the spirit and scope of the present invention.Therefore, present example is as showing property and nonrestrictive, and the present invention simultaneously is not limited to the given specification specified of this paper, but can correct in appended claim scope.
Claims (14)
1. plasma processing chamber that is used for etch substrate, this substrate has top surface, basal surface and limit, and said plasma processing chamber comprises:
The chuck that radio frequency drives, said RF drives at least a portion of chuck support substrates basal surface;
The lifting side ring that inner surface and upper surface are arranged, its inner surface place said RF to drive above the part of chuck and the limit of adjacent substrate, and upper surface has a lifting distance of being scheduled to the top surface of substrate, and the inner surface of described lifting side ring comprises the grooving district.
2. the plasma processing chamber of claim 1, wherein the lifting side ring surrounds substrate.
3. the plasma processing chamber of claim 1, wherein substrate is a wafer.
4. the plasma processing chamber of claim 1, wherein the lifting side ring is made up of dielectric substance basically.
5. the plasma processing chamber of claim 1, wherein predetermined lifting distance is between 1 to 10 millimeter.
6. plasma processing chamber that is used for etch substrate, this substrate has top surface, basal surface and limit, and said plasma processing chamber comprises:
The chuck that radio frequency drives, the chuck that said RF drives supports the basal surface of at least a portion substrate; With
Flute profile side ring, its inner surface place above the chuck part that said RF drives and the adjacent substrate edge and
Wherein the flute profile side ring provides the flute profile district at the adjacent substrate edge.
7. the plasma processing chamber of claim 6, wherein the flute profile district of flute profile side ring is around substrate.
8. the plasma processing chamber of claim 6, wherein substrate is a wafer.
9. the plasma processing chamber of claim 6, wherein the flute profile side ring is made up of dielectric substance basically.
10. the plasma processing chamber of claim 6, wherein the basal surface in flute profile district is positioned at next preset distance of substrate basal surface.
11. the plasma processing chamber of claim 6, wherein the slope that covers of the second portion that partly covers by first slope with by the substrate basal surface of flute profile district limits, and this first slope is connected the slope of upper surface with this part covering.
12. the plasma processing chamber of claim 6, flute profile side ring (308) provide the flute profile district (318) that is in below substrate (106) edge.
13. the plasma processing chamber of claim 6, extend in the bottom surface that is lower than substrate (306) edge flute profile district (318).
14. the plasma processing chamber of claim 6, flute profile district (318) extend to the basal surface of substrate (306).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/345639 | 1999-06-30 | ||
| US09/345,639 US6344105B1 (en) | 1999-06-30 | 1999-06-30 | Techniques for improving etch rate uniformity |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008097933A Division CN100392791C (en) | 1999-06-30 | 2000-06-29 | Techniques for improving etch rate uniformity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101241846A CN101241846A (en) | 2008-08-13 |
| CN101241846B true CN101241846B (en) | 2010-08-11 |
Family
ID=23355856
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100852345A Expired - Lifetime CN101241846B (en) | 1999-06-30 | 2000-06-29 | Techniques for improving etch rate uniformity |
| CNB008097933A Expired - Lifetime CN100392791C (en) | 1999-06-30 | 2000-06-29 | Techniques for improving etch rate uniformity |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008097933A Expired - Lifetime CN100392791C (en) | 1999-06-30 | 2000-06-29 | Techniques for improving etch rate uniformity |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6344105B1 (en) |
| EP (2) | EP1898444B1 (en) |
| JP (2) | JP4792185B2 (en) |
| KR (1) | KR100743872B1 (en) |
| CN (2) | CN101241846B (en) |
| AU (1) | AU5908600A (en) |
| DE (2) | DE60038175T2 (en) |
| TW (1) | TW463235B (en) |
| WO (1) | WO2001001445A1 (en) |
Families Citing this family (112)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5662770A (en) * | 1993-04-16 | 1997-09-02 | Micron Technology, Inc. | Method and apparatus for improving etch uniformity in remote source plasma reactors with powered wafer chucks |
| US6334960B1 (en) * | 1999-03-11 | 2002-01-01 | Board Of Regents, The University Of Texas System | Step and flash imprint lithography |
| KR100315088B1 (en) * | 1999-09-29 | 2001-11-24 | 윤종용 | Apparatus for processing semiconductor wafer having focus ring |
| US6489249B1 (en) * | 2000-06-20 | 2002-12-03 | Infineon Technologies Ag | Elimination/reduction of black silicon in DT etch |
| TW506234B (en) * | 2000-09-18 | 2002-10-11 | Tokyo Electron Ltd | Tunable focus ring for plasma processing |
| US6475336B1 (en) * | 2000-10-06 | 2002-11-05 | Lam Research Corporation | Electrostatically clamped edge ring for plasma processing |
| US6554954B2 (en) * | 2001-04-03 | 2003-04-29 | Applied Materials Inc. | Conductive collar surrounding semiconductor workpiece in plasma chamber |
| TWI234417B (en) * | 2001-07-10 | 2005-06-11 | Tokyo Electron Ltd | Plasma procesor and plasma processing method |
| DE10143718A1 (en) * | 2001-08-31 | 2003-03-27 | Infineon Technologies Ag | Mounting device for wafer in plasma etching plant has sealant introduced into free space between wafer and electrode |
| US7041201B2 (en) * | 2001-11-14 | 2006-05-09 | Applied Materials, Inc. | Sidewall magnet improving uniformity of inductively coupled plasma and shields used therewith |
| WO2003054947A1 (en) * | 2001-12-13 | 2003-07-03 | Tokyo Electron Limited | Ring mechanism, and plasma processing device using the ring mechanism |
| US20030159778A1 (en) * | 2002-02-27 | 2003-08-28 | Kunihiko Koroyasu | Plasma processing apparatus, protecting layer therefor and installation of protecting layer |
| US20040000375A1 (en) * | 2002-06-27 | 2004-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Plasma etch chamber equipped with multi-layer insert ring |
| US20040040663A1 (en) * | 2002-08-29 | 2004-03-04 | Ryujiro Udo | Plasma processing apparatus |
| US20040112862A1 (en) * | 2002-12-12 | 2004-06-17 | Molecular Imprints, Inc. | Planarization composition and method of patterning a substrate using the same |
| DE10260645B3 (en) * | 2002-12-23 | 2004-09-16 | Infineon Technologies Ag | Compensation frame for holding substrate for semiconducting manufacture has polygonal inner profile for holding substrate, area of upper main surface of frame with different widths at different points |
| US20040168613A1 (en) * | 2003-02-27 | 2004-09-02 | Molecular Imprints, Inc. | Composition and method to form a release layer |
| US7540935B2 (en) * | 2003-03-14 | 2009-06-02 | Lam Research Corporation | Plasma oxidation and removal of oxidized material |
| KR101141488B1 (en) * | 2003-03-21 | 2012-05-03 | 도쿄엘렉트론가부시키가이샤 | Method and apparatus for reducing substrate backside deposition during processing |
| US7049052B2 (en) * | 2003-05-09 | 2006-05-23 | Lam Research Corporation | Method providing an improved bi-layer photoresist pattern |
| US20040226516A1 (en) * | 2003-05-13 | 2004-11-18 | Daniel Timothy J. | Wafer pedestal cover |
| CN100463112C (en) * | 2003-05-30 | 2009-02-18 | 周星工程股份有限公司 | Apparatus for semiconductor device |
| US7307118B2 (en) * | 2004-11-24 | 2007-12-11 | Molecular Imprints, Inc. | Composition to reduce adhesion between a conformable region and a mold |
| US7157036B2 (en) * | 2003-06-17 | 2007-01-02 | Molecular Imprints, Inc | Method to reduce adhesion between a conformable region and a pattern of a mold |
| US20050160934A1 (en) * | 2004-01-23 | 2005-07-28 | Molecular Imprints, Inc. | Materials and methods for imprint lithography |
| US20060108710A1 (en) * | 2004-11-24 | 2006-05-25 | Molecular Imprints, Inc. | Method to reduce adhesion between a conformable region and a mold |
| US7658816B2 (en) | 2003-09-05 | 2010-02-09 | Tokyo Electron Limited | Focus ring and plasma processing apparatus |
| US7024105B2 (en) * | 2003-10-10 | 2006-04-04 | Applied Materials Inc. | Substrate heater assembly |
| US7122482B2 (en) | 2003-10-27 | 2006-10-17 | Molecular Imprints, Inc. | Methods for fabricating patterned features utilizing imprint lithography |
| US7244336B2 (en) * | 2003-12-17 | 2007-07-17 | Lam Research Corporation | Temperature controlled hot edge ring assembly for reducing plasma reactor etch rate drift |
| US7338578B2 (en) * | 2004-01-20 | 2008-03-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Step edge insert ring for etch chamber |
| US8076386B2 (en) * | 2004-02-23 | 2011-12-13 | Molecular Imprints, Inc. | Materials for imprint lithography |
| US20050189068A1 (en) * | 2004-02-27 | 2005-09-01 | Kawasaki Microelectronics, Inc. | Plasma processing apparatus and method of plasma processing |
| JP3981091B2 (en) * | 2004-03-01 | 2007-09-26 | 株式会社東芝 | Film-forming ring and semiconductor device manufacturing equipment |
| US20050193951A1 (en) * | 2004-03-08 | 2005-09-08 | Muneo Furuse | Plasma processing apparatus |
| JP2005303099A (en) | 2004-04-14 | 2005-10-27 | Hitachi High-Technologies Corp | Apparatus and method for plasma processing |
| US7939131B2 (en) | 2004-08-16 | 2011-05-10 | Molecular Imprints, Inc. | Method to provide a layer with uniform etch characteristics |
| US7282550B2 (en) * | 2004-08-16 | 2007-10-16 | Molecular Imprints, Inc. | Composition to provide a layer with uniform etch characteristics |
| US20060062922A1 (en) * | 2004-09-23 | 2006-03-23 | Molecular Imprints, Inc. | Polymerization technique to attenuate oxygen inhibition of solidification of liquids and composition therefor |
| US7578945B2 (en) * | 2004-09-27 | 2009-08-25 | Lam Research Corporation | Method and apparatus for tuning a set of plasma processing steps |
| US7138067B2 (en) * | 2004-09-27 | 2006-11-21 | Lam Research Corporation | Methods and apparatus for tuning a set of plasma processing steps |
| US7244311B2 (en) * | 2004-10-13 | 2007-07-17 | Lam Research Corporation | Heat transfer system for improved semiconductor processing uniformity |
| US20060081557A1 (en) * | 2004-10-18 | 2006-04-20 | Molecular Imprints, Inc. | Low-k dielectric functional imprinting materials |
| GB0424371D0 (en) * | 2004-11-04 | 2004-12-08 | Trikon Technologies Ltd | Shielding design for backside metal deposition |
| JP4336320B2 (en) * | 2005-02-25 | 2009-09-30 | キヤノンアネルバ株式会社 | Wafer holder |
| US9659758B2 (en) * | 2005-03-22 | 2017-05-23 | Honeywell International Inc. | Coils utilized in vapor deposition applications and methods of production |
| US20060219172A1 (en) * | 2005-04-05 | 2006-10-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | PVD equipment and electrode and deposition ring thereof |
| KR100714896B1 (en) * | 2005-06-08 | 2007-05-04 | 삼성전자주식회사 | Focus ring of dry etching apparatus |
| US20060278520A1 (en) * | 2005-06-13 | 2006-12-14 | Lee Eal H | Use of DC magnetron sputtering systems |
| KR100688747B1 (en) | 2005-06-27 | 2007-03-02 | 동부일렉트로닉스 주식회사 | Apparatus and method for etching wafer edge |
| US8557351B2 (en) * | 2005-07-22 | 2013-10-15 | Molecular Imprints, Inc. | Method for adhering materials together |
| US7759407B2 (en) * | 2005-07-22 | 2010-07-20 | Molecular Imprints, Inc. | Composition for adhering materials together |
| US8808808B2 (en) | 2005-07-22 | 2014-08-19 | Molecular Imprints, Inc. | Method for imprint lithography utilizing an adhesion primer layer |
| WO2007034747A1 (en) * | 2005-09-22 | 2007-03-29 | Sekisui Chemical Co., Ltd. | Plasma processing device |
| KR101153118B1 (en) * | 2005-10-12 | 2012-06-07 | 파나소닉 주식회사 | Plasma processing apparatus and plasma processing method |
| US7651571B2 (en) * | 2005-12-22 | 2010-01-26 | Kyocera Corporation | Susceptor |
| JP2007250967A (en) * | 2006-03-17 | 2007-09-27 | Tokyo Electron Ltd | Plasma treating apparatus and method, and focus ring |
| US8635971B2 (en) * | 2006-03-31 | 2014-01-28 | Lam Research Corporation | Tunable uniformity in a plasma processing system |
| US20080194113A1 (en) * | 2006-09-20 | 2008-08-14 | Samsung Electronics Co., Ltd. | Methods and apparatus for semiconductor etching including an electro static chuck |
| KR100809957B1 (en) * | 2006-09-20 | 2008-03-07 | 삼성전자주식회사 | Semiconductor etching device |
| US20080110557A1 (en) * | 2006-11-15 | 2008-05-15 | Molecular Imprints, Inc. | Methods and Compositions for Providing Preferential Adhesion and Release of Adjacent Surfaces |
| US20080296261A1 (en) * | 2007-06-01 | 2008-12-04 | Nordson Corporation | Apparatus and methods for improving treatment uniformity in a plasma process |
| US7837827B2 (en) * | 2007-06-28 | 2010-11-23 | Lam Research Corporation | Edge ring arrangements for substrate processing |
| US8999106B2 (en) * | 2007-12-19 | 2015-04-07 | Applied Materials, Inc. | Apparatus and method for controlling edge performance in an inductively coupled plasma chamber |
| US20090194414A1 (en) * | 2008-01-31 | 2009-08-06 | Nolander Ira G | Modified sputtering target and deposition components, methods of production and uses thereof |
| US8409355B2 (en) * | 2008-04-24 | 2013-04-02 | Applied Materials, Inc. | Low profile process kit |
| US20100101729A1 (en) * | 2008-10-28 | 2010-04-29 | Applied Materials, Inc. | Process kit having reduced erosion sensitivity |
| KR101063588B1 (en) * | 2008-11-05 | 2011-09-07 | 주식회사 디엠에스 | Electrostatic chuck assembly with structure to extend the life of cover ring and improve the etching performance of plasma reactor |
| KR101540609B1 (en) * | 2009-02-24 | 2015-07-31 | 삼성전자 주식회사 | Apparatus for etching edge of wafer |
| KR101343502B1 (en) * | 2009-07-24 | 2013-12-19 | 엘지디스플레이 주식회사 | Coater chuck of coating apparatus |
| WO2011058851A1 (en) * | 2009-11-16 | 2011-05-19 | シャープ株式会社 | Dry etching apparatus and dry etching method |
| JP6285620B2 (en) * | 2011-08-26 | 2018-02-28 | 新光電気工業株式会社 | Electrostatic chuck and semiconductor / liquid crystal manufacturing equipment |
| US9376752B2 (en) * | 2012-04-06 | 2016-06-28 | Applied Materials, Inc. | Edge ring for a deposition chamber |
| KR20140101996A (en) * | 2013-02-13 | 2014-08-21 | 삼성전자주식회사 | Unit for supporting a substrate and apparatus for etching substrate using plasma with the same |
| US9997381B2 (en) * | 2013-02-18 | 2018-06-12 | Lam Research Corporation | Hybrid edge ring for plasma wafer processing |
| WO2015116245A1 (en) * | 2014-01-30 | 2015-08-06 | Applied Materials, Inc. | Gas confiner assembly for eliminating shadow frame |
| US10242848B2 (en) * | 2014-12-12 | 2019-03-26 | Lam Research Corporation | Carrier ring structure and chamber systems including the same |
| JP2016184610A (en) * | 2015-03-25 | 2016-10-20 | 株式会社東芝 | Upper electrode, edge ring and plasma processing apparatus |
| US10903055B2 (en) | 2015-04-17 | 2021-01-26 | Applied Materials, Inc. | Edge ring for bevel polymer reduction |
| JP6570971B2 (en) * | 2015-05-27 | 2019-09-04 | 東京エレクトロン株式会社 | Plasma processing apparatus and focus ring |
| US10755902B2 (en) * | 2015-05-27 | 2020-08-25 | Tokyo Electron Limited | Plasma processing apparatus and focus ring |
| US10854492B2 (en) * | 2015-08-18 | 2020-12-01 | Lam Research Corporation | Edge ring assembly for improving feature profile tilting at extreme edge of wafer |
| KR101722382B1 (en) * | 2016-01-08 | 2017-04-03 | 주식회사 윈텔 | Plasma Processing Apparatus |
| JP6888007B2 (en) * | 2016-01-26 | 2021-06-16 | アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ | Wafer edge ring lifting solution |
| CN107316795B (en) * | 2016-04-26 | 2020-01-03 | 北京北方华创微电子装备有限公司 | Focusing ring and plasma processing device |
| US10163642B2 (en) * | 2016-06-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device, method and tool of manufacture |
| JP2018006299A (en) | 2016-07-08 | 2018-01-11 | 東芝メモリ株式会社 | Processing object susceptor for plasma processing apparatus, plasma processing apparatus and plasma processing method |
| US20180122670A1 (en) * | 2016-11-01 | 2018-05-03 | Varian Semiconductor Equipment Associates, Inc. | Removable substrate plane structure ring |
| US10032661B2 (en) | 2016-11-18 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device, method, and tool of manufacture |
| US11251026B2 (en) * | 2017-03-31 | 2022-02-15 | Mattson Technology, Inc. | Material deposition prevention on a workpiece in a process chamber |
| KR101966793B1 (en) * | 2017-05-17 | 2019-04-09 | 세메스 주식회사 | Substrate supporting unit and substrate processing apparatus comprising the same |
| US11183373B2 (en) | 2017-10-11 | 2021-11-23 | Honeywell International Inc. | Multi-patterned sputter traps and methods of making |
| JP6966286B2 (en) * | 2017-10-11 | 2021-11-10 | 東京エレクトロン株式会社 | Plasma processing device, focus ring elevation control method and focus ring elevation control program |
| KR102089949B1 (en) * | 2017-10-20 | 2020-03-19 | 세메스 주식회사 | Substrate treating apparatus component of substrate treating apparatus |
| WO2020081644A1 (en) * | 2018-10-18 | 2020-04-23 | Lam Research Corporation | Lower plasma exclusion zone ring for bevel etcher |
| JP7117734B2 (en) * | 2018-12-06 | 2022-08-15 | 東京エレクトロン株式会社 | Plasma processing apparatus and plasma processing method |
| US11551965B2 (en) * | 2018-12-07 | 2023-01-10 | Applied Materials, Inc. | Apparatus to reduce polymers deposition |
| KR102647177B1 (en) * | 2019-02-11 | 2024-03-15 | 삼성전자주식회사 | Plasma processing apparatus |
| JP2022537038A (en) * | 2019-06-18 | 2022-08-23 | ラム リサーチ コーポレーション | Reduced diameter carrier ring hardware for substrate processing systems |
| US11302563B2 (en) * | 2019-06-20 | 2022-04-12 | Corning Incorporated | Carrier for back end of line processing |
| KR102214333B1 (en) | 2019-06-27 | 2021-02-10 | 세메스 주식회사 | Apparatus and method for treating substrate |
| CN112885690B (en) * | 2019-11-29 | 2023-10-20 | 中微半导体设备(上海)股份有限公司 | Plasma processing device |
| CN112992631B (en) * | 2019-12-16 | 2023-09-29 | 中微半导体设备(上海)股份有限公司 | Lower electrode assembly, installation method thereof and plasma processing device |
| CN111312630A (en) * | 2020-03-05 | 2020-06-19 | 锐捷光电科技（江苏）有限公司 | Method for improving etching uniformity of single sealing leather ring |
| JP7398988B2 (en) * | 2020-03-13 | 2023-12-15 | 東京エレクトロン株式会社 | sputtering equipment |
| KR102177146B1 (en) * | 2020-04-10 | 2020-11-10 | 비씨엔씨 주식회사 | Edge ring for plasma process chamber |
| USD1034491S1 (en) | 2020-07-27 | 2024-07-09 | Applied Materials, Inc. | Edge ring |
| US11380575B2 (en) * | 2020-07-27 | 2022-07-05 | Applied Materials, Inc. | Film thickness uniformity improvement using edge ring and bias electrode geometry |
| US12106943B2 (en) | 2021-05-25 | 2024-10-01 | Applied Materials, Inc. | Substrate halo arrangement for improved process uniformity |
| US20230066418A1 (en) * | 2021-08-30 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Focus ring for a plasma-based semiconductor processing tool |
| CN113921365B (en) * | 2021-09-29 | 2024-03-26 | 北京北方华创微电子装备有限公司 | Semiconductor process equipment and edge protection mechanism thereof |
| KR20230094576A (en) | 2021-12-21 | 2023-06-28 | 삼성전자주식회사 | Ring assembly, substrate support apparatus and plasma processing apparatus having the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5213658A (en) * | 1990-10-26 | 1993-05-25 | Mitsubishi Denki Kabushiki Kaisha | Plasma processing method |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100297358B1 (en) * | 1991-07-23 | 2001-11-30 | 히가시 데쓰로 | Plasma Etching Equipment |
| US5411624A (en) * | 1991-07-23 | 1995-05-02 | Tokyo Electron Limited | Magnetron plasma processing apparatus |
| JPH0529270A (en) * | 1991-07-23 | 1993-02-05 | Tokyo Electron Ltd | Magnetron plasma processing device |
| US5662770A (en) | 1993-04-16 | 1997-09-02 | Micron Technology, Inc. | Method and apparatus for improving etch uniformity in remote source plasma reactors with powered wafer chucks |
| JP2638443B2 (en) | 1993-08-31 | 1997-08-06 | 日本電気株式会社 | Dry etching method and dry etching apparatus |
| KR100264445B1 (en) * | 1993-10-04 | 2000-11-01 | 히가시 데쓰로 | Plasma treatment equipment |
| US5463525A (en) | 1993-12-20 | 1995-10-31 | International Business Machines Corporation | Guard ring electrostatic chuck |
| JP3257741B2 (en) * | 1994-03-03 | 2002-02-18 | 東京エレクトロン株式会社 | Plasma etching apparatus and method |
| JP2659919B2 (en) | 1994-01-13 | 1997-09-30 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Plasma device for correcting non-uniformity of plasma |
| US5891348A (en) | 1996-01-26 | 1999-04-06 | Applied Materials, Inc. | Process gas focusing apparatus and method |
| JPH09213683A (en) * | 1996-02-07 | 1997-08-15 | Sony Corp | Plasma etching device |
| US6113731A (en) * | 1997-01-02 | 2000-09-05 | Applied Materials, Inc. | Magnetically-enhanced plasma chamber with non-uniform magnetic field |
| JP4602545B2 (en) * | 1997-09-16 | 2010-12-22 | アプライド マテリアルズ インコーポレイテッド | Shroud for semiconductor workpiece in plasma chamber |
| US6074488A (en) | 1997-09-16 | 2000-06-13 | Applied Materials, Inc | Plasma chamber support having an electrically coupled collar ring |
| US6039836A (en) | 1997-12-19 | 2000-03-21 | Lam Research Corporation | Focus rings |
| KR100258984B1 (en) * | 1997-12-24 | 2000-08-01 | 윤종용 | Dry etching apparatus |
| US6117349A (en) * | 1998-08-28 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite shadow ring equipped with a sacrificial inner ring |
-
1999
- 1999-06-30 US US09/345,639 patent/US6344105B1/en not_active Expired - Lifetime
-
2000
- 2000-06-28 TW TW089112761A patent/TW463235B/en not_active IP Right Cessation
- 2000-06-29 DE DE60038175T patent/DE60038175T2/en not_active Expired - Lifetime
- 2000-06-29 EP EP07023156A patent/EP1898444B1/en not_active Expired - Lifetime
- 2000-06-29 KR KR1020017016518A patent/KR100743872B1/en active IP Right Grant
- 2000-06-29 EP EP00945097A patent/EP1198821B1/en not_active Expired - Lifetime
- 2000-06-29 CN CN2008100852345A patent/CN101241846B/en not_active Expired - Lifetime
- 2000-06-29 CN CNB008097933A patent/CN100392791C/en not_active Expired - Lifetime
- 2000-06-29 AU AU59086/00A patent/AU5908600A/en not_active Abandoned
- 2000-06-29 DE DE60044958T patent/DE60044958D1/en not_active Expired - Lifetime
- 2000-06-29 JP JP2001506576A patent/JP4792185B2/en not_active Expired - Lifetime
- 2000-06-29 WO PCT/US2000/018234 patent/WO2001001445A1/en active IP Right Grant
-
2010
- 2010-10-21 JP JP2010236658A patent/JP2011014943A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5213658A (en) * | 1990-10-26 | 1993-05-25 | Mitsubishi Denki Kabushiki Kaisha | Plasma processing method |
Also Published As
| Publication number | Publication date |
|---|---|
| DE60038175D1 (en) | 2008-04-10 |
| AU5908600A (en) | 2001-01-31 |
| CN100392791C (en) | 2008-06-04 |
| DE60044958D1 (en) | 2010-10-21 |
| TW463235B (en) | 2001-11-11 |
| CN1373899A (en) | 2002-10-09 |
| EP1898444B1 (en) | 2010-09-08 |
| EP1198821B1 (en) | 2008-02-27 |
| KR20020041340A (en) | 2002-06-01 |
| EP1898444A1 (en) | 2008-03-12 |
| KR100743872B1 (en) | 2007-07-30 |
| JP2011014943A (en) | 2011-01-20 |
| JP4792185B2 (en) | 2011-10-12 |
| EP1198821A1 (en) | 2002-04-24 |
| DE60038175T2 (en) | 2009-03-12 |
| JP2003503841A (en) | 2003-01-28 |
| US6344105B1 (en) | 2002-02-05 |
| CN101241846A (en) | 2008-08-13 |
| WO2001001445A1 (en) | 2001-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101241846B (en) | Techniques for improving etch rate uniformity | |
| US9997381B2 (en) | Hybrid edge ring for plasma wafer processing | |
| EP1446825B1 (en) | Apparatus and method for improving etch rate uniformity | |
| KR101342319B1 (en) | Integrated capacitive and inductive power sources for a plasma etching chamber | |
| US6320320B1 (en) | Method and apparatus for producing uniform process rates | |
| EP1230666B1 (en) | Plasma processing systems and method therefor | |
| US6806437B2 (en) | Inductively coupled plasma generating apparatus incorporating double-layered coil antenna | |
| JP5554705B2 (en) | Method and apparatus for substrate processing | |
| US20110011534A1 (en) | Apparatus for adjusting an edge ring potential during substrate processing | |
| US6518190B1 (en) | Plasma reactor with dry clean apparatus and method | |
| KR19980032909A (en) | Parallel plate plasma reactor inductively connected to a conical dome | |
| KR20130077880A (en) | Plasma processing apparatus | |
| CN1647238A (en) | Faraday shields and plasma wafer processing | |
| CN1432188A (en) | Method and appts. for forming inner magnetic bucket to control volume of plasma | |
| CN1555568A (en) | Method and apparatus for producing uniform process rates | |
| US7088047B2 (en) | Inductively coupled plasma generator having low aspect ratio | |
| US20030084999A1 (en) | Apparatus and method for mitigating chamber resonances in plasma processing | |
| CN114975056A (en) | Conductive member for cleaning focus ring of plasma processing apparatus | |
| KR101281191B1 (en) | Inductively coupled plasma reactor capable | |
| KR20240107345A (en) | Multiple antenna units for large-area inductively coupled plasma processing devices | |
| KR20240107361A (en) | High density plasma enhanced process chamber | |
| KR101002260B1 (en) | Compound plasma reactor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100811 |