CN101233475B - 增加于多核心处理器上的一个或多个核心的工作量效能 - Google Patents
增加于多核心处理器上的一个或多个核心的工作量效能 Download PDFInfo
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Abstract
整合在单一集成电路芯片上的处理节点(12)包括第一处理器核心(18A)及第二处理器核心(18B)。该处理节点亦包括在该第一处理器核心及该第二处理器核心中之一者执行的操作系统(13A、13B)。该操作系统可监视该第一处理器核心及该第二处理器核心之电流使用(current utilization)。响应检测到该第一处理器核心操作低于使用临限值,该操作系统可使该第一处理器核心操作在低于系统最大性能水平的性能水平,并可使该第二处理器核心操作在高于该系统最大性能水平的性能水平。
Description
技术领域
本发明系关于多核心处理器,且详而言之,系关于多核心处理器环境内之工作量效能。
背景技术
单芯片多处理器(chip multiprocessor,CMP)目前系日益普遍。CMP系将两个或更多个处理器核心实施在相同集成电路上。CMP系能比如较为复杂的单处理器更有效的利用包含于集成电路的数以百万的晶体管。
在许多情况中,CMP可藉由具有不只一个处理器执行中央处理工作而增加系统之运算能力。此外,CMP藉由分担该处理工作量,当相较于单核心处理器以其最大频率运作时,系能增加其处理效率并能降低整体热流及功率预算。
然而,在某些CMP中,由于加诸于该CMP的热及功率限制(thermaland power constraints),而浪费某些可得的处理频宽。例如,在双核心设计中,两个核心皆能单独操作在三十亿赫(GHz)。然而,由于包装的热预算(thermal budget),或系统的功率预算,两个处理器核心皆被限制在2.7GHz。
发明内容
揭露多核心处理节点之各种实施例。广而言之,思量处理节点,其中在整合于该处理节点内之多个处理器核心中之一者执行的操作系统可监视各个该等处理器核心之使用。响应检测到一个或多个之该等处理器核心操作低于使用临限值(utilization threshold),该操作系统可使一个或多个处理器核心操作在降低效能状态或置于最小功率状态,如所期望者。此外,该操作系统可进一步使正在被使用之处理器核心操作在高于系统最大效能状态的效能状态。
在一个实施例中,整合在单一集成电路芯片上的处理节点包括第一处理器核心及第二处理器核心。该处理节点包括在该第一处理器核心及该第二处理器核心中之一者执行的操作系统。该操作系统可设成监视该第一处理器核心及该第二处理器核心之电流使用。响应检测到该第一处理器核心操作低于使用临限值,该操作系统可设成使该第一处理器核心操作在低于系统最大性能水平的性能水平,并使该第二处理器核心操作在高于该系统最大性能水平的性能水平。
在一个特定实作中,响应检测到该第一处理器核心之使用位准降低为低于最小使用临限值,该操作系统可将该第一处理器核心置于最小功率状态并增加该第二处理器核心之性能水平至核心最大性能水平。要注意,该系统最大性能水平可当该第一处理器核心及该第二处理器核心二者在操作时对应至最大频率及电压位准,且该核心最大性能水平可对应至各个该第一处理器核心及该第二处理器核心当单独操作时能够操作的最大频率及电压位准。
附图说明
图1系包含芯片多处理器之计算器系统的一个实施例的方块图;以及
图2系叙述显示在图1中之处理节点之一个实施例的操作的流程图。
本发明藉由随附图式显示其特定实施例,系容许各种修改及替代形式,并且在此将详细叙述。然而,应了解,该随附图式及其详述并非意于限制本发明至特定揭露之形式,而相反的,系用以涵盖由附加申请专利范围所定义之本发明之精神及范畴内所有的修饰、等效与替代形式。注意,该标题系仅作组织目的用,而非用以限制或阐释该叙述或申请专利范围。再者,注意此申请书全文中“可”(may)字系指许可的意思(亦即,具有潜力能…,或能够…),而非强制的意思(亦即,必须)。用语“包括”(include)及其衍伸系指“包括,但非限制”。用语“连接”(connected)系指“直接或间接地连接”,而用语“耦合”(coupled)系指“直接或间接地耦合”。
具体实施方式
现在参照图1,系显示计算器系统10之一实施例的方块图。在该实施例中,计算器系统10包括处理节点12、存储器14、外围集线器16、外围装置17、传感器35、电压调整器45A与45B及基本输入/输出系统(BIOS)30。该处理节点12包括耦合至节点控制器20的处理器核心18A至18B,该节点控制器20系进一步耦合至存储器控制器22及复数个HyperTransportTM(HT)接口电路24A至24C(在此实施例中系透过HT接口)。HT电路24B系耦合至该外围集线器16,其中该外围集线器16系以菊链(daisy-chain)组态耦合至该外围装置17(在此实施例中系利用HT接口)。外围集线器16亦耦合至BIOS 30。该存储器控制器22系耦合至存储器14。在一实施例中,各个该处理器核心18A至18B可包括个别的快取或多个快取(未图标)。在一实施例中,处理节点12可以是包括如图1所示之该电路的单一集成电路芯片。换言之,处理节点12可以是单芯片多处理器(CMP)。其它实施例可依期望实施处理节点12作为两个或更多个分离的集成电路。可使用任何等级的整合或离散组件。应注意,在其它实施例中,系可在节点12内使用任何数量之处理器核心。进一步应注意,为求简化,同时具有文字及数字的参考指示的组件系能仅参照适当的数字。
一般而言,处理器核心18A与18B可各包括指定执行由给定指令集架构所定义之指令的电路。换言之,该处理器核心电路可设成提取(fetch)、译码、执行及储存由指令集架构所定义之指令的结果。该处理器核心18可包括任何期望之组态,包含超管线(superpipeline)、超纯量(superscalar)或其组合。其它组态可包括纯量、管线、非管线等。各种实施例可不依顺序臆测执行(speculative execution)或依序执行。该处理器核心可包括一个或多个指令或其它功能的微编码(microcoding),连同任何上述架构。各种实施例可实施多种其它设计特征,例如快取、转换后备缓冲区(translation lookaside buffer,TLB)等。
在一实施例中,处理节点12可执行控制两个处理器核心18A至18B的操作系统范例。该操作系统(OS)核心(指定为OS 13A及OS 13B)可分别执行在处理器核心18A或处理器核心18B。在一实施例中,处理器核心18A至18B其中之一可在系统初始化期间被指定为激活程序(bootstrap)核心,而一个处理器核心(可能为同一个)可被指定执行该节点12之该OS核心13。
在一实施例中,各处理器核心18及OS 13可包括使该OS 13控制各处理器核心之该性能水平及该功率位准的特征及功能。例如,经由使用特定寄存器(例如寄存器19A至19B),OS 13可使各处理器核心18操作在一个或多个频率及/或电压位准组合。具体而言,先进组态及电力接口(Advanced Configuration and Power Interface,ACPI)规格系定义系统及含有处理器之系统组件的功率位准及性能水平。由此,处理器核心频率及电压在操作期间可动态地调整以提供有效的功率及效能取舍(trade-off)。例如,某些应用软件可能较不如其它软件需求大。因此,该OS 13可步降(step down)该频率及/或电压以提供增强的电池寿命同时仍能提供有用的效能。相似地,在未使用期间欲降低功率消耗,系定义各种功率状态使处理器核心能有效地设置在最小功率状态(例如睡眠状态)。再者,OS 13可设成单独地动态调整各处理器核心18之该功率及效能状态,端看使用各处理器核心18时之此类参数而定。
该节点控制器20一般可设成接收来自该处理器核心18A至18B、该存储器控制器22及该HT电路24A至24C的通讯,并依据通讯类型、通讯地址等发送这些通讯至该处理器核心18A至18B、该HT电路24A至24C及该存储器控制器22。在一实施例中,该节点控制器20包括系统管理单元21,其可设成接收系统管理信息,例如处理器节点温度或其它系统环境信息。系统管理单元21可包括电路以提供ACPI顺应功能(compliant functionality)。如下将详细叙述,在节点控制器20内之该系统管理单元21可设成告知该OS核心13特定系统管理事件。在一实施例中,系统管理信息可以是使处理器核心18A至18B进入特定状态的要求。例如,该状态可以是功率管理状态或效能管理状态(例如以上所述)。其它实施例则可定义如下所述之其它系统管理信息。
在该说明实施例中,传感器35可以是任何类型用以监视环境状况的装置。例如,在一实施例中,传感器35可以是设成决定处理节点12内之参考二极管之接面温度的温度感应装置。传感器35系可进一步设成提供系统管理单元21温度的指示。
在该说明实施例中,电压调整器45A与45B可设成可程序化地调整并控制分别提供处理器核心18A与18B的操作电压。例如,在一实施例中,OS核心13可送出改变两个核心或其中之一至节点控制器20之操作电压的要求。节点控制器20可送出对应信号至可影响电压改变的电压调整器45A与45B。在此实施例中,为允许处理器核心18A与18B的单独电压控制,处理节点12可包括各处理器核心18A与18B分离的电压供应针脚(例如VDD及Gnd)。
一般而言,该处理器核心18A至18B可使用连至该节点控制器20的接口与该计算器系统10之其它组件(例如外围集线器16、外围装置17、其它处理器核心、该存储器控制器22等)通讯。该接口能以任何期望方式设计。该接口系可定义快取连贯通讯(coherent communication)。在一实施例中,在该节点控制器20与该处理器核心18A至18B之间的接口通讯系可以是相似于那些使用在该HT接口的封包形式。在其它实施例中,系可使用任何期望之通讯(例如总线接口的交易、不同形式的封包等)。在其它实施例中,该处理器核心18A至18B可共享连至该节点控制器20的接口(例如共享总线接口)。
该存储器14可包括任何适合的存储器装置。例如,存储器14可包括一个或多个RAMBUS DRAM(RDRAM)、同步DRAM(SDRAM)、双倍资料速率(DDR)SDRAM、静态RAM等。该计算器系统10之地址空间在存储器14与其它处理节点之任何相似存储器(未图标)之间系可被分割。在此情况中,各节点12可包括存储器映像(memory map)(例如在该节点控制器20中)以决定哪个地址被映像至哪个存储器14,以及存储器所要求之特定地址应被发送至哪个节点12。该存储器控制器22可包括用以与该存储器14形成接口的控制电路。另外,该存储器控制器22可包括要求队列存储器要求的要求等。
该HT电路24A至24C可包括各种用以接收来自HT链接的封包及在HT链接上传送封包的缓冲及控制电路。该HT接口包括用以传送封包的单向链接。各HT电路24A至24C可耦合至两个此类链接(一个作为传送而一个作为接收)。给定之HT接口可以快取连贯方式(例如在两个节点12之间)或非连贯方式(例如至/从外围集线器16/外围装置17)操作。在该说明实施例中,该HT电路24C可透过连贯HT链接耦合至在另一节点上之相似HT接口(未图标)藉以在节点间通讯。该HT电路24A并未使用,而该HT电路24B系透过非连贯链接耦合至该外围集线器16/外围装置17。
该外围集线器16及外围装置17可以是任何类型的外围装置。例如,该外围集线器16/外围装置17可包括与另一计算器系统通讯的装置,而该装置系可耦合至该另一计算器系统(例如网络接口卡、整合在计算器系统之主电路板上的电路实施网络接口功能、或调制解调器等)。再者,该外围集线器16/外围装置17可包括视频加速器、声频卡(audiocard)、硬盘或软盘或磁盘控制器、SCSI(小型计算器系统接口)转接器及电话语音卡(telephony card)、声卡及各种资料撷取卡,例如通用接口总线(GPIB)或场总线接口卡(field bus interface cards)。应注意,名词“外围装置”系意指包含输入/输出(I/O)装置。
当本实施例使用该HT接口在节点间及节点与外围装置间通讯时,应注意到其它实施例系可使用任何期望的接口或多个接口来通讯。例如,可使用其它封包基础接口、总线接口、各种标准外围接口等(例如外围组件连结(PCI)、快速PCI(PCI express)等)。
如上所述,OS核心13可执行在任一处理器核心18A至处理器核心18B上。OS核心13可监视并控制系统功能,决定并分派哪个处理器核心18执行特定执行绪(execution thread)等。具体而言,OS核心13可监视各处理器核心18A至18B之使用。此外,依据各处理器核心18A至18B之使用及其它系统参数,OS核心13可单独地控制各处理器核心18A至18B之该功率状态及该效能状态。
在图2中,系显示说明图1之处理节点12之一实施例的操作流程图。在系统初始化期间合并参照图1及图2,可利用初始性能水平及功率位准以执行处理器核心18A至18B(方块205)。例如,该初始设定可以是写入寄存器19A至19B的预设设定。在一实施例中,寄存器19A至19B可以是模型特定寄存器(model specific register,MSR),然而系可使用任何寄存器。该预设设定可透过保险丝来固定编码(hard coded)或在激活期间或开机自动测试(power-on self-test,POST)期间透过该BIOS而被写入。在任一情况中,该OS 13可利用储存于寄存器19A与19B的值来决定各处理器核心18A至18B之该操作频率、电压及功率状态。根据系统分析,该初始或预设设定可以是预定值。例如,可为系统最大性能水平设定该频率及电压设定。该系统最大性能水平可对应至两个处理器核心18A至18B可一起操作而不超过处理节点12之该热预算时的频率及电压位准。该系统最大性能水平系典型地不同于核心最大性能水平,该核心最大性能水平系对应至给定处理器核心18能操作之该频率及电压位准。该核心最大值可在制造期间经由测试及特性化(characterization)而决定。
在一实施例之操作处理节点12时,OS 13可监视各处理器核心18使用任何可用之公用程序(utility)时之电流使用。此外,OS 13可监视系统管理参数,例如是否以接收到任何外部或内部系统管理中断或要求信息(方块210)。
假使OS 13决定处理器核心18A或处理器核心18B之使用已降低至低于预定临限值(方块215)时,OS则决定是否该核心已降至低于最小临限值(方块220),OS 13可切断具有低使用之该处理器核心的电源或使其操作在最小功率状态(方块230)。此外,OS 13可使正在使用之该处理器核心18操作在核心最大位准(方块235)。
经由范例说明,假定不管任何系统位准或热流规定,各个处理器核心18A至18B皆能操作在3GHz。因此,各处理器核心18之该核心最大性能水平系3GHz。然而,当两个处理器核心18皆在相同包装时,假使两者同时一起操作在3Ghz则会超过该热预算。因此,可设定该系统最大性能水平俾使该处理器核心18在一起操作时不会超过2.6GHz。
现在,应用程序可仅执行在处理器核心18A,而处理器核心18B闲置,例如执行单绪应用(single threaded application)的情况。由此,OS13可切断处理器核心18B的电源并使处理器核心18A操作在其核心最大性能水平。以此方法,该热预算便不会超过,而该应用程序则能执行在最大性能水平。
此外,该使用可能会有最大值与最小值间描述不清的情况。因此,OS 13可设成检查对于各种临限值之该电流使用。因此,OS 13可以改变增量的方式动态地调低一个处理器核心性能水平,同时调高另一个处理器核心性能水平,而不会超过该热预算。因此,回头参照方块220,假使OS 13决定该处理器核心并未低于该最小使用临限值,但低于某些其它临限值时,OS 13可以增量的方式降低具有较低使用之该处理器核心之该性能水平并增加具有较高使用之该处理器核心之该性能水平(方块225)。然后操作便如方块210所述进行,其中OS 13监视各处理器核心18之电流使用。
回头参照方块215,假使OS 13决定处理器核心18两个都未低于使用临限值,OS 13可决定是否该系统温度低于最小临限值(方块240)。例如,该处理器核心18典型的晶粒操作温度可以是90℃。此温度可由传感器35所监视。在一实施例中,传感器35可检测处理器核心18A及/或处理器核心18B内参考二极管的温度。传感器35可提供系统管理单元21的温度指示。在一实施例中,例如,最小临限值可以是75℃,而最大临限值可以是88℃。因此,假使该温度低于该最小临限值,OS 13可以增量方式增加一个或二者(one or both)处理器核心性能水平(方块245)直到该温度在该最小临限值(方块240)及最大临限值(方块250)内。方块240及250之操作可反复执行数次以获得所期望的性能水平及温度。然后操作便如方块210所述进行,其中OS 13监视各处理器核心18之电流使用。
参照方块250,假使该温度高于该最大临限值(方块250)。假使该温度高于该最小临限值,OS 13可以增量方式降低一个或二者处理器核心性能水平(方块245),直到该温度在该最小临限值及最大临限值内。然而,在此上限情况中,该OS 13可增加该性能水平步长(step size)来尽快地降低该温度。然后操作便如方块210所述进行,其中OS 13监视各处理器核心18之电流使用。
应注意,该操作电压系可以如同频率以相同方式增量地增加及降低。在一实施例中,该电压可随该频率调整,而在另一实施例中,该电压则独立于该频率作调整。例如,如上所述,OS 13可藉由送出要求至节点控制器20来增加或降低该操作电压。节点控制器20需要时可提供信号给电压调整器45A及/或电压调整器45B来增加或降低该电压。
虽已详尽叙述以上之实施例,然而一旦完整了解以上揭露后,对于熟习该技术领域者而言系能明白各种改变及修饰之可能。下列之申请专利范围系意于涵盖所有此类改变及修饰。
工业实用性
本发明通常应用于多核心处理器。
Claims (8)
1.一种处理节点装置,集成在单个集成电路芯片上,所述的处理节点装置包括:
第一处理器核心(18A);
第二处理器核心(18B);
操作系统(13A,13B),在所述第一处理器核心及所述第二处理器核心的任意一个上面执行,所述操作系统设置成依据所述第一处理器核心和所述第二处理器核心的任意一个电流使用水平独立地控制所述第一处理器核心和所述第二处理器核心的每一个的核心性能水平;
其中响应于检测所述第一处理器核心的电流使用水平低于使用临限值,所述操作系统设置成将所述第一处理器核心的核心性能水平降低第一量和将所述第二处理器核心的核心性能水平增加第二量,从而使所述第二处理器核心操作高于系统最大性能水平,其中所述系统最大性能水平对应于所述第一处理器核心及所述第二处理器核心可一起操作而不超过所述处理节点装置的热预算时的最大频率及电压位准。
2.如权利要求1所述的处理节点装置,其中响应于检测到所述第二处理器核心的电流使用水平低于使用临限值,而非所述第一处理器核心的电流使用水平低于使用临限值,所述操作系统设置成将所述第二处理器核心的核心性能水平降低第一量和将所述第一处理器核心的核心性能水平增加第二量,从而使所述第一处理器核心操作高于系统最大性能水平。
3.如权利要求1所述的处理节点装置,其中响应于检测所述第一处理器核心的电流使用水平降低到最小使用临限值以下,所述操作系统设置成将所述第一处理器核心置于最小功率状态,并且将所述第二处理器核心的性能水平增加至核心最大性能水平。
4.如权利要求3所述的处理节点装置,其中,所述核心最大性能水平相当于能够使所述第一处理器核心和所述第二处理器核心的每一个独立运行的最大的频率和电压水平。
5.一种用于增加于多核心处理器上的一个或多个核心的工作量效能的方法,包括:
处理节点的第一处理器核心(18A)执行指令;
处理节点的第二处理器核心(18B)执行指令;
操作系统(13A,13B)在所述第一处理器核心及所述第二处理器核心的任意一个上面执行,以及依据所述第一处理器核心和所述第二处理器核心的任意一个的电流使用水平独立地控制所述第一处理器核心和所述第二处理器核心的每一个的核心性能水平;
其中响应于检测所述第一处理器核心的电流使用水平低于使用临限值,所述操作系统将所述第一处理器核心的核心性能水平降低第一量和将所述第二处理器核心的核心性能水平增加第二量而高于系统最大性能水平,其中所述系统最大性能水平对应于所述第一处理器核心及所述第二处理器核心可一起操作而不超过所述处理节点的热预算时的最大频率及电压位准。
6.如权利要求5所述的方法,其中响应于检测到所述第二处理器核心的电流使用水平低于使用临限值,而非所述第一处理器核心的电流使用水平低于使用临限值,所述操作系统设置成将所述第二处理器核心的核心性能水平降低第一量和将所述第一处理器核心的核心性能水平增加第二量,从而使所述第一处理器核心操作高于系统最大性能水平。
7.如权利要求5所述的方法,其中响应于检测所述第一处理器核心的电流使用水平降低到最小使用临限值以下,所述操作系统将所述第一处理器核心置于最小功率状态,并且将所述第二处理器核心的性能水平增加至核心最大性能水平。
8.如权利要求7所述的方法,其中,所述核心最大性能水平相当于能够使所述第一处理器核心和所述第二处理器核心的每一个独立运行的最大的频率和电压水平。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107066069A (zh) * | 2013-02-04 | 2017-08-18 | 英特尔公司 | 多电压识别(vid)功率架构、数字可合成低压差调节器及用于改善功率门可靠性的装置 |
Families Citing this family (120)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7434073B2 (en) | 2004-11-29 | 2008-10-07 | Intel Corporation | Frequency and voltage scaling architecture |
US20070094436A1 (en) * | 2005-10-20 | 2007-04-26 | Keown William F Jr | System and method for thermal management in PCI express system |
US7263457B2 (en) * | 2006-01-03 | 2007-08-28 | Advanced Micro Devices, Inc. | System and method for operating components of an integrated circuit at independent frequencies and/or voltages |
US7774590B2 (en) * | 2006-03-23 | 2010-08-10 | Intel Corporation | Resiliently retaining state information of a many-core processor |
US7636864B2 (en) * | 2006-05-03 | 2009-12-22 | Intel Corporation | Mechanism for adaptively adjusting a direct current loadline in a multi-core processor |
US7650518B2 (en) * | 2006-06-28 | 2010-01-19 | Intel Corporation | Method, apparatus, and system for increasing single core performance in a multi-core microprocessor |
US8051276B2 (en) * | 2006-07-07 | 2011-11-01 | International Business Machines Corporation | Operating system thread scheduling for optimal heat dissipation |
US7949887B2 (en) * | 2006-11-01 | 2011-05-24 | Intel Corporation | Independent power control of processing cores |
US8117478B2 (en) | 2006-12-29 | 2012-02-14 | Intel Corporation | Optimizing power usage by processor cores based on architectural events |
WO2008108133A1 (ja) * | 2007-03-02 | 2008-09-12 | Nec Corporation | タスク群割当方法、タスク群割当装置、タスク群割当プログラム、プロセッサ及びコンピュータ |
EP2130106B1 (en) * | 2007-03-28 | 2018-11-14 | Nytell Software LLC | Electronic device and method determining a workload of an electronic device |
US7900069B2 (en) * | 2007-03-29 | 2011-03-01 | Intel Corporation | Dynamic power reduction |
US8490103B1 (en) * | 2007-04-30 | 2013-07-16 | Hewlett-Packard Development Company, L.P. | Allocating computer processes to processor cores as a function of process utilizations |
US7908493B2 (en) * | 2007-06-06 | 2011-03-15 | International Business Machines Corporation | Unified management of power, performance, and thermals in computer systems |
US8166326B2 (en) * | 2007-11-08 | 2012-04-24 | International Business Machines Corporation | Managing power consumption in a computer |
US8032772B2 (en) | 2007-11-15 | 2011-10-04 | Intel Corporation | Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor |
US20090132842A1 (en) * | 2007-11-15 | 2009-05-21 | International Business Machines Corporation | Managing Computer Power Consumption In A Computer Equipment Rack |
US8041521B2 (en) * | 2007-11-28 | 2011-10-18 | International Business Machines Corporation | Estimating power consumption of computing components configured in a computing system |
US8024590B2 (en) * | 2007-12-10 | 2011-09-20 | Intel Corporation | Predicting future power level states for processor cores |
US20090182657A1 (en) * | 2008-01-15 | 2009-07-16 | Omx Technology Ab | Distributed ranking and matching of messages |
US20090235108A1 (en) * | 2008-03-11 | 2009-09-17 | Gold Spencer M | Automatic processor overclocking |
US20090288092A1 (en) * | 2008-05-15 | 2009-11-19 | Hiroaki Yamaoka | Systems and Methods for Improving the Reliability of a Multi-Core Processor |
US8103884B2 (en) * | 2008-06-25 | 2012-01-24 | International Business Machines Corporation | Managing power consumption of a computer |
US8200999B2 (en) * | 2008-08-11 | 2012-06-12 | International Business Machines Corporation | Selective power reduction of memory hardware |
US20100057404A1 (en) * | 2008-08-29 | 2010-03-04 | International Business Machines Corporation | Optimal Performance and Power Management With Two Dependent Actuators |
US8041976B2 (en) * | 2008-10-01 | 2011-10-18 | International Business Machines Corporation | Power management for clusters of computers |
US8707060B2 (en) * | 2008-10-31 | 2014-04-22 | Intel Corporation | Deterministic management of dynamic thermal response of processors |
US8514215B2 (en) * | 2008-11-12 | 2013-08-20 | International Business Machines Corporation | Dynamically managing power consumption of a computer with graphics adapter configurations |
US8055477B2 (en) * | 2008-11-20 | 2011-11-08 | International Business Machines Corporation | Identifying deterministic performance boost capability of a computer system |
US8689017B2 (en) * | 2009-03-12 | 2014-04-01 | Cisco Technology, Inc. | Server power manager and method for dynamically managing server power consumption |
EP2435914B1 (en) | 2009-05-26 | 2019-12-11 | Telefonaktiebolaget LM Ericsson (publ) | Method and scheduler in an operating system |
JP5223804B2 (ja) * | 2009-07-22 | 2013-06-26 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
EP2457139A1 (en) * | 2009-07-24 | 2012-05-30 | Advanced Micro Devices, Inc. | Altering performance of computational units heterogeneously according to performance sensitivity |
US20110022356A1 (en) * | 2009-07-24 | 2011-01-27 | Sebastien Nussbaum | Determining performance sensitivities of computational units |
US8452991B2 (en) * | 2009-08-20 | 2013-05-28 | International Business Machines Corporation | Partition level power management using fully asynchronous cores with software that has limited asynchronous support |
KR101620103B1 (ko) * | 2009-10-21 | 2016-05-13 | 삼성전자주식회사 | 멀티 코어 시스템에서 중앙 처리 장치의 전력 제어 장치 및 방법 |
US9098274B2 (en) * | 2009-12-03 | 2015-08-04 | Intel Corporation | Methods and apparatuses to improve turbo performance for events handling |
US9176572B2 (en) | 2009-12-16 | 2015-11-03 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US9104411B2 (en) | 2009-12-16 | 2015-08-11 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US8650426B2 (en) * | 2009-12-16 | 2014-02-11 | Qualcomm Incorporated | System and method for controlling central processing unit power in a virtualized system |
US8775830B2 (en) | 2009-12-16 | 2014-07-08 | Qualcomm Incorporated | System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature |
US9563250B2 (en) * | 2009-12-16 | 2017-02-07 | Qualcomm Incorporated | System and method for controlling central processing unit power based on inferred workload parallelism |
US8689037B2 (en) * | 2009-12-16 | 2014-04-01 | Qualcomm Incorporated | System and method for asynchronously and independently controlling core clocks in a multicore central processing unit |
US20110145559A1 (en) * | 2009-12-16 | 2011-06-16 | Thomson Steven S | System and method for controlling central processing unit power with guaranteed steady state deadlines |
US8909962B2 (en) * | 2009-12-16 | 2014-12-09 | Qualcomm Incorporated | System and method for controlling central processing unit power with guaranteed transient deadlines |
US9128705B2 (en) * | 2009-12-16 | 2015-09-08 | Qualcomm Incorporated | System and method for controlling central processing unit power with reduced frequency oscillations |
US8352759B2 (en) * | 2010-01-11 | 2013-01-08 | Qualcomm Incorporated | System and method of monitoring a central processing unit in real time |
US8549339B2 (en) * | 2010-02-26 | 2013-10-01 | Empire Technology Development Llc | Processor core communication in multi-core processor |
US8615672B2 (en) * | 2010-06-30 | 2013-12-24 | Via Technologies, Inc. | Multicore processor power credit management to allow all processing cores to operate at elevated frequency |
US9600059B2 (en) * | 2010-09-20 | 2017-03-21 | Apple Inc. | Facilitating power management in a multi-core processor |
US8943334B2 (en) * | 2010-09-23 | 2015-01-27 | Intel Corporation | Providing per core voltage and frequency control |
US8612781B2 (en) * | 2010-12-14 | 2013-12-17 | Advanced Micro Devices, Inc. | Method and apparatus for application of power density multipliers optimally in a multicore system |
US9063730B2 (en) | 2010-12-20 | 2015-06-23 | Intel Corporation | Performing variation-aware profiling and dynamic core allocation for a many-core processor |
US8984305B2 (en) | 2010-12-21 | 2015-03-17 | Intel Corporation | Method and apparatus to configure thermal design power in a microprocessor |
US9201707B2 (en) * | 2011-02-02 | 2015-12-01 | Nec Corporation | Distributed system, device, method, and program |
US8949637B2 (en) * | 2011-03-24 | 2015-02-03 | Intel Corporation | Obtaining power profile information with low overhead |
US8924752B1 (en) | 2011-04-20 | 2014-12-30 | Apple Inc. | Power management for a graphics processing unit or other circuit |
US8793515B2 (en) | 2011-06-27 | 2014-07-29 | Intel Corporation | Increasing power efficiency of turbo mode operation in a processor |
US20130000871A1 (en) * | 2011-06-30 | 2013-01-03 | Ian Olson | Systems and Methods for Extending Operating Temperatures of Electronic Components |
US9098561B2 (en) | 2011-08-30 | 2015-08-04 | Intel Corporation | Determining an effective stress level on a processor |
US8769316B2 (en) | 2011-09-06 | 2014-07-01 | Intel Corporation | Dynamically allocating a power budget over multiple domains of a processor |
US8688883B2 (en) * | 2011-09-08 | 2014-04-01 | Intel Corporation | Increasing turbo mode residency of a processor |
CN102999150B (zh) * | 2011-09-14 | 2016-02-03 | 宏碁股份有限公司 | 电子系统与效能控制方法 |
US8862917B2 (en) * | 2011-09-19 | 2014-10-14 | Qualcomm Incorporated | Dynamic sleep for multicore computing devices |
US9074947B2 (en) | 2011-09-28 | 2015-07-07 | Intel Corporation | Estimating temperature of a processor core in a low power state without thermal sensor information |
KR20130040485A (ko) * | 2011-10-14 | 2013-04-24 | 삼성전자주식회사 | 휴대 단말기에서 중앙처리장치를 제어하는 장치 및 방법 |
US9026815B2 (en) * | 2011-10-27 | 2015-05-05 | Intel Corporation | Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor |
US8924758B2 (en) * | 2011-12-13 | 2014-12-30 | Advanced Micro Devices, Inc. | Method for SOC performance and power optimization |
US8856566B1 (en) | 2011-12-15 | 2014-10-07 | Apple Inc. | Power management scheme that accumulates additional off time for device when no work is available and permits additional power consumption by device when awakened |
WO2013095436A1 (en) * | 2011-12-21 | 2013-06-27 | Intel Corporation | Method and apparatus for setting an i/o bandwidth-based processor frequency floor |
US9569278B2 (en) * | 2011-12-22 | 2017-02-14 | Intel Corporation | Asymmetric performance multicore architecture with same instruction set architecture |
WO2013137862A1 (en) * | 2012-03-13 | 2013-09-19 | Intel Corporation | Dynamically controlling interconnect frequency in a processor |
US9436245B2 (en) | 2012-03-13 | 2016-09-06 | Intel Corporation | Dynamically computing an electrical design point (EDP) for a multicore processor |
CN104169832B (zh) * | 2012-03-13 | 2017-04-19 | 英特尔公司 | 提供处理器的能源高效的超频操作 |
WO2013147906A1 (en) * | 2012-03-31 | 2013-10-03 | Intel Corporation | Controlling power consumption in multi-core environments |
US9390461B1 (en) | 2012-05-08 | 2016-07-12 | Apple Inc. | Graphics hardware mode controls |
WO2013181168A1 (en) | 2012-05-30 | 2013-12-05 | Schweitzer Engineering Laboratories, Inc. | Thermal management of a communication transceiver in an electrical communication device |
US9250665B2 (en) * | 2012-06-07 | 2016-02-02 | Apple Inc. | GPU with dynamic performance adjustment |
US9229524B2 (en) | 2012-06-27 | 2016-01-05 | Intel Corporation | Performing local power gating in a processor |
US8862824B2 (en) * | 2012-09-26 | 2014-10-14 | Intel Corporation | Techniques for managing power and performance of multi-socket processors |
CN103810141A (zh) * | 2012-11-09 | 2014-05-21 | 辉达公司 | 处理器和包括其的电路板 |
US9218044B2 (en) * | 2012-11-27 | 2015-12-22 | International Business Machines Corporation | Computing system frequency target monitor |
US9323300B2 (en) * | 2012-11-27 | 2016-04-26 | International Business Machines Corporation | Computing system voltage control |
KR102005765B1 (ko) | 2012-12-17 | 2019-07-31 | 삼성전자주식회사 | 시스템-온 칩과, 이의 동작 방법 |
US9052885B2 (en) * | 2012-12-21 | 2015-06-09 | Advanced Micro Devices, Inc. | Using temperature margin to balance performance with power allocation |
US9672046B2 (en) * | 2012-12-28 | 2017-06-06 | Intel Corporation | Apparatus and method for intelligently powering heterogeneous processor components |
US9639372B2 (en) | 2012-12-28 | 2017-05-02 | Intel Corporation | Apparatus and method for heterogeneous processors mapping to virtual cores |
US9727345B2 (en) | 2013-03-15 | 2017-08-08 | Intel Corporation | Method for booting a heterogeneous system and presenting a symmetric core view |
US9430346B2 (en) | 2013-03-26 | 2016-08-30 | Texas Instruments Incorporated | Processor power measurement |
US9317389B2 (en) | 2013-06-28 | 2016-04-19 | Intel Corporation | Apparatus and method for controlling the reliability stress rate on a processor |
JP6142709B2 (ja) * | 2013-07-23 | 2017-06-07 | 富士通株式会社 | 計測方法、計測プログラム、携帯情報端末、及びその制御方法 |
CN104424156A (zh) * | 2013-09-09 | 2015-03-18 | 中兴通讯股份有限公司 | 处理器的核处理方法、装置及终端 |
WO2015039320A1 (en) * | 2013-09-19 | 2015-03-26 | Intel Corporation | Techniques for distributed processing task portion assignment |
US9395788B2 (en) | 2014-03-28 | 2016-07-19 | Intel Corporation | Power state transition analysis |
JP5986138B2 (ja) * | 2014-05-09 | 2016-09-06 | レノボ・シンガポール・プライベート・リミテッド | 複数のプロセッサに電力を供給する電源装置の出力を制御する方法、電源システムおよび情報処理装置 |
US10025361B2 (en) * | 2014-06-05 | 2018-07-17 | Advanced Micro Devices, Inc. | Power management across heterogeneous processing units |
US9600058B2 (en) * | 2014-06-24 | 2017-03-21 | Intel Corporation | Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power |
US9904339B2 (en) | 2014-09-10 | 2018-02-27 | Intel Corporation | Providing lifetime statistical information for a processor |
US9906497B2 (en) | 2014-10-06 | 2018-02-27 | Cryptzone North America, Inc. | Multi-tunneling virtual network adapter |
US9898071B2 (en) * | 2014-11-20 | 2018-02-20 | Apple Inc. | Processor including multiple dissimilar processor cores |
US9704598B2 (en) | 2014-12-27 | 2017-07-11 | Intel Corporation | Use of in-field programmable fuses in the PCH dye |
US9779058B2 (en) * | 2015-07-13 | 2017-10-03 | Google Inc. | Modulating processsor core operations |
US20170147053A1 (en) * | 2015-11-23 | 2017-05-25 | Mediatek Inc. | Application driven dynamic voltage and frequency scaling method and associated machine readable medium |
US10013392B2 (en) | 2016-01-26 | 2018-07-03 | Intel Corporation | Providing access from outside a multicore processor SoC to individually configure voltages |
US10412048B2 (en) | 2016-02-08 | 2019-09-10 | Cryptzone North America, Inc. | Protecting network devices by a firewall |
US10296067B2 (en) * | 2016-04-08 | 2019-05-21 | Qualcomm Incorporated | Enhanced dynamic clock and voltage scaling (DCVS) scheme |
US9560015B1 (en) | 2016-04-12 | 2017-01-31 | Cryptzone North America, Inc. | Systems and methods for protecting network devices by a firewall |
WO2018032334A1 (zh) * | 2016-08-16 | 2018-02-22 | 陈银芳 | 手机多核多线程调度方法及系统 |
US10659168B2 (en) | 2016-08-23 | 2020-05-19 | Schweitzer Engineering Laboratories, Inc. | Low-power fiber optic transceiver |
US10528118B2 (en) * | 2017-04-21 | 2020-01-07 | Intel Corporation | Dynamically power on/off register files during execution |
CN111435267A (zh) * | 2019-01-15 | 2020-07-21 | 海信集团有限公司 | 功耗自动调整的方法、装置、设备及计算机可读存储介质 |
US11086081B2 (en) | 2019-03-21 | 2021-08-10 | Schweitzer Engineering Laboratories, Inc. | Conductive cooling for small form-factor pluggable (SFP) fiber optic transceivers |
US11073888B2 (en) * | 2019-05-31 | 2021-07-27 | Advanced Micro Devices, Inc. | Platform power manager for rack level power and thermal constraints |
US11487339B2 (en) * | 2019-08-29 | 2022-11-01 | Micron Technology, Inc. | Operating mode register |
CN114816033A (zh) * | 2019-10-17 | 2022-07-29 | 华为技术有限公司 | 处理器的调频方法及装置、计算设备 |
US11392418B2 (en) | 2020-02-21 | 2022-07-19 | International Business Machines Corporation | Adaptive pacing setting for workload execution |
KR20230015895A (ko) * | 2020-05-29 | 2023-01-31 | 인텔 코포레이션 | 하드웨어를 워크로드 최적화하기 위한 시스템들, 장치들, 및 방법들 |
TWI777320B (zh) * | 2020-12-04 | 2022-09-11 | 神雲科技股份有限公司 | 功耗校調方法與伺服器 |
US20230205306A1 (en) * | 2021-12-24 | 2023-06-29 | Advanced Micro Devices, Inc | Default Boost Mode State for Devices |
CN115622592B (zh) * | 2022-12-20 | 2023-03-10 | 翱捷科技(深圳)有限公司 | 音频数据获取方法、系统及存储介质 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1268687A (zh) * | 1999-03-24 | 2000-10-04 | 新巨企业股份有限公司 | 具有多处理器控制装置的电源供应器 |
CN1605063A (zh) * | 2001-12-13 | 2005-04-06 | 英特尔公司 | 在多处理器间分配指令执行以降低功耗的计算系统和方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04215168A (ja) * | 1990-12-13 | 1992-08-05 | Nec Corp | コンピュータシステム |
DE69231762T2 (de) | 1991-07-08 | 2001-07-26 | Seiko Epson Corp | Risc-prozessor mit dehnbarer architektur |
US6823516B1 (en) * | 1999-08-10 | 2004-11-23 | Intel Corporation | System and method for dynamically adjusting to CPU performance changes |
JP2001109729A (ja) * | 1999-10-12 | 2001-04-20 | Nec Corp | マルチプロセッサシステムにおける消費電力制御装置および方法 |
JP2002189540A (ja) * | 2000-12-20 | 2002-07-05 | Pfu Ltd | 装置電源の節電制御装置および節電制御方法並びに記録媒体 |
US6704687B2 (en) * | 2001-01-31 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Historical results based method for automatically improving computer system performance |
US6895520B1 (en) * | 2001-03-02 | 2005-05-17 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
US7017060B2 (en) * | 2001-03-19 | 2006-03-21 | Intel Corporation | Power management system that changes processor level if processor utilization crosses threshold over a period that is different for switching up or down |
US7111178B2 (en) | 2001-09-28 | 2006-09-19 | Intel Corporation | Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system |
US7100056B2 (en) * | 2002-08-12 | 2006-08-29 | Hewlett-Packard Development Company, L.P. | System and method for managing processor voltage in a multi-processor computer system for optimized performance |
US6908227B2 (en) | 2002-08-23 | 2005-06-21 | Intel Corporation | Apparatus for thermal management of multiple core microprocessors |
US7272732B2 (en) * | 2003-06-30 | 2007-09-18 | Hewlett-Packard Development Company, L.P. | Controlling power consumption of at least one computer system |
JP4549652B2 (ja) * | 2003-10-27 | 2010-09-22 | パナソニック株式会社 | プロセッサシステム |
EP1555595A3 (en) * | 2004-01-13 | 2011-11-23 | LG Electronics, Inc. | Apparatus for controlling power of processor having a plurality of cores and control method of the same |
US8190863B2 (en) * | 2004-07-02 | 2012-05-29 | Intel Corporation | Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction |
US7788670B2 (en) * | 2004-10-26 | 2010-08-31 | Intel Corporation | Performance-based workload scheduling in multi-core architectures |
US20060091061A1 (en) | 2004-11-02 | 2006-05-04 | Baldwin Filters, Inc. | Filter assembly with sealing system |
US7536567B2 (en) * | 2004-12-10 | 2009-05-19 | Hewlett-Packard Development Company, L.P. | BIOS-based systems and methods of processor power management |
KR101108397B1 (ko) | 2005-06-10 | 2012-01-30 | 엘지전자 주식회사 | 멀티-코어 프로세서의 전원 제어 장치 및 방법 |
-
2005
- 2005-08-02 US US11/195,305 patent/US7490254B2/en active Active
-
2006
- 2006-07-20 GB GB0802801A patent/GB2442919B/en active Active
- 2006-07-20 JP JP2008524998A patent/JP4937260B2/ja active Active
- 2006-07-20 CN CN2006800280754A patent/CN101233475B/zh active Active
- 2006-07-20 KR KR1020087005317A patent/KR101310044B1/ko active IP Right Grant
- 2006-07-20 DE DE112006002056T patent/DE112006002056T5/de not_active Ceased
- 2006-07-20 WO PCT/US2006/028199 patent/WO2007019003A2/en active Application Filing
- 2006-08-01 TW TW095128098A patent/TWI412993B/zh active
-
2009
- 2009-01-22 US US12/357,635 patent/US20090187777A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1268687A (zh) * | 1999-03-24 | 2000-10-04 | 新巨企业股份有限公司 | 具有多处理器控制装置的电源供应器 |
CN1605063A (zh) * | 2001-12-13 | 2005-04-06 | 英特尔公司 | 在多处理器间分配指令执行以降低功耗的计算系统和方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107066069A (zh) * | 2013-02-04 | 2017-08-18 | 英特尔公司 | 多电压识别(vid)功率架构、数字可合成低压差调节器及用于改善功率门可靠性的装置 |
CN107066069B (zh) * | 2013-02-04 | 2020-09-15 | 英特尔公司 | 多电压识别(vid)功率架构、数字可合成低压差调节器及用于改善功率门可靠性的装置 |
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US7490254B2 (en) | 2009-02-10 |
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KR20080038389A (ko) | 2008-05-06 |
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