CN101180739B - 具有边缘末端的半导体器件 - Google Patents

具有边缘末端的半导体器件 Download PDF

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CN101180739B
CN101180739B CN2006800180192A CN200680018019A CN101180739B CN 101180739 B CN101180739 B CN 101180739B CN 2006800180192 A CN2006800180192 A CN 2006800180192A CN 200680018019 A CN200680018019 A CN 200680018019A CN 101180739 B CN101180739 B CN 101180739B
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罗布·范达伦
马尔腾·J·斯韦恩伯格
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III Holdings 6 LLC
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Abstract

半导体器件具有有源区(30)和包括多个浮置场区域(46)的边缘末端区域(32)。场板(54)在边缘末端区域(32)中从接触孔(56)在浮置场区域(46)上向内向有源区(30)延伸。可以设置柱子(40)。

Description

具有边缘末端的半导体器件
技术领域
本发明涉及一种用于半导体器件的边缘末端(edge termination)结构。
背景技术
边缘末端是高电压器件中的一种特别要求，以避免器件边缘的电压击穿。当峰值场达到所谓的临界场约3×105Vcm-1时发生击穿。
在理想的(虚构的)无限宽的垂直结构中，击穿将在称为1D击穿电压的某个击穿电压处发生，因为其省略了边缘处的2D和/或3D效果。在实际器件中，击穿电压将比1D击穿电压低。
作为示例，考虑图1的高压pn二极管，在n-型衬底4中具有p+型区域2。当施加电压时，电力线将聚集于角落区域8。因为场在区域8中较大，当电压上升时，击穿将首先发生在该区域中。
表面电荷可以改变场分布，提高场聚集，导致在较低的不可复制电压处的击穿。
图2示出了用于减小该问题的一种方法，使用在使用时将采取中间电势的结周围的浮置(floating)p-型区域10。耗尽层和电力线不再遵循p型区域2和n型衬底4之间的结周围的曲率，减小了角落区域8中的场聚集和电压击穿。
另一种方法使用如图3所示的场板(field plate)12和绝缘层14，其中场板12在与p+型区域2相邻的n-型衬底的区域上延伸，通过绝缘层14与其绝缘。
1995年在美国波士顿由PWS出版社出版的Baliga的教科书“PowerSemiconductor Devices”描述了(该教科书的图3.27)场环和场板的组合，场板从场环向外延伸以防止器件顶面上的电荷改变表面电势。
在转让给Philips的US 6,724,021中描述了一种更复杂的方案，使用功率金属氧化物半导体场效应晶体管(MOSFET)周围的表面上的电阻层。与边缘相距不同距离的多个电阻路径将电阻层与下面的衬底连接，产生电势分配器，所述电势分配器使场平滑并且因此减小了对于场轮廓变化的敏感性。
在转让给Siemens的US 6,376,890中提供了一种不同的边缘末端，所述末端包括半导体表面处的多个浮置区域、表面上的绝缘层以及在与浮置区域相连的绝缘层中绝缘的场板。
边缘末端在减小的表面场(RESURF)器件中特别重要。在这种器件中，与具有传统漂移区的器件相比，当器件处于截止状态时将漂移区耗尽，以提高器件承受的最大电压，但是具有类似的电流携带能力。例如，这可以通过使用由交替的p-型层和n-型层组成的漂移区来实现，使得结的耗尽区延伸通过漂移区。
因为器件本身能够抵抗高电压，边缘末端也必需承受高电压。实际上，RESURF器件可以典型地承受是相应的非RESURF器件的1D击穿电压几倍高的电压，并且这提出了关于边缘末端的主要问题。
为了实现，边缘末端结构典型地需要至少是所述结构的深度的两倍宽，以允许电压在足够大的区域上下降。因此，尽管当与传统器件相比时将要求更多数量的浮置区域，与图2中所示类似的浮置区域方式是合适的。
然而，在这些方法中存在以下问题：因为当靠近较低和较高电压区域时，边缘末端经历未知环境条件的组合，表面电荷的可变效果可能在这些器件中是显著的。这引入了可能会影响边缘末端的可变电势分布。
为了补偿该可变性，需要将边缘末端结构保守地设计为比考虑到可能的不利条件所需的结构更大。
发明内容
根据本发明，提出了一种具有边缘末端结构的半导体器件，包括：
半导体本体，具有相对的第一和第二主表面；
半导体本体的有源区域，限定了至少一种半导体部件；
有源区域外部的边缘末端区域，其中所述边缘末端区域包括：
半导体本体中的多个浮置场区域；
浮置场区域上的第一主表面上的绝缘层；以及
至少一个场板，在连接点处穿过绝缘层与边缘末端区域中的第一主表面相连，并且从所述连接点向内向多个浮置场区域上的有源区域延伸。
通过将场板从连接点在多个浮置区域上向内延伸，所使用的场板取与连接点处的电压类似的电压，所述电压与内部场区域或场板下面区域的电压明显不同。该电压能够显著地减小氧化效果和边缘末端结构上的表面电荷。同样，在几个浮置区域上延伸的多个场板的使用允许使用更大的场板来辅助制造。
在实施例中，浮置场区域是第一主表面处的第一导电类型的半导体区域。
与第一导电类型相反的第二导电类型的半导体本体的下部区域可以位于浮置场区域下面，下部区域可以通过比下部区域和浮置场区域更低掺杂的间隔区域与浮置场区域隔离。
低掺杂的间隔区域可以从边缘末端区域延伸到有源区域中，并且可以作为有源区中的漂移区。按照这种方式在有源区域和边缘末端区域中使用相同的结构，便于制造。
间隔区域可以包括与第二导电类型的区域交替的第一导电类型的区域，这两个区域均比浮置场区域和下部区域的掺杂低。
间隔区域可以包括与第二导电类型的横向延伸区域垂直交替的第一导电类型的横向延伸区域。
替换地，间隔区域可以包括与第二导电类型的区域横向交替的、从浮置场区域向下部区域垂直延伸的第一导电类型的区域。
在另一种结构中，间隔区域包括在横向和垂直两个方向上与第二导电类型的区域交替的第一导电类型的多个区域。
所述器件可以包括按照相距有源区增加的距离间隔开的多个场板，相邻场板之间所述或每一个间隙设置在浮置场区域上。这可以增加稳定性。
在特别优选的实施例中，可以将相邻场板之间的所述或每一个间隙设置在接合区域上。接合区域是比其他浮置场区域更大宽度的浮置场区域。
相邻浮置场区域之间的间隔可以在相距有源区更大距离处比更靠近有源区处的边缘区域中更大。
附图说明
为了更好的理解本发明，现在将参考附图并且只作为示例来描述实施例，其中：
图1示出了说明场聚集的现有技术器件的示意图；
图2示出了根据比较示例的方法；
图3示出了根据另一个比较示例的方法；
图4是通过根据本发明的半导体器件的第一实施例的侧剖图；
图5是图4结构的半导体本体的顶视图；
图6是使用中的图4的结构的说明；
图7是通过根据本发明的半导体器件的第二实施例的侧剖图；
图8是通过根据本发明的半导体器件的第三实施例的侧剖图；
图9是通过根据本发明的半导体器件的第四实施例的侧剖图；
图10是通过根据本发明的半导体器件的第五实施例的侧剖图；以及
图11是通过根据本发明的半导体器件的第六实施例的侧剖图。
附图只是示意性的，并且没有按比例绘制。在不同的图中，相同的部件用相同的参考数字表示。
具体实施方式
参考图4和图5，根据本发明第一实施例的半导体器件20形成于n型重掺杂的n+衬底22上。外延层28形成于衬底上，包括漂移区24和重掺杂p-型区域26。半导体器件的正面限定了第一(顶部)主表面34，以及背面限定了与第一主表面相对的第二(底部)主表面36。衬底22和外延层28限定了具有下部区域22(衬底)的半导体本体22和28，并且外延层28作为间隔层。
应该理解的是在替换实施例中，可以仅使用半导体本体，可以对其进行掺杂以无需要求使用外延层28就提供间隔。
在有源区30中，在图4中只示出其边缘，将轻掺杂n-型漂移区24形成于n型衬底上面，其上是在第一主表面34处的重掺杂p-型区26。在该实施例中，漂移区简单地是n-型区域。
将RESURF结构70设置在所述器件的有源区30的漂移区24中。RESURF结构70用于当器件截止时来耗尽漂移区24，这增加了可以通过有源区支持的电压，因此增加对于有效边缘末端结构的需要。下面讨论它们的结构。
有源区30可以包括任意的半导体器件，例如二极管、闸流晶体管或诸如绝缘栅极晶体管之类的晶体管，所述绝缘栅极晶体管可以是水平或垂直的MOSFET、双极型器件或这些器件的组合。
在有源区30的边缘周围设置了边缘末端区域32，在图4和图5中只示出其一部分。
边缘末端区域32包括下部衬底区域22，并且其上是结构如下的间隔区域38。
将多个柱子40形成于有源区30的边缘周围的间隔区域38中，柱子40限定了它们之间的n-型硅的中间区域42。应该注意的是在实施例中，RESURF结构70刚好与在边缘末端区域32中使用的柱子40相同，这允许它们使用相同的工艺同时制造。
如图5所示，将柱子40在有源区30周围间隔开。注意为了清楚起见，图5只示出了半导体本体而没有示出以下参考图4所述的绝缘层52或绝缘层上面的场板54。
在图4的实施例中，将柱子40和RESURF结构70形成于从第一主表面34延伸通过浮置区域46和中间区域42直至衬底22的沟槽中。如果需要，所述柱子可以略微延伸至衬底22中。所述柱子40包括中心绝缘区48和沟槽侧壁上的薄p-型层50。
将浮置区域46设置在第一主表面34处的柱子的顶部处。浮置区域46是p-型重掺杂的p+区域。
在第一主表面34上面是绝缘层52，其上是通过绝缘层52中作为连接点的各个接触孔56与下面的浮置区域46相连的多个场板54。
注意，具体地，场板54在多个浮置区域46上从接触孔56向内延伸至有源区30。
在该实施例中，中心覆盖区域53覆盖了浮置区域46的中心，确保在浮置区域46的中心处不存在接触孔56。这样，接触孔56处于环形形式。注意，这样的覆盖区域并非是必需的。
根据图4的结构可以如下制造，其中将省略用于形成有源器件的处理的描述。
首先，将n-掺杂外延层28形成于n+掺杂衬底22上。外延层28可以是n-型轻掺杂的，通过覆盖掺杂或掩模以只在特定区域(例如，在边缘末端区域中而不在有源区)中提供掺杂。
然后，通过在外延层28顶部处的第一主表面34中进行注入来形成重掺杂p-型区域26和浮置区域46。接下来，形成沟槽41，例如通过选择性外延生长或通过其中从气相扩散掺杂剂的扩散工艺来在侧壁上形成p+型层50。然后用绝缘体48填充所述沟槽。
在所使用的器件中，n-型掺杂最高至1016cm-3的范围，而p-型掺杂在1016至1018cm-3附近。p+型层可以更重地掺杂。
形成绝缘层52，方便的是二氧化硅，并且对其进行构图以暴露有源区30并且形成接触孔56。然后，可以形成并且构图场板54。
使用中，所述结构可以提供有用的边缘末端。
考虑将有源区域30的p+型层26保持为0V并且将n+衬底22保持为100V的情况(如图6所示)。那么，有源区域外边的第一浮置区域58可以处于大约20V的电压。然而，场板与显著地远离有源区30的浮置区相连，并且因此处于更接近衬底22的电势。在示例中，场板是75V的电势。
这样，通过提供从连接点56在几个浮置区域46上向内延伸的场板，使用中的场板的电势显著地是正的，比如果场板与相邻浮置区相连(比较US 6,376,890)、或如果场板从浮置区向外延伸(比较Baliga的教科书)更是正的。实际上，在其中场板向外延伸的传统情况下，场板相对于浮置区是负的。
通常，在没有场板上的电势的情况下，当电压上升时，有源区30和相邻浮置区58之间的穿通(punch through)将出现在沿表面路径60的表面上。通过当间隔层变为完全耗尽时的空穴流(hole flow)来发生这两个p-型区域之间的穿通。因为穿通发生在与绝缘层52的氧化物相邻的表面处，氧化物界面电荷64或任意其他表面电荷对于穿通具有显著影响，因此对于发生穿通的实际电压具有显著影响。
场板上的负电压只吸引空穴，因此穿通仍然发生在表面处。
不局限于理论，本发明考虑了场板上的较大正电势将增加发生穿通的电压，并且还引起穿通在除了表面之外的沿路径62的表面以下发生。
通过将穿通路径62与表面分离，包括氧化物半导体界面电荷的表面电荷的影响变得显著减少，因此穿通电压变得更不依赖于不能很好控制的制造和操作特征。
在普通的半导体器件中，不得不非常保守地设计半导体器件以允许最差情况场景。通过使用本发明的方法，穿通电压对于表面电荷的依赖性变得较小，并且这允许使用比其他情况下更积极的小设计。
表面以下发生的穿通也可以增加设计的热可靠性。
本发明另外的益处是场板的实际偏置与现有技术结构相比更不重要。这意味着场板的布局不是严格的，使得它们易于制造。
与现有结构相比要求更少量的场板和接触，并且这允许更小的边缘末端区域。
该实施例允许减少额外开销，即边缘末端结构所占用的附加面积。
当光刻限制不允许形成相同尺寸的间隙和接触时，本实施例的方法是特别有用的。
图7示出了具有一些更进一步的改进的本发明另外的实施例。
如图7中所示，将多个场板结构54从有源区30向外设置，每一个场板在多个浮置区域46上延伸。间隙72间隔场板54。
然而，如图7所示，该器件与图4器件不同之处在于：在相邻场板之间的间隙72下面，浮置区域采取不同的结构，在相邻柱子40之间具有接合区域74。该接合区域74是横越两个相邻柱子40之间间隙的较大的浮置区域46。接合区域74减小了相邻场板之间的间隙72下面的相邻柱子之间的电压。因为这些间隙72较少受到场板的保护，太早的穿通或甚至破坏性的击穿可能另外在这些区域发生，这种可能性在该实施例中将减小。这进一步增加了图4结构上的可靠性。
图7还示出了另外的改进。相邻浮置区域46之间的间隔57在外部浮置区域46之间比内部浮置区域46之间更大，其中外部浮置区域在比内部非浮置区域更远离有源区30的边缘区域32中。
尽管图7只示出了两个不同的间隔，优选实施例具有在从有源区30通过边缘区域32向外移动的浮置区域46之间的逐渐增加的间隔。
另外的变化在图8中示出，图8示出了与图4和图7不同的RESURF结构70和柱子40。在图8的结构中，每一个柱子40和RESURF结构70具有用p-型区域80填充沟槽40、70的沟槽41的形式。
同样，在两个有源区30中均使用相同结构以形成RESURF结构70和边缘末端区域32以形成柱子40。
图9示出了另外的替换实施例，其中将RESURF结构形成为多个水平p-型层90和n-型层92。没有柱子40。将浮置区域46如前所述设置在有源区30周围。
注意在该结构中，仍然使用接合区域74，但是所述接合区域74不再接合相邻柱子，而是只具有与浮置区域46相同但是宽度更大的结构。
这种类型的分层RESURF结构可以通过使用多步外延和注入步骤来实现。
图10示出了另外的组合。外部场板54(也就是说远离有源区30的场板)指向内部，即从接触孔56在多个浮置区域46上向有源区30延伸。
但是，最内部的场板96在其内侧末端(即最接近有源区30的一端)而非离有源区最远的外边缘处被连接。
尽管图10只示出了按照这种方式连接的最内侧的场板96，这不是必需的，也可以让多个内侧场板这样相连，让接触孔位于场板的内侧末端(或甚至其他地方)，并且远离有源区30地延伸，其中只有外部场板54在其外边缘处与接触孔相连。
在图11中示出了另外的修改，将图4、7、8和10的柱子用垂直和横向间隔的多个p-掺杂区域98来代替，作为有源区30中的RESURF区。
本领域普通技术人员应该理解，本发明不局限于上述实施例。
具体地，p-型和n-型掺杂层可以互换。
不必将浮置区域46设置为边缘末端结构中的分离柱子或区域，而是可以将其设置为有源区周围的环，或者所要求的任意其他形式。
可以在有源区中使用其他形式的有源器件，包括具有沟槽栅极的结构、复杂RESURF结构、或者实际上这些结构的任意组合。有源区可以包括场效应和/或双极型器件。
可以将多种绝缘材料用于绝缘层52和绝缘区域48，包括二氧化硅、氮化硅、旋涂玻璃或任意其他绝缘材料。同样，场板可以由金属、诸如金属硅化物之类的金属合金化合物、自对准金属硅化物、多晶硅或提供有效导体的其他材料组成。
可以使用多种制造方法，包括通过刻蚀沟槽并且填充沟槽形成间隔区域38的交替部分，通过多层外延生长和注入、或者任意其他方法。
所使用的半导体没有限制，并且可以使用硅和任意半导体材料。
另外，尽管在大多数实施例中将RESURF结构(在存在的情况下)设置在浮置场区下面，对于这种情况没有绝对的要求，优选地，可以对RESURF结构独立地进行构图。
尽管已经参考RESURF结构描述了实施例，还可以将本发明应用于没有柱子、片或区域的非RESURF结构。

Claims (10)

1.一种具有边缘末端结构的半导体器件，包括：
半导体本体(22，28)，具有相对的第一(34)和第二(36)主表面；
半导体本体的有源区域(30)，限定了至少一种半导体部件；
有源区域(30)外部的边缘末端区域(32)，其中所述边缘末端区域(32)包括：
多个横向间隔的浮置场区域(46)；
第一主表面(34)上的绝缘层(52)；以及
至少一个场板(54)，在连接点(56)处穿过绝缘层(52)与边缘末端区域(32)中的第一主表面(34)相连，并且从所述连接点(56)在多个浮置场区域(46)上向内向有源区域(30)延伸，其中：
浮置场区域(46)是第一主表面(34)处的第一导电类型的半导体区域，将浮置场区域(46)设置为边缘末端区域(32)中的第一主表面处的排列为二维阵列的区域；
半导体本体的与第一导电类型相反的第二导电类型的下部区域(22)位于浮置场区域(46)下面，下部区域(22)通过比下部区域(22)和浮置场区域(46)更低掺杂的间隔区域与浮置场区域(46)隔离。
2.根据权利要求1所述的半导体器件，其中低掺杂的间隔区域从边缘末端区域(32)延伸到有源区域(30)中，并且作为有源区域中的漂移区域(24)。
3.根据权利要求1所述的半导体器件，其中间隔区域包括与第二导电类型的区域(42；92)交替的第一导电类型的区域(40；90)，第一和第二导电类型的交替区域(40，42；90，92)均比浮置场区域(46)和下部区域(22)的掺杂低。
4.根据权利要求3所述的半导体器件，其中间隔区域包括柱子(40)，所述柱子(40)包括垂直地延伸穿过间隔区域至下部区域(22)的第一导电类型的区域(50，80)，限定了柱子(40)之间的第二导电类型的区域(42)。
5.根据权利要求4所述的半导体器件，其中在边缘末端区域中，将柱子(40)设置在浮置场区域(46)下面。
6.根据权利要求3所述的半导体器件，其中间隔区域包括与横向延伸的第二导电类型的区域(92)垂直地交替的横向延伸的第一导电类型的区域(90)。
7.根据权利要求3所述的半导体器件，其中间隔区域包括在横向和垂直两个方向上与第二导电类型的区域(42)交替的多个第一导电类型的区域(98)。
8.根据权利要求1所述的半导体器件，其中将浮置场区域(46)设置为边缘末端区域(32)中的第一主表面处的排列为六边形阵列的区域。
9.根据权利要求1所述的半导体器件，包括与有源区域(30)间隔开的多个场板(54)，限定了相邻场板之间的至少一个间隙(72)，
其中将相邻场板之间的所述至少一个间隙(72)设置在接合区域(74)上，所述接合区域(74)是比其他浮置场区域(46)更大宽度的浮置场区域。
10.根据权利要求1所述的半导体器件，其中相邻浮置场区域(46)之间的间隔在相距有源区域(30)更大距离处比更靠近有源区(30)处的边缘末端区域(32)中更大。
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GIAN-FRANCO DALLA BETTA ET AL.A Novel Silicon Microstrip Termination Structure With All P-Type Multiguard and Scribe-Line Implants.IEEE TRANSACTIONS ON NUCLEAR SCIENCE49 4.2002,49(4),1712-1716.
GIAN-FRANCO DALLA BETTA ET AL.A Novel Silicon Microstrip Termination Structure With All P-Type Multiguard and Scribe-Line Implants.IEEE TRANSACTIONS ON NUCLEAR SCIENCE49 4.2002,49(4),1712-1716. *

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US7859076B2 (en) 2010-12-28
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US20100001362A1 (en) 2010-01-07
CN101180739A (zh) 2008-05-14

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