CN101162707B - 半导体器件结构及基于晶体管密度的应力层的形成方法 - Google Patents

半导体器件结构及基于晶体管密度的应力层的形成方法 Download PDF

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CN101162707B
CN101162707B CN2007101802175A CN200710180217A CN101162707B CN 101162707 B CN101162707 B CN 101162707B CN 2007101802175 A CN2007101802175 A CN 2007101802175A CN 200710180217 A CN200710180217 A CN 200710180217A CN 101162707 B CN101162707 B CN 101162707B
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陈向东
杨海宁
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Abstract

本发明提供一种半导体器件结构及一种用于增加包括在半导体器件中的晶体管的载流子迁移率的方法，该方法包括在多个晶体管上方形成引起应力的层，该晶体管形成在不同晶体管密度的区域中，其中该引起应力的层根据晶体管密度而形成为不同厚度，使得在增大的晶体管密度的区域中该引起应力的层更厚以及在减小的晶体管密度的区域中该引起应力的层更薄。

Description

半导体器件结构及基于晶体管密度的应力层的形成方法
技术领域
本发明总地涉及半导体器件工艺技术，且更特别地，涉及互补金属氧化物半导体(CMOS)器件中的结构及基于晶体管密度的应力层的形成方法。
背景技术
最近应变工程(strain engineering)技术已经应用于CMOS器件制造，从而在P型MOS(PMOS)器件中提供相对于N型MOS(NMOS)器件不同的应力。例如，第一型的氮化物衬(liner)形成在CMOS器件的PFET上方，而第二型的氮化物衬形成在CMOS器件的NFET上方。更具体地，已经发现，PFET沟道中压缩应力的应用提高其中的载流子(空穴)迁移率，而NFET沟道中拉伸应力的应用提高其中的载流子(电子)迁移率，导致更高的导通电流(on-current)和产品速度。因此，以获得压缩应力(compressive stress)的方式形成PFET器件上方的第一型氮化物衬，而以获得拉伸应力(tensile stress)的方式形成NFET器件上方的第二型氮化物衬。相反，当相反类型的应力分别施加于NFET和PFET器件时，器件性能会降低。
对于这种使用压缩/拉伸衬的CMOS器件，传统方法是形成给定厚度的氮化物层，而不考虑特定位置中晶体管的密度。然而，除了应力层的厚度以外，载流子迁移率提高的程度也是邻近器件栅极的应力层材料的宽度的函数。换句话说，相对孤立的器件将具有更大的邻近栅极的应力层材料的宽度，因为距最近的晶体管的栅极的距离增大了。此外，在传统工艺中，由于沉积技术的特性，应力层趋向于在成套区域(nested region)中比在孤立区域中更薄。结果，施加于这种孤立晶体管的沟道的应变程度相对大于施加于“成套”晶体管的沟道的应变。在载流子迁移率增强的方面而言，这能进而导致成套和孤立晶体管之间的性能不同。因此，理想的是能够以自对准方式形成用于CMOS器件的引起应力的衬并能提高成套和孤立晶体管器件的性能一致性。
发明内容
通过一种用于增加包括在半导体器件中的晶体管的载流子迁移率的方法，前面讨论的早先技术的缺陷和不足得到克服或减轻。在示范性实施例中，该方法包括在多个晶体管上方形成引起应力的层，该晶体管形成在不同晶体管密度的区域中，其中引起应力的层依赖晶体管密度而形成为不同厚度，使得在增大的晶体管密度的区域中引起应力的层更厚以及在减小的晶体管密度的区域中引起应力的层更薄。
在另一实施例中，一种用于增加包括在半导体器件中的晶体管的载流子迁移率的方法包括在半导体衬底上形成多个MOS(金属氧化物半导体)晶体管，所述晶体管形成在不同晶体管密度的区域中，以及通过高密度等离子体(HDP)沉积工艺在多个晶体管上方形成引起应力的层。引起应力的层依赖晶体管密度而形成为不同厚度，使得在增大的晶体管密度的区域中引起应力的层更厚和在减小的晶体管密度的区域中引起应力的层更薄。
在又一实施例中，一种半导体器件结构包括：形成在半导体衬底上的多个MOS(金属氧化物半导体)晶体管，该晶体管形成在不同晶体管密度的区域中；以及形成在多个晶体管上方的引起应力的氮化物层。引起应力的氮化物层依赖晶体管密度而具有不同的厚度，使得在增大的晶体管密度的区域中引起应力的层更厚和在减小的晶体管密度的区域中引起应力的层更薄。
在又一实施例中，一种半导体器件结构包括：形成在半导体衬底上的多个MOS(金属氧化物半导体)晶体管，所述晶体管形成在不同晶体管密度的区域中；以及形成在多个晶体管上方的引起应力的氮化物层。引起应力的氮化物层对于所述多个晶体管产生作为晶体管密度的函数的不同的载流子迁移率增强，使得相对于减小的晶体管密度的区域在增大的晶体管密度的区域中得到更高的载流子迁移率增强。
附图说明
参考示范性的附图，其中在一些图中相似的元件标注类似的附图标记：
图1为示范性MOS晶体管器件的横截面图，由于应力层提供了施加到沟道的机械应力，该MOS晶体管器件具有提高的载流子迁移率；
图2为框图，示出了根据本发明实施例的用于形成自对准的基于晶体管密度的应力层以提高载流子迁移率的示范性工艺流程200；
图3为半导体器件的横截面图，该半导体器件具有形成于其中的成套晶体管的第一区域和第二孤立的区域，每个区域都包括通过HDP沉积同时形成在其上的单个氮化物层；
图4(a)至(c)为HDP形成的氮化物层的扫描电子显微镜(SEM)照片，在其中层的厚度根据相邻晶体管间的间距而改变；
图5为由图4(a)至4(c)得到的氮化物层厚度数据的图解总结。
具体实施方式
在这里公开的为一种在CMOS器件中形成基于晶体管密度的应力层从而提高器件均匀性的方法。简单地说，在此公开的实施例利用这样的效应，即晶体管增强的程度与施加的应力的程度成比例，该施加的应力的程度又与产生施加应力的该层的厚度成比例。因此，晶体管器件更密集的地方比晶体管器件更稀疏的地方形成更大厚度的相关的应力产生层。也就是，形成应力层的方式为半导体衬底上特定位置的应力层的厚度是在该位置处晶体管器件之间的间距的函数。更具体地，应力层的厚度随减小的晶体管间距(节距)而增大。在一示范性实施例中，其通过氮化物材料的高密度等离子体(HDP)沉积而实现，如下文所述。
首先参考图1，示出了示范性MOS晶体管器件100(例如，NMOS、PMOS)的横截面图，该MOS晶体管器件100由于应力层提供了施加到沟道的机械应力(其方向依赖于晶体管是NMOS器件或PMOS器件)而具有提高的载流子迁移率。如图所示，器件100形成在半导体衬底102上(例如，硅、绝缘体上硅、硅锗等)。在图1所描绘的工艺的特定阶段中，自对准硅化物(salicide：self-aligned silicide)接触104已经形成在器件的源极和漏极区域、以及形成在栅绝缘层108上方的栅电极106之上。
图1中还示出，引起应力的氮化物层110形成在栅结构、侧壁间隔壁(spacer)112、硅化源极/漏极区域和衬底102的邻近区域之上。应力层110在第一层间介电(ILD)层在其上沉积之前形成。通过层110施加的应力(由大箭头指示)转换到器件的沟道(由小箭头指示)从而提高器件的载流子迁移率(因而以及Ion)。如果器件100为N型器件，则氮化物层110为提供拉伸应力的成分；如其为P型器件，则氮化物层110配置为提供压缩应力。
然而，如上面所述，传统地应力层110以在晶体管器件上方导致基本均匀的厚度的方式形成，而不考虑它们之间的节距(pitch)。相应地，图2为框图，示出了根据本发明实施例的用于形成自对准的基于晶体管密度的应力层以提高载流子迁移率的示范性工艺流程200。如框202中所示，MOS晶体管的源极/漏极区域、栅堆叠材料(例如，栅绝缘层、多晶硅栅电极)和侧壁间隔壁(例如，氮化硅)根据传统器件工艺技术形成在衬底上。框204中进一步示出，依照现有硅化技术，还形成用于栅导体、源极和漏极区域的自对准硅化物接触。
接着，如框206中所示，氮化物应力层形成在器件上从而提供适当类型的应力(压缩或拉伸)以用于提高载流子迁移率。然而，与传统应力层形成技术例如化学气相沉积(CVD)或物理气相沉积(PVD)相反，应力衬采用高密度等离子体(HDP)工艺形成。HDP可例如在设定为提供约200W至约5000W范围内的等离子体功率的HDP腔中进行，且在示范性实施例中，以约400W的高频功率水平和约3600W的低频功率水平进行。
用于形成氮化物应力层的其它示范性HDP工艺参数包括约310sccm的N2流速、约230sccm的氩流速和约90sccm的硅烷(SiH4)前驱体流速。衬底在沉积期间以约400℃的温度加热。此外，HDP工艺的加热部分实行约50秒且HDP工艺的沉积部分实行约15秒。依赖特定工艺条件和在衬底的特定位置上晶体管器件的密度，氮化物应力层厚度能够以约20nm至约150nm形成。一旦氮化物应力衬通过HDP沉积形成，附加工艺然后可以如本领域所公知地进行，例如ILD层形成、通路刻蚀和填充、及上布线层形成(框208)。
通过HDP沉积的使用，氮化物应力衬因此在衬底表面之上以相对于晶体管器件之间的距离或节距成反比的关系以可变厚度形成。即，节距越短，相邻栅结构之间的氮化物应力层的厚度越大。图3为半导体器件300的横截面图，该半导体器件具有形成有密集“成套”晶体管的第一区域302和第二孤立区域304。区域302和304都包括通过HDP沉积同时形成于其上的单个氮化物层。然而，能够看出，成套区域302中相邻的栅结构之间的氮化物层306的厚度(t1)比孤立区域304中相邻的栅结构之间的氮化物层306的厚度(t2)大。
相对于孤立区域304中的器件，成套区域中应力层306的额外厚度弥补了应力层宽度(即，栅-栅间距)的相对减小。结果，施加于晶体管沟道的应力的程度在整个器件上更平衡。
已经发现，到目前为止，本发明所公开的通过HDP沉积形成应力层的方法尤其适合于压缩应力层。因此，在提高载流子迁移率方面，HDP沉积工艺对PMOS器件尤其理想。然而，应该理解的是，HDP沉积技术的后续改进可使该工艺对形成NMOS器件中提高电子迁移率的拉伸氮化物层同样理想。
最后，图4和5示出了根据上面所述的技术形成在多个PFET器件之上的HDP沉积的压缩氮化物层的氮化物厚度的结果。具体地，图4(a)至(c)为HDP形成的氮化物层的扫描电子显微镜(SEM)照片，其中其厚度根据相邻晶体管间的间距而改变。例如，在相邻PFET之间的节距约为245nm的器件的成套区域中，所得氮化物层的厚度约139nm，如图4(a)所示。随着图4(b)中节距增大至约280nm，所得氮化物层的厚度减少到约125nm。接着如图4(c)所示，在约315nm节距的情况下，氮化物层的厚度进一步减小到约117nm。在图5中数据以图形形式总结。尽管图中未示出，器件的孤立区域中的氮化物的厚度为约107nm。
虽然参考优选的实施例描述了本发明，然而本领域的一般技术人员可以理解，在不脱离本发明的范围的情况下，可以作出不同变化且其元件可被等同物替换。此外，在不脱离其本质范围的情况下，根据本发明教导，可进行一些修改以适应特定情形或材料。因此，本发明不意图受限于公开为为了实行本发明而想到的最佳模式的具体实施例，而是本发明将包括在随附的权利要求范围内的所有实施例。

Claims (17)

1.一种用于增加包括在半导体器件中的晶体管的载流子迁移率的方法，所述方法包括：
在多个晶体管之上形成引起应力的层，所述晶体管形成在半导体衬底上并形成在不同晶体管密度的区域中；
其中所述引起应力的层根据所述晶体管密度而以不同厚度形成，使得所述引起应力的层在具有增大的晶体管密度的区域中较厚以及在具有减小的晶体管密度的区域中较薄，
其中与具有增大的晶体管密度的区域相比，在具有减小的晶体管密度的区域中邻近晶体管的栅极的应力层的宽度更大。
2.如权利要求1的方法，其中所述引起应力的层通过高密度等离子体HDP工艺形成。
3.如权利要求2的方法，其中所述引起应力的层包括氮化物材料。
4.如权利要求3的方法，其中所述引起应力的层为压缩氮化物材料且所述多个晶体管包括P型器件。
5.如权利要求3的方法，其中所述引起应力的层为拉伸氮化物材料且所述多个晶体管包括N型器件。
6.如权利要求2的方法，其中所述HDP工艺采用约310sccm的N2流速、约230sccm的氩流速和约90sccm的硅烷SiH4前驱体流速执行。
7.如权利要求2的方法，其中所述衬底在沉积期间在约400℃的温度加热。
8.如权利要求2的方法，其中HDP工艺的加热部分执行约50秒且HDP工艺的沉积部分执行约15秒。
9.一种用于增加包括在半导体器件中的晶体管的载流子迁移率的方法，所述方法包括：
在半导体衬底上形成多个金属氧化物半导体晶体管，所述晶体管形成在不同晶体管密度的区域中；及
通过高密度等离子体HDP工艺在所述多个金属氧化物半导体晶体管之上形成引起应力的氮化物层；
其中所述引起应力的氮化物层根据所述晶体管密度以不同厚度形成，使得所述引起应力的层在具有增大的晶体管密度的区域中较厚以及在具有减小的晶体管密度的区域中较薄，
其中与具有增大的晶体管密度的区域相比，在具有减小的晶体管密度的区域中邻近晶体管的栅极的应力层的宽度更大。
10.如权利要求9的方法，其中所述引起应力的层为压缩氮化物材料且所述多个金属氧化物半导体晶体管包括PMOS器件。
11.如权利要求9的方法，其中所述引起应力的层为拉伸氮化物材料且所述多个金属氧化物半导体晶体管包括NMOS器件。
12.如权利要求9的方法，其中所述HDP工艺采用约310sccm的N2流速、约230sccm的氩流速和约90sccm的硅烷SiH4前驱体流速执行。
13.如权利要求9的方法，其中所述衬底在沉积期间在约400℃的温度加热。
14.如权利要求9的方法，其中HDP工艺的加热部分执行约50秒且HDP工艺的沉积部分执行约15秒。
15.一种半导体器件结构，包括：
形成在半导体衬底上的多个金属氧化物半导体晶体管，所述晶体管形成在不同晶体管密度的区域中；及
形成在所述多个金属氧化物半导体晶体管之上的引起应力的氮化物层；
其中所述引起应力的氮化物层根据所述晶体管密度具有不同厚度，使得所述引起应力的层在具有增大的晶体管密度的区域中较厚以及在具有减小的晶体管密度的区域中较薄，
其中与具有增大的晶体管密度的区域相比，在具有减小的晶体管密度的区域中邻近晶体管的栅极的应力层的宽度更大。
16.如权利要求15的结构，其中所述引起应力的层为压缩氮化物材料且所述多个金属氧化物半导体晶体管包括PMOS器件。
17.如权利要求15的结构，其中所述引起应力的层为拉伸氮化物材料且所述多个金属氧化物半导体晶体管包括NMOS器件。
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