CN101140900A - 形成半导体存储器件位线的方法 - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 14
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- 230000004888 barrier function Effects 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000006911 nucleation Effects 0.000 claims description 2
- 238000010899 nucleation Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
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- 239000003795 chemical substances by application Substances 0.000 description 6
- 239000004744 fabric Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Abstract
一种形成半导体存储器件位线的方法，实施如下。在半导体衬底上形成第一层间绝缘层，其中在所述半导体衬底中已形成底层结构。蚀刻第一绝缘层的区域，从而形成接触孔，半导体衬底的接触区域通过该接触孔被暴露。在包括接触孔的整个表面上沉积低电阻钨层，从而形成触点。实施CMP工艺以减小低电阻钨层的表面粗糙度。使层间绝缘层上的低电阻钨层图案化为位线金属线图案，形成位线。
Description
交叉引用相关申请
本发明要求享有于2006年9月6日提交的申请号为10-2006-085747的韩国专利优先权，并通过引用将其全部内容并入本文。
技术领域
本发明涉及半导体存储器件，更具体而言，涉及一种形成半导体存储器件位线的方法，该方法能降低位线的电阻。
背景技术
最近，进行了对于亚80nm器件的研究。在亚80nm技术中，利用光刻工艺形成图案提出了一场艰难的挑战。换句话说，用于100nm器件的使用氟化氪(KrF，248nm)光源和活性离子蚀刻(RIE)技术的曝光技术似乎达到了其极限。
对于100nm器件的情况(例如，DRAM)，利用采用KrF光源的光刻工艺形成临界层。对于金属层，大部分图案采用RIE形成。这些工艺技术已用于大规模生产，迄今为止未出现显著的问题。但是，对于亚80nm器件的情况，利用现有的KrF和RIE方法实施图案形成过程是不可能的。
具体地，对于具有100nm器件的设计标准中最小节距的位线的情况，，该节距较亚80nm器件中的最终检查临界尺寸(FICD)更低。在这种情况下，KrF达到其极限。因此，具有更小波长的氟化氩(193nm)光源被考虑用于下一代器件。
由于光刻胶的重要性，已经对ArF的使用进行了大量的研究。这是因为由于ArF光源较小的波长因而具有高的分辨率，但是必须使用薄的阻剂(resist)以保持小的焦深(DOF)容限。但是，当时实施RIE蚀刻工艺时ArFd阻剂对阻剂具有低的蚀刻选择性。因此，预期在实施蚀刻工艺时将存在困难。即，如果使用具有低选择性的薄阻剂，蚀刻工艺的容限可被显著减小。但是，对于将来纳米级器件，该蚀刻工艺将具有局限性。
为了增加ArF光源和阻剂之间的蚀刻工艺容限，已经对氧化层图案化、沉积金属和接着实施化学机械抛光(CMP)的大马士革工艺进行了研究。通常，这是由于蚀刻氧化层而不是金属或氮化物层具有优势，因为同样的阻剂厚度具有高的选择性。即，大马士革工艺可成为用于增加蚀刻过程工艺容限的基本方法。而且，大马士革工艺可应用于微型器件的制造，因为关于光刻胶的工艺容限在光学过程中变大。
此外，由于器件小型化，采用具有较小电阻率的材料例如钨代替多晶硅和硅化钨，以提高器件的速度。这种向具有较低电阻率金属的发展通常首先应用于位线，因为其往往是在器件中具有最小的节距。
发明内容
本发明的实施方案涉及一种形成半导体存储器件位线的方法，其中通过RIE方法，利用低电阻的钨形成触点(contact)和位线，因此减少位线的薄层电阻值、简化工艺步骤，并且提高TAT。
根据本发明的实施方案，一种形成半导体存储器件位线的方法包括步骤：在其中已形成底层结构的半导体衬底上形成第一绝缘层；蚀刻第一绝缘层的区域，从而形成接触孔，半导体衬底的接触区域通过该接触孔被暴露；在接触孔的侧壁和底部表面上形成阻挡金属层；在包括接触孔的整个表面上沉积低电阻钨层，从而形成接触；实施CMP工艺以减小低电阻钨层的表面粗糙度；和在位线金属线图案中的第一绝缘层上图案化低电阻钨层，形成位线。
方法还包括在形成接触孔和沉积低电阻钨层的步骤前，在接触孔的侧壁和底部表面上形成阻挡金属层的步骤。
可以利用电阻值为9～12Ω·μm的钨来形成厚度为1500～2000埃的低电阻钨层。
在沉积低电阻钨层的步骤中，掺杂B2H6或者SiH4以产生核。
附图说明
图1～6是举例说明根据本发明实施方案形成半导体存储器件位线的方法的截面图。
具体实施方式
参考图1，在半导体衬底100上形成第一绝缘层101，其中在所述衬底中已形成底层结构；利用光刻胶图案蚀刻第一绝缘层101，使得底层结构和触点相互接触的区域被暴露，从而形成接触孔。除去光刻胶图案。
参考图2，实施预处理清洗过程以除去底层结构上任何剩余的残留物。在包括接触孔的整个表面上形成阻挡金属层102。阻挡金属层102的作用是防止在后续接触过程中接触材料扩散入周围材料中。
参考图3，在阻挡金属层102上形成低电阻钨层103。此时，利用低电阻钨层103填充接触孔以形成触点。形成的低电阻钨层103厚度为1500～2000埃，其包括某些在后续的化学机械抛光(CMP)工艺中被除去的材料。低电阻钨层103的电阻值可以为9～12Ω·μm。在钨沉积步骤的成核步骤中，掺杂B2H6或/和SiH4以形成低电阻钨层103。这样控制钨核的形成以增加块体(bulk)钨的晶粒尺寸。如果在位线中使用低电阻钨层103，那么薄层电阻Rs减小。
参考图4，实施CMP工艺以抛光低电阻钨层103的表面从而降低粗糙度。控制CMP工艺，使得仅去除低电阻钨层103的表面而不暴露阻挡金属层102。
参考图5，在低电阻钨层103上形成包括SiON层、α-碳层和抗反射层的硬掩模图案104。
参考图6，使用硬掩模图案蚀刻低电阻钨层103。在除位线区域的其它区域中，阻挡金属层102连同低电阻钨层103一起被蚀刻。在整个表面上形成第二绝缘层105。通过HDP工艺或SOG工艺形成第二绝缘层105。
如上所述，依照本发明，在形成半导体存储器件位线的过程中，通过RIE方法利用低电阻钨形成触点和位线。从而，能减小位线的薄层电阻，简化工艺步骤，并且改进TAT。
本发明的详细实施方案是例证性的并不是限制性的。可进行各种变化和修改而不背离如所附权利要求所限定的本发明的精神和范围。
Claims (6)
1.一种形成半导体存储器件位线的方法，所述方法包括：
在半导体衬底上形成第一绝缘层；
蚀刻所述第一绝缘层的区域以形成暴露部分所述半导体衬底的接触孔；
在所述接触孔上形成阻挡层；
在所述阻挡层上和所述接触孔中沉积低电阻钨层以形成接触塞；
实施化学机械抛光(CMP)工艺以抛光所述低电阻钨层，而不暴露所述低电阻钨层下的阻挡层；和
将所述低电阻钨层图案化为包括位线和接触塞的位线金属图案。
2.权利要求1的方法，其中所述低电阻钨层形成的厚度为1500～2000埃。
3.权利要求1的方法，其中所述低电阻钨层的电阻值为9～12Ω·μm。
4.权利要求1的方法，其中在钨沉积步骤的成核步骤中，通过掺杂B2H6或SiH4或二者而形成所述低电阻钨层，以增加块体钨的晶粒尺寸。
5.权利要求1的方法，其中使所述低电阻钨层图案化包括：
在所述低电阻钨层上形成包括SiON层、α-碳层和抗反射层的硬掩模图案；和
使用所述硬掩模图案蚀刻所述低电阻钨层。
6.权利要求1的方法，还包括在形成所述位线后通过HDP工艺或SOG工艺形成第二绝缘层。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060085747 | 2006-09-06 | ||
| KR1020060085747A KR100885786B1 (ko) | 2006-09-06 | 2006-09-06 | 반도체 메모리 소자의 비트라인 형성 방법 |
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| CN101140900A true CN101140900A (zh) | 2008-03-12 |
| CN100589238C CN100589238C (zh) | 2010-02-10 |
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| CN113764419A (zh) * | 2021-09-09 | 2021-12-07 | 福建省晋华集成电路有限公司 | 半导体装置及其形成方法 |
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| EP2680591B1 (en) | 2011-02-21 | 2015-11-18 | FUJIFILM Corporation | Color imaging device |
| JP5054857B1 (ja) | 2011-02-28 | 2012-10-24 | 富士フイルム株式会社 | カラー撮像装置 |
| WO2012127700A1 (ja) | 2011-03-24 | 2012-09-27 | 富士フイルム株式会社 | カラー撮像素子、撮像装置、及び撮像プログラム |
| US11329052B2 (en) | 2019-08-02 | 2022-05-10 | Applied Materials, Inc. | Method of processing DRAM |
| WO2024110839A2 (en) | 2022-11-22 | 2024-05-30 | Pfizer Inc. | Immunogenic compositions comprising conjugated capsular saccharide antigens and uses thereof |
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| KR20030000125A (ko) | 2001-06-22 | 2003-01-06 | 주식회사 하이닉스반도체 | 반도체소자의 비트라인 형성방법 |
| KR100390042B1 (ko) * | 2001-06-27 | 2003-07-04 | 주식회사 하이닉스반도체 | 반도체 소자의 비트라인 형성 방법 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113764419A (zh) * | 2021-09-09 | 2021-12-07 | 福建省晋华集成电路有限公司 | 半导体装置及其形成方法 |
| CN113764419B (zh) * | 2021-09-09 | 2023-09-05 | 福建省晋华集成电路有限公司 | 半导体装置及其形成方法 |
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| JP2008066698A (ja) | 2008-03-21 |
| US20080057688A1 (en) | 2008-03-06 |
| US7462536B2 (en) | 2008-12-09 |
| KR20080022387A (ko) | 2008-03-11 |
| KR100885786B1 (ko) | 2009-02-26 |
| CN100589238C (zh) | 2010-02-10 |
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